target/linux/ipq806x/patches-4.9/0009-spi-qup-refactor-spi_qup_io_config-in-two-functions.patch

   1 From e06f04d55752e460d8f332f28317aebc27ab1b17 Mon Sep 17 00:00:00 2001
   2 From: Matthew McClintock <mmcclint@codeaurora.org>
   3 Date: Tue, 26 Apr 2016 12:57:46 -0500
   4 Subject: [PATCH 09/69] spi: qup: refactor spi_qup_io_config in two functions
   5
   6 This is preparation for handling transactions larger than 64K-1 bytes in
   7 block mode which is currently unsupported quietly fails.
   8
   9 We need to break these into two functions 1) prep is called once per
  10 spi_message and 2) io_config is calle once per spi-qup bus transaction
  11
  12 This is just refactoring, there should be no functional change
  13
  14 Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org>
  15 ---
  16  drivers/spi/spi-qup.c | 141 ++++++++++++++++++++++++++++++--------------------
  17  1 file changed, 86 insertions(+), 55 deletions(-)
  18
  19 --- a/drivers/spi/spi-qup.c
  20 +++ b/drivers/spi/spi-qup.c
  21 @@ -585,12 +585,11 @@ static irqreturn_t spi_qup_qup_irq(int i
  22         return IRQ_HANDLED;
  23  }
  24
  25 -/* set clock freq ... bits per word */
  26 -static int spi_qup_io_config(struct spi_device *spi, struct spi_transfer *xfer)
  27 +/* set clock freq ... bits per word, determine mode */
  28 +static int spi_qup_io_prep(struct spi_device *spi, struct spi_transfer *xfer)
  29  {
  30         struct spi_qup *controller = spi_master_get_devdata(spi->master);
  31 -       u32 config, iomode, control;
  32 -       int ret, n_words;
  33 +       int ret;
  34
  35         if (spi->mode & SPI_LOOP && xfer->len > controller->in_fifo_sz) {
  36                 dev_err(controller->dev, "too big size for loopback %d > %d\n",
  37 @@ -605,56 +604,94 @@ static int spi_qup_io_config(struct spi_
  38                 return -EIO;
  39         }
  40
  41 -       if (spi_qup_set_state(controller, QUP_STATE_RESET)) {
  42 -               dev_err(controller->dev, "cannot set RESET state\n");
  43 -               return -EIO;
  44 -       }
  45 -
  46         controller->w_size = DIV_ROUND_UP(xfer->bits_per_word, 8);
  47         controller->n_words = xfer->len / controller->w_size;
  48 -       n_words = controller->n_words;
  49
  50 -       if (n_words <= (controller->in_fifo_sz / sizeof(u32))) {
  51 +       if (controller->n_words <= (controller->in_fifo_sz / sizeof(u32)))
  52                 controller->mode = QUP_IO_M_MODE_FIFO;
  53 -               writel_relaxed(n_words, controller->base + QUP_MX_READ_CNT);
  54 -               writel_relaxed(n_words, controller->base + QUP_MX_WRITE_CNT);
  55 -               /* must be zero for FIFO */
  56 -               writel_relaxed(0, controller->base + QUP_MX_INPUT_CNT);
  57 -               writel_relaxed(0, controller->base + QUP_MX_OUTPUT_CNT);
  58 -       } else if (spi->master->can_dma &&
  59 -           spi->master->can_dma(spi->master, spi, xfer) &&
  60 -           spi->master->cur_msg_mapped) {
  61 +       else if (spi->master->can_dma &&
  62 +                spi->master->can_dma(spi->master, spi, xfer) &&
  63 +                spi->master->cur_msg_mapped)
  64                 controller->mode = QUP_IO_M_MODE_BAM;
  65 -               writel_relaxed(n_words, controller->base + QUP_MX_INPUT_CNT);
  66 -               writel_relaxed(n_words, controller->base + QUP_MX_OUTPUT_CNT);
  67 -               /* must be zero for BLOCK and BAM */
  68 -               writel_relaxed(0, controller->base + QUP_MX_READ_CNT);
  69 -               writel_relaxed(0, controller->base + QUP_MX_WRITE_CNT);
  70 -
  71 -               if (!controller->qup_v1) {
  72 -                       void __iomem *input_cnt;
  73 -
  74 -                       input_cnt = controller->base + QUP_MX_INPUT_CNT;
  75 -                       /*
  76 -                        * for DMA transfers, both QUP_MX_INPUT_CNT and
  77 -                        * QUP_MX_OUTPUT_CNT must be zero to all cases but one.
  78 -                        * That case is a non-balanced transfer when there is
  79 -                        * only a rx_buf.
  80 -                        */
  81 -                       if (xfer->tx_buf)
  82 -                               writel_relaxed(0, input_cnt);
  83 -                       else
  84 -                               writel_relaxed(n_words, input_cnt);
  85 +       else
  86 +               controller->mode = QUP_IO_M_MODE_BLOCK;
  87 +
  88 +       return 0;
  89 +}
  90
  91 +/* prep qup for another spi transaction of specific type */
  92 +static int spi_qup_io_config(struct spi_device *spi, struct spi_transfer *xfer)
  93 +{
  94 +       struct spi_qup *controller = spi_master_get_devdata(spi->master);
  95 +       u32 config, iomode, control;
  96 +       unsigned long flags;
  97 +
  98 +       reinit_completion(&controller->done);
  99 +       reinit_completion(&controller->dma_tx_done);
 100 +
 101 +       spin_lock_irqsave(&controller->lock, flags);
 102 +       controller->xfer     = xfer;
 103 +       controller->error    = 0;
 104 +       controller->rx_bytes = 0;
 105 +       controller->tx_bytes = 0;
 106 +       spin_unlock_irqrestore(&controller->lock, flags);
 107 +
 108 +
 109 +       if (spi_qup_set_state(controller, QUP_STATE_RESET)) {
 110 +               dev_err(controller->dev, "cannot set RESET state\n");
 111 +               return -EIO;
 112 +       }
 113 +
 114 +       switch (controller->mode) {
 115 +               case QUP_IO_M_MODE_FIFO:
 116 +                       writel_relaxed(controller->n_words,
 117 +                                      controller->base + QUP_MX_READ_CNT);
 118 +                       writel_relaxed(controller->n_words,
 119 +                                      controller->base + QUP_MX_WRITE_CNT);
 120 +                       /* must be zero for FIFO */
 121 +                       writel_relaxed(0, controller->base + QUP_MX_INPUT_CNT);
 122                         writel_relaxed(0, controller->base + QUP_MX_OUTPUT_CNT);
 123 -               }
 124 -       } else {
 125 -               controller->mode = QUP_IO_M_MODE_BLOCK;
 126 -               writel_relaxed(n_words, controller->base + QUP_MX_INPUT_CNT);
 127 -               writel_relaxed(n_words, controller->base + QUP_MX_OUTPUT_CNT);
 128 -               /* must be zero for BLOCK and BAM */
 129 -               writel_relaxed(0, controller->base + QUP_MX_READ_CNT);
 130 -               writel_relaxed(0, controller->base + QUP_MX_WRITE_CNT);
 131 +                       break;
 132 +               case QUP_IO_M_MODE_BAM:
 133 +                       writel_relaxed(controller->n_words,
 134 +                                      controller->base + QUP_MX_INPUT_CNT);
 135 +                       writel_relaxed(controller->n_words,
 136 +                                      controller->base + QUP_MX_OUTPUT_CNT);
 137 +                       /* must be zero for BLOCK and BAM */
 138 +                       writel_relaxed(0, controller->base + QUP_MX_READ_CNT);
 139 +                       writel_relaxed(0, controller->base + QUP_MX_WRITE_CNT);
 140 +                       if (!controller->qup_v1) {
 141 +                               void __iomem *input_cnt;
 142 +
 143 +                               input_cnt = controller->base + QUP_MX_INPUT_CNT;
 144 +                               /*
 145 +                                * for DMA transfers, both QUP_MX_INPUT_CNT and
 146 +                                * QUP_MX_OUTPUT_CNT must be zero to all cases
 147 +                                * but one. That case is a non-balanced
 148 +                                * transfer when there is only a rx_buf.
 149 +                                */
 150 +                               if (xfer->tx_buf)
 151 +                                       writel_relaxed(0, input_cnt);
 152 +                               else
 153 +                                       writel_relaxed(controller->n_words,
 154 +                                                      input_cnt);
 155 +
 156 +                               writel_relaxed(0, controller->base + QUP_MX_OUTPUT_CNT);
 157 +                       }
 158 +                       break;
 159 +               case QUP_IO_M_MODE_BLOCK:
 160 +                       writel_relaxed(controller->n_words,
 161 +                                      controller->base + QUP_MX_INPUT_CNT);
 162 +                       writel_relaxed(controller->n_words,
 163 +                                      controller->base + QUP_MX_OUTPUT_CNT);
 164 +                       /* must be zero for BLOCK and BAM */
 165 +                       writel_relaxed(0, controller->base + QUP_MX_READ_CNT);
 166 +                       writel_relaxed(0, controller->base + QUP_MX_WRITE_CNT);
 167 +                       break;
 168 +               default:
 169 +                       dev_err(controller->dev, "unknown mode = %d\n",
 170 +                                       controller->mode);
 171 +                       return -EIO;
 172         }
 173
 174         iomode = readl_relaxed(controller->base + QUP_IO_M_MODES);
 175 @@ -743,6 +780,10 @@ static int spi_qup_transfer_one(struct s
 176         unsigned long timeout, flags;
 177         int ret = -EIO;
 178
 179 +       ret = spi_qup_io_prep(spi, xfer);
 180 +       if (ret)
 181 +               return ret;
 182 +
 183         ret = spi_qup_io_config(spi, xfer);
 184         if (ret)
 185                 return ret;
 186 @@ -751,16 +792,6 @@ static int spi_qup_transfer_one(struct s
 187         timeout = DIV_ROUND_UP(xfer->len * 8, timeout);
 188         timeout = 100 * msecs_to_jiffies(timeout);
 189
 190 -       reinit_completion(&controller->done);
 191 -       reinit_completion(&controller->dma_tx_done);
 192 -
 193 -       spin_lock_irqsave(&controller->lock, flags);
 194 -       controller->xfer     = xfer;
 195 -       controller->error    = 0;
 196 -       controller->rx_bytes = 0;
 197 -       controller->tx_bytes = 0;
 198 -       spin_unlock_irqrestore(&controller->lock, flags);
 199 -
 200         if (spi_qup_is_dma_xfer(controller->mode))
 201                 ret = spi_qup_do_dma(master, xfer, timeout);
 202         else