target/linux/ipq806x/patches-4.9/0002-dmaengine-Add-ADM-driver.patch

   1 From 1d32bf93c8e83db0aca04d2961badef7e86d663b Mon Sep 17 00:00:00 2001
   2 From: Thomas Pedersen <twp@codeaurora.org>
   3 Date: Mon, 16 May 2016 17:58:51 -0700
   4 Subject: [PATCH 02/37] dmaengine: Add ADM driver
   5
   6 Original patch by Andy Gross.
   7
   8 Add the DMA engine driver for the QCOM Application Data Mover (ADM) DMA
   9 controller found in the MSM8x60 and IPQ/APQ8064 platforms.
  10
  11 The ADM supports both memory to memory transactions and memory
  12 to/from peripheral device transactions.  The controller also provides flow
  13 control capabilities for transactions to/from peripheral devices.
  14
  15 The initial release of this driver supports slave transfers to/from peripherals
  16 and also incorporates CRCI (client rate control interface) flow control.
  17
  18 Signed-off-by: Andy Gross <agross@codeaurora.org>
  19 Signed-off-by: Thomas Pedersen <twp@codeaurora.org>
  20 ---
  21  drivers/dma/qcom/Kconfig    |   10 +
  22  drivers/dma/qcom/Makefile   |    1 +
  23  drivers/dma/qcom/qcom_adm.c |  900 +++++++++++++++++++++++++++++++++++++++++++
  24  3 files changed, 911 insertions(+)
  25  create mode 100644 drivers/dma/qcom/qcom_adm.c
  26
  27 --- a/drivers/dma/qcom/Kconfig
  28 +++ b/drivers/dma/qcom/Kconfig
  29 @@ -27,3 +27,13 @@ config QCOM_HIDMA
  30           (user to kernel, kernel to kernel, etc.).  It only supports
  31           memcpy interface. The core is not intended for general
  32           purpose slave DMA.
  33 +
  34 +config QCOM_ADM
  35 +       tristate "Qualcomm ADM support"
  36 +       depends on ARCH_QCOM || (COMPILE_TEST && OF && ARM)
  37 +       select DMA_ENGINE
  38 +       select DMA_VIRTUAL_CHANNELS
  39 +       ---help---
  40 +         Enable support for the Qualcomm ADM DMA controller.  This controller
  41 +         provides DMA capabilities for both general purpose and on-chip
  42 +         peripheral devices.
  43 --- a/drivers/dma/qcom/Makefile
  44 +++ b/drivers/dma/qcom/Makefile
  45 @@ -3,3 +3,4 @@ obj-$(CONFIG_QCOM_HIDMA_MGMT) += hdma_mg
  46  hdma_mgmt-objs  := hidma_mgmt.o hidma_mgmt_sys.o
  47  obj-$(CONFIG_QCOM_HIDMA) +=  hdma.o
  48  hdma-objs        := hidma_ll.o hidma.o hidma_dbg.o
  49 +obj-$(CONFIG_QCOM_ADM) += qcom_adm.o
  50 --- /dev/null
  51 +++ b/drivers/dma/qcom/qcom_adm.c
  52 @@ -0,0 +1,900 @@
  53 +/*
  54 + * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
  55 + *
  56 + * This program is free software; you can redistribute it and/or modify
  57 + * it under the terms of the GNU General Public License version 2 and
  58 + * only version 2 as published by the Free Software Foundation.
  59 + *
  60 + * This program is distributed in the hope that it will be useful,
  61 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  62 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  63 + * GNU General Public License for more details.
  64 + *
  65 + */
  66 +
  67 +#include <linux/kernel.h>
  68 +#include <linux/io.h>
  69 +#include <linux/init.h>
  70 +#include <linux/slab.h>
  71 +#include <linux/module.h>
  72 +#include <linux/interrupt.h>
  73 +#include <linux/dma-mapping.h>
  74 +#include <linux/scatterlist.h>
  75 +#include <linux/device.h>
  76 +#include <linux/platform_device.h>
  77 +#include <linux/of.h>
  78 +#include <linux/of_address.h>
  79 +#include <linux/of_irq.h>
  80 +#include <linux/of_dma.h>
  81 +#include <linux/reset.h>
  82 +#include <linux/clk.h>
  83 +#include <linux/dmaengine.h>
  84 +
  85 +#include "../dmaengine.h"
  86 +#include "../virt-dma.h"
  87 +
  88 +/* ADM registers - calculated from channel number and security domain */
  89 +#define ADM_CHAN_MULTI                 0x4
  90 +#define ADM_CI_MULTI                   0x4
  91 +#define ADM_CRCI_MULTI                 0x4
  92 +#define ADM_EE_MULTI                   0x800
  93 +#define ADM_CHAN_OFFS(chan)            (ADM_CHAN_MULTI * chan)
  94 +#define ADM_EE_OFFS(ee)                        (ADM_EE_MULTI * ee)
  95 +#define ADM_CHAN_EE_OFFS(chan, ee)     (ADM_CHAN_OFFS(chan) + ADM_EE_OFFS(ee))
  96 +#define ADM_CHAN_OFFS(chan)            (ADM_CHAN_MULTI * chan)
  97 +#define ADM_CI_OFFS(ci)                        (ADM_CHAN_OFF(ci))
  98 +#define ADM_CH_CMD_PTR(chan, ee)       (ADM_CHAN_EE_OFFS(chan, ee))
  99 +#define ADM_CH_RSLT(chan, ee)          (0x40 + ADM_CHAN_EE_OFFS(chan, ee))
 100 +#define ADM_CH_FLUSH_STATE0(chan, ee)  (0x80 + ADM_CHAN_EE_OFFS(chan, ee))
 101 +#define ADM_CH_STATUS_SD(chan, ee)     (0x200 + ADM_CHAN_EE_OFFS(chan, ee))
 102 +#define ADM_CH_CONF(chan)              (0x240 + ADM_CHAN_OFFS(chan))
 103 +#define ADM_CH_RSLT_CONF(chan, ee)     (0x300 + ADM_CHAN_EE_OFFS(chan, ee))
 104 +#define ADM_SEC_DOMAIN_IRQ_STATUS(ee)  (0x380 + ADM_EE_OFFS(ee))
 105 +#define ADM_CI_CONF(ci)                        (0x390 + ci * ADM_CI_MULTI)
 106 +#define ADM_GP_CTL                     0x3d8
 107 +#define ADM_CRCI_CTL(crci, ee)         (0x400 + crci * ADM_CRCI_MULTI + \
 108 +                                               ADM_EE_OFFS(ee))
 109 +
 110 +/* channel status */
 111 +#define ADM_CH_STATUS_VALID    BIT(1)
 112 +
 113 +/* channel result */
 114 +#define ADM_CH_RSLT_VALID      BIT(31)
 115 +#define ADM_CH_RSLT_ERR                BIT(3)
 116 +#define ADM_CH_RSLT_FLUSH      BIT(2)
 117 +#define ADM_CH_RSLT_TPD                BIT(1)
 118 +
 119 +/* channel conf */
 120 +#define ADM_CH_CONF_SHADOW_EN          BIT(12)
 121 +#define ADM_CH_CONF_MPU_DISABLE                BIT(11)
 122 +#define ADM_CH_CONF_PERM_MPU_CONF      BIT(9)
 123 +#define ADM_CH_CONF_FORCE_RSLT_EN      BIT(7)
 124 +#define ADM_CH_CONF_SEC_DOMAIN(ee)     (((ee & 0x3) << 4) | ((ee & 0x4) << 11))
 125 +
 126 +/* channel result conf */
 127 +#define ADM_CH_RSLT_CONF_FLUSH_EN      BIT(1)
 128 +#define ADM_CH_RSLT_CONF_IRQ_EN                BIT(0)
 129 +
 130 +/* CRCI CTL */
 131 +#define ADM_CRCI_CTL_MUX_SEL   BIT(18)
 132 +#define ADM_CRCI_CTL_RST       BIT(17)
 133 +
 134 +/* CI configuration */
 135 +#define ADM_CI_RANGE_END(x)    (x << 24)
 136 +#define ADM_CI_RANGE_START(x)  (x << 16)
 137 +#define ADM_CI_BURST_4_WORDS   BIT(2)
 138 +#define ADM_CI_BURST_8_WORDS   BIT(3)
 139 +
 140 +/* GP CTL */
 141 +#define ADM_GP_CTL_LP_EN       BIT(12)
 142 +#define ADM_GP_CTL_LP_CNT(x)   (x << 8)
 143 +
 144 +/* Command pointer list entry */
 145 +#define ADM_CPLE_LP            BIT(31)
 146 +#define ADM_CPLE_CMD_PTR_LIST  BIT(29)
 147 +
 148 +/* Command list entry */
 149 +#define ADM_CMD_LC             BIT(31)
 150 +#define ADM_CMD_DST_CRCI(n)    (((n) & 0xf) << 7)
 151 +#define ADM_CMD_SRC_CRCI(n)    (((n) & 0xf) << 3)
 152 +
 153 +#define ADM_CMD_TYPE_SINGLE    0x0
 154 +#define ADM_CMD_TYPE_BOX       0x3
 155 +
 156 +#define ADM_CRCI_MUX_SEL       BIT(4)
 157 +#define ADM_DESC_ALIGN         8
 158 +#define ADM_MAX_XFER           (SZ_64K-1)
 159 +#define ADM_MAX_ROWS           (SZ_64K-1)
 160 +#define ADM_MAX_CHANNELS       16
 161 +
 162 +struct adm_desc_hw_box {
 163 +       u32 cmd;
 164 +       u32 src_addr;
 165 +       u32 dst_addr;
 166 +       u32 row_len;
 167 +       u32 num_rows;
 168 +       u32 row_offset;
 169 +};
 170 +
 171 +struct adm_desc_hw_single {
 172 +       u32 cmd;
 173 +       u32 src_addr;
 174 +       u32 dst_addr;
 175 +       u32 len;
 176 +};
 177 +
 178 +struct adm_async_desc {
 179 +       struct virt_dma_desc vd;
 180 +       struct adm_device *adev;
 181 +
 182 +       size_t length;
 183 +       enum dma_transfer_direction dir;
 184 +       dma_addr_t dma_addr;
 185 +       size_t dma_len;
 186 +
 187 +       void *cpl;
 188 +       dma_addr_t cp_addr;
 189 +       u32 crci;
 190 +       u32 mux;
 191 +       u32 blk_size;
 192 +};
 193 +
 194 +struct adm_chan {
 195 +       struct virt_dma_chan vc;
 196 +       struct adm_device *adev;
 197 +
 198 +       /* parsed from DT */
 199 +       u32 id;                 /* channel id */
 200 +
 201 +       struct adm_async_desc *curr_txd;
 202 +       struct dma_slave_config slave;
 203 +       struct list_head node;
 204 +
 205 +       int error;
 206 +       int initialized;
 207 +};
 208 +
 209 +static inline struct adm_chan *to_adm_chan(struct dma_chan *common)
 210 +{
 211 +       return container_of(common, struct adm_chan, vc.chan);
 212 +}
 213 +
 214 +struct adm_device {
 215 +       void __iomem *regs;
 216 +       struct device *dev;
 217 +       struct dma_device common;
 218 +       struct device_dma_parameters dma_parms;
 219 +       struct adm_chan *channels;
 220 +
 221 +       u32 ee;
 222 +
 223 +       struct clk *core_clk;
 224 +       struct clk *iface_clk;
 225 +
 226 +       struct reset_control *clk_reset;
 227 +       struct reset_control *c0_reset;
 228 +       struct reset_control *c1_reset;
 229 +       struct reset_control *c2_reset;
 230 +       int irq;
 231 +};
 232 +
 233 +/**
 234 + * adm_free_chan - Frees dma resources associated with the specific channel
 235 + *
 236 + * Free all allocated descriptors associated with this channel
 237 + *
 238 + */
 239 +static void adm_free_chan(struct dma_chan *chan)
 240 +{
 241 +       /* free all queued descriptors */
 242 +       vchan_free_chan_resources(to_virt_chan(chan));
 243 +}
 244 +
 245 +/**
 246 + * adm_get_blksize - Get block size from burst value
 247 + *
 248 + */
 249 +static int adm_get_blksize(unsigned int burst)
 250 +{
 251 +       int ret;
 252 +
 253 +       switch (burst) {
 254 +       case 16:
 255 +       case 32:
 256 +       case 64:
 257 +       case 128:
 258 +               ret = ffs(burst>>4) - 1;
 259 +               break;
 260 +       case 192:
 261 +               ret = 4;
 262 +               break;
 263 +       case 256:
 264 +               ret = 5;
 265 +               break;
 266 +       default:
 267 +               ret = -EINVAL;
 268 +               break;
 269 +       }
 270 +
 271 +       return ret;
 272 +}
 273 +
 274 +/**
 275 + * adm_process_fc_descriptors - Process descriptors for flow controlled xfers
 276 + *
 277 + * @achan: ADM channel
 278 + * @desc: Descriptor memory pointer
 279 + * @sg: Scatterlist entry
 280 + * @crci: CRCI value
 281 + * @burst: Burst size of transaction
 282 + * @direction: DMA transfer direction
 283 + */
 284 +static void *adm_process_fc_descriptors(struct adm_chan *achan,
 285 +       void *desc, struct scatterlist *sg, u32 crci, u32 burst,
 286 +       enum dma_transfer_direction direction)
 287 +{
 288 +       struct adm_desc_hw_box *box_desc = NULL;
 289 +       struct adm_desc_hw_single *single_desc;
 290 +       u32 remainder = sg_dma_len(sg);
 291 +       u32 rows, row_offset, crci_cmd;
 292 +       u32 mem_addr = sg_dma_address(sg);
 293 +       u32 *incr_addr = &mem_addr;
 294 +       u32 *src, *dst;
 295 +
 296 +       if (direction == DMA_DEV_TO_MEM) {
 297 +               crci_cmd = ADM_CMD_SRC_CRCI(crci);
 298 +               row_offset = burst;
 299 +               src = &achan->slave.src_addr;
 300 +               dst = &mem_addr;
 301 +       } else {
 302 +               crci_cmd = ADM_CMD_DST_CRCI(crci);
 303 +               row_offset = burst << 16;
 304 +               src = &mem_addr;
 305 +               dst = &achan->slave.dst_addr;
 306 +       }
 307 +
 308 +       while (remainder >= burst) {
 309 +               box_desc = desc;
 310 +               box_desc->cmd = ADM_CMD_TYPE_BOX | crci_cmd;
 311 +               box_desc->row_offset = row_offset;
 312 +               box_desc->src_addr = *src;
 313 +               box_desc->dst_addr = *dst;
 314 +
 315 +               rows = remainder / burst;
 316 +               rows = min_t(u32, rows, ADM_MAX_ROWS);
 317 +               box_desc->num_rows = rows << 16 | rows;
 318 +               box_desc->row_len = burst << 16 | burst;
 319 +
 320 +               *incr_addr += burst * rows;
 321 +               remainder -= burst * rows;
 322 +               desc += sizeof(*box_desc);
 323 +       }
 324 +
 325 +       /* if leftover bytes, do one single descriptor */
 326 +       if (remainder) {
 327 +               single_desc = desc;
 328 +               single_desc->cmd = ADM_CMD_TYPE_SINGLE | crci_cmd;
 329 +               single_desc->len = remainder;
 330 +               single_desc->src_addr = *src;
 331 +               single_desc->dst_addr = *dst;
 332 +               desc += sizeof(*single_desc);
 333 +
 334 +               if (sg_is_last(sg))
 335 +                       single_desc->cmd |= ADM_CMD_LC;
 336 +       } else {
 337 +               if (box_desc && sg_is_last(sg))
 338 +                       box_desc->cmd |= ADM_CMD_LC;
 339 +       }
 340 +
 341 +       return desc;
 342 +}
 343 +
 344 +/**
 345 + * adm_process_non_fc_descriptors - Process descriptors for non-fc xfers
 346 + *
 347 + * @achan: ADM channel
 348 + * @desc: Descriptor memory pointer
 349 + * @sg: Scatterlist entry
 350 + * @direction: DMA transfer direction
 351 + */
 352 +static void *adm_process_non_fc_descriptors(struct adm_chan *achan,
 353 +       void *desc, struct scatterlist *sg,
 354 +       enum dma_transfer_direction direction)
 355 +{
 356 +       struct adm_desc_hw_single *single_desc;
 357 +       u32 remainder = sg_dma_len(sg);
 358 +       u32 mem_addr = sg_dma_address(sg);
 359 +       u32 *incr_addr = &mem_addr;
 360 +       u32 *src, *dst;
 361 +
 362 +       if (direction == DMA_DEV_TO_MEM) {
 363 +               src = &achan->slave.src_addr;
 364 +               dst = &mem_addr;
 365 +       } else {
 366 +               src = &mem_addr;
 367 +               dst = &achan->slave.dst_addr;
 368 +       }
 369 +
 370 +       do {
 371 +               single_desc = desc;
 372 +               single_desc->cmd = ADM_CMD_TYPE_SINGLE;
 373 +               single_desc->src_addr = *src;
 374 +               single_desc->dst_addr = *dst;
 375 +               single_desc->len = (remainder > ADM_MAX_XFER) ?
 376 +                               ADM_MAX_XFER : remainder;
 377 +
 378 +               remainder -= single_desc->len;
 379 +               *incr_addr += single_desc->len;
 380 +               desc += sizeof(*single_desc);
 381 +       } while (remainder);
 382 +
 383 +       /* set last command if this is the end of the whole transaction */
 384 +       if (sg_is_last(sg))
 385 +               single_desc->cmd |= ADM_CMD_LC;
 386 +
 387 +       return desc;
 388 +}
 389 +
 390 +/**
 391 + * adm_prep_slave_sg - Prep slave sg transaction
 392 + *
 393 + * @chan: dma channel
 394 + * @sgl: scatter gather list
 395 + * @sg_len: length of sg
 396 + * @direction: DMA transfer direction
 397 + * @flags: DMA flags
 398 + * @context: transfer context (unused)
 399 + */
 400 +static struct dma_async_tx_descriptor *adm_prep_slave_sg(struct dma_chan *chan,
 401 +       struct scatterlist *sgl, unsigned int sg_len,
 402 +       enum dma_transfer_direction direction, unsigned long flags,
 403 +       void *context)
 404 +{
 405 +       struct adm_chan *achan = to_adm_chan(chan);
 406 +       struct adm_device *adev = achan->adev;
 407 +       struct adm_async_desc *async_desc;
 408 +       struct scatterlist *sg;
 409 +       u32 i, burst;
 410 +       u32 single_count = 0, box_count = 0, crci = 0;
 411 +       void *desc;
 412 +       u32 *cple;
 413 +       int blk_size = 0;
 414 +
 415 +       if (!is_slave_direction(direction)) {
 416 +               dev_err(adev->dev, "invalid dma direction\n");
 417 +               return NULL;
 418 +       }
 419 +
 420 +       /*
 421 +        * get burst value from slave configuration
 422 +        */
 423 +       burst = (direction == DMA_MEM_TO_DEV) ?
 424 +               achan->slave.dst_maxburst :
 425 +               achan->slave.src_maxburst;
 426 +
 427 +       /* if using flow control, validate burst and crci values */
 428 +       if (achan->slave.device_fc) {
 429 +
 430 +               blk_size = adm_get_blksize(burst);
 431 +               if (blk_size < 0) {
 432 +                       dev_err(adev->dev, "invalid burst value: %d\n",
 433 +                               burst);
 434 +                       return ERR_PTR(-EINVAL);
 435 +               }
 436 +
 437 +               crci = achan->slave.slave_id & 0xf;
 438 +               if (!crci || achan->slave.slave_id > 0x1f) {
 439 +                       dev_err(adev->dev, "invalid crci value\n");
 440 +                       return ERR_PTR(-EINVAL);
 441 +               }
 442 +       }
 443 +
 444 +       /* iterate through sgs and compute allocation size of structures */
 445 +       for_each_sg(sgl, sg, sg_len, i) {
 446 +               if (achan->slave.device_fc) {
 447 +                       box_count += DIV_ROUND_UP(sg_dma_len(sg) / burst,
 448 +                                                 ADM_MAX_ROWS);
 449 +                       if (sg_dma_len(sg) % burst)
 450 +                               single_count++;
 451 +               } else {
 452 +                       single_count += DIV_ROUND_UP(sg_dma_len(sg),
 453 +                                                    ADM_MAX_XFER);
 454 +               }
 455 +       }
 456 +
 457 +       async_desc = kzalloc(sizeof(*async_desc), GFP_NOWAIT);
 458 +       if (!async_desc)
 459 +               return ERR_PTR(-ENOMEM);
 460 +
 461 +       if (crci)
 462 +               async_desc->mux = achan->slave.slave_id & ADM_CRCI_MUX_SEL ?
 463 +                                       ADM_CRCI_CTL_MUX_SEL : 0;
 464 +       async_desc->crci = crci;
 465 +       async_desc->blk_size = blk_size;
 466 +       async_desc->dma_len = single_count * sizeof(struct adm_desc_hw_single) +
 467 +                               box_count * sizeof(struct adm_desc_hw_box) +
 468 +                               sizeof(*cple) + 2 * ADM_DESC_ALIGN;
 469 +
 470 +       async_desc->cpl = dma_alloc_writecombine(adev->dev, async_desc->dma_len,
 471 +                               &async_desc->dma_addr, GFP_NOWAIT);
 472 +
 473 +       if (!async_desc->cpl) {
 474 +               kfree(async_desc);
 475 +               return ERR_PTR(-ENOMEM);
 476 +       }
 477 +
 478 +       async_desc->adev = adev;
 479 +
 480 +       /* both command list entry and descriptors must be 8 byte aligned */
 481 +       cple = PTR_ALIGN(async_desc->cpl, ADM_DESC_ALIGN);
 482 +       desc = PTR_ALIGN(cple + 1, ADM_DESC_ALIGN);
 483 +
 484 +       /* init cmd list */
 485 +       *cple = ADM_CPLE_LP;
 486 +       *cple |= (desc - async_desc->cpl + async_desc->dma_addr) >> 3;
 487 +
 488 +       for_each_sg(sgl, sg, sg_len, i) {
 489 +               async_desc->length += sg_dma_len(sg);
 490 +
 491 +               if (achan->slave.device_fc)
 492 +                       desc = adm_process_fc_descriptors(achan, desc, sg, crci,
 493 +                                                       burst, direction);
 494 +               else
 495 +                       desc = adm_process_non_fc_descriptors(achan, desc, sg,
 496 +                                                          direction);
 497 +       }
 498 +
 499 +       return vchan_tx_prep(&achan->vc, &async_desc->vd, flags);
 500 +}
 501 +
 502 +/**
 503 + * adm_terminate_all - terminate all transactions on a channel
 504 + * @achan: adm dma channel
 505 + *
 506 + * Dequeues and frees all transactions, aborts current transaction
 507 + * No callbacks are done
 508 + *
 509 + */
 510 +static int adm_terminate_all(struct dma_chan *chan)
 511 +{
 512 +       struct adm_chan *achan = to_adm_chan(chan);
 513 +       struct adm_device *adev = achan->adev;
 514 +       unsigned long flags;
 515 +       LIST_HEAD(head);
 516 +
 517 +       spin_lock_irqsave(&achan->vc.lock, flags);
 518 +       vchan_get_all_descriptors(&achan->vc, &head);
 519 +
 520 +       /* send flush command to terminate current transaction */
 521 +       writel_relaxed(0x0,
 522 +               adev->regs + ADM_CH_FLUSH_STATE0(achan->id, adev->ee));
 523 +
 524 +       spin_unlock_irqrestore(&achan->vc.lock, flags);
 525 +
 526 +       vchan_dma_desc_free_list(&achan->vc, &head);
 527 +
 528 +       return 0;
 529 +}
 530 +
 531 +static int adm_slave_config(struct dma_chan *chan, struct dma_slave_config *cfg)
 532 +{
 533 +       struct adm_chan *achan = to_adm_chan(chan);
 534 +       unsigned long flag;
 535 +
 536 +       spin_lock_irqsave(&achan->vc.lock, flag);
 537 +       memcpy(&achan->slave, cfg, sizeof(struct dma_slave_config));
 538 +       spin_unlock_irqrestore(&achan->vc.lock, flag);
 539 +
 540 +       return 0;
 541 +}
 542 +
 543 +/**
 544 + * adm_start_dma - start next transaction
 545 + * @achan - ADM dma channel
 546 + */
 547 +static void adm_start_dma(struct adm_chan *achan)
 548 +{
 549 +       struct virt_dma_desc *vd = vchan_next_desc(&achan->vc);
 550 +       struct adm_device *adev = achan->adev;
 551 +       struct adm_async_desc *async_desc;
 552 +
 553 +       lockdep_assert_held(&achan->vc.lock);
 554 +
 555 +       if (!vd)
 556 +               return;
 557 +
 558 +       list_del(&vd->node);
 559 +
 560 +       /* write next command list out to the CMD FIFO */
 561 +       async_desc = container_of(vd, struct adm_async_desc, vd);
 562 +       achan->curr_txd = async_desc;
 563 +
 564 +       /* reset channel error */
 565 +       achan->error = 0;
 566 +
 567 +       if (!achan->initialized) {
 568 +               /* enable interrupts */
 569 +               writel(ADM_CH_CONF_SHADOW_EN |
 570 +                      ADM_CH_CONF_PERM_MPU_CONF |
 571 +                      ADM_CH_CONF_MPU_DISABLE |
 572 +                      ADM_CH_CONF_SEC_DOMAIN(adev->ee),
 573 +                      adev->regs + ADM_CH_CONF(achan->id));
 574 +
 575 +               writel(ADM_CH_RSLT_CONF_IRQ_EN | ADM_CH_RSLT_CONF_FLUSH_EN,
 576 +                       adev->regs + ADM_CH_RSLT_CONF(achan->id, adev->ee));
 577 +
 578 +               achan->initialized = 1;
 579 +       }
 580 +
 581 +       /* set the crci block size if this transaction requires CRCI */
 582 +       if (async_desc->crci) {
 583 +               writel(async_desc->mux | async_desc->blk_size,
 584 +                       adev->regs + ADM_CRCI_CTL(async_desc->crci, adev->ee));
 585 +       }
 586 +
 587 +       /* make sure IRQ enable doesn't get reordered */
 588 +       wmb();
 589 +
 590 +       /* write next command list out to the CMD FIFO */
 591 +       writel(ALIGN(async_desc->dma_addr, ADM_DESC_ALIGN) >> 3,
 592 +               adev->regs + ADM_CH_CMD_PTR(achan->id, adev->ee));
 593 +}
 594 +
 595 +/**
 596 + * adm_dma_irq - irq handler for ADM controller
 597 + * @irq: IRQ of interrupt
 598 + * @data: callback data
 599 + *
 600 + * IRQ handler for the bam controller
 601 + */
 602 +static irqreturn_t adm_dma_irq(int irq, void *data)
 603 +{
 604 +       struct adm_device *adev = data;
 605 +       u32 srcs, i;
 606 +       struct adm_async_desc *async_desc;
 607 +       unsigned long flags;
 608 +
 609 +       srcs = readl_relaxed(adev->regs +
 610 +                       ADM_SEC_DOMAIN_IRQ_STATUS(adev->ee));
 611 +
 612 +       for (i = 0; i < ADM_MAX_CHANNELS; i++) {
 613 +               struct adm_chan *achan = &adev->channels[i];
 614 +               u32 status, result;
 615 +
 616 +               if (srcs & BIT(i)) {
 617 +                       status = readl_relaxed(adev->regs +
 618 +                               ADM_CH_STATUS_SD(i, adev->ee));
 619 +
 620 +                       /* if no result present, skip */
 621 +                       if (!(status & ADM_CH_STATUS_VALID))
 622 +                               continue;
 623 +
 624 +                       result = readl_relaxed(adev->regs +
 625 +                               ADM_CH_RSLT(i, adev->ee));
 626 +
 627 +                       /* no valid results, skip */
 628 +                       if (!(result & ADM_CH_RSLT_VALID))
 629 +                               continue;
 630 +
 631 +                       /* flag error if transaction was flushed or failed */
 632 +                       if (result & (ADM_CH_RSLT_ERR | ADM_CH_RSLT_FLUSH))
 633 +                               achan->error = 1;
 634 +
 635 +                       spin_lock_irqsave(&achan->vc.lock, flags);
 636 +                       async_desc = achan->curr_txd;
 637 +
 638 +                       achan->curr_txd = NULL;
 639 +
 640 +                       if (async_desc) {
 641 +                               vchan_cookie_complete(&async_desc->vd);
 642 +
 643 +                               /* kick off next DMA */
 644 +                               adm_start_dma(achan);
 645 +                       }
 646 +
 647 +                       spin_unlock_irqrestore(&achan->vc.lock, flags);
 648 +               }
 649 +       }
 650 +
 651 +       return IRQ_HANDLED;
 652 +}
 653 +
 654 +/**
 655 + * adm_tx_status - returns status of transaction
 656 + * @chan: dma channel
 657 + * @cookie: transaction cookie
 658 + * @txstate: DMA transaction state
 659 + *
 660 + * Return status of dma transaction
 661 + */
 662 +static enum dma_status adm_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
 663 +       struct dma_tx_state *txstate)
 664 +{
 665 +       struct adm_chan *achan = to_adm_chan(chan);
 666 +       struct virt_dma_desc *vd;
 667 +       enum dma_status ret;
 668 +       unsigned long flags;
 669 +       size_t residue = 0;
 670 +
 671 +       ret = dma_cookie_status(chan, cookie, txstate);
 672 +       if (ret == DMA_COMPLETE || !txstate)
 673 +               return ret;
 674 +
 675 +       spin_lock_irqsave(&achan->vc.lock, flags);
 676 +
 677 +       vd = vchan_find_desc(&achan->vc, cookie);
 678 +       if (vd)
 679 +               residue = container_of(vd, struct adm_async_desc, vd)->length;
 680 +
 681 +       spin_unlock_irqrestore(&achan->vc.lock, flags);
 682 +
 683 +       /*
 684 +        * residue is either the full length if it is in the issued list, or 0
 685 +        * if it is in progress.  We have no reliable way of determining
 686 +        * anything inbetween
 687 +       */
 688 +       dma_set_residue(txstate, residue);
 689 +
 690 +       if (achan->error)
 691 +               return DMA_ERROR;
 692 +
 693 +       return ret;
 694 +}
 695 +
 696 +/**
 697 + * adm_issue_pending - starts pending transactions
 698 + * @chan: dma channel
 699 + *
 700 + * Issues all pending transactions and starts DMA
 701 + */
 702 +static void adm_issue_pending(struct dma_chan *chan)
 703 +{
 704 +       struct adm_chan *achan = to_adm_chan(chan);
 705 +       unsigned long flags;
 706 +
 707 +       spin_lock_irqsave(&achan->vc.lock, flags);
 708 +
 709 +       if (vchan_issue_pending(&achan->vc) && !achan->curr_txd)
 710 +               adm_start_dma(achan);
 711 +       spin_unlock_irqrestore(&achan->vc.lock, flags);
 712 +}
 713 +
 714 +/**
 715 + * adm_dma_free_desc - free descriptor memory
 716 + * @vd: virtual descriptor
 717 + *
 718 + */
 719 +static void adm_dma_free_desc(struct virt_dma_desc *vd)
 720 +{
 721 +       struct adm_async_desc *async_desc = container_of(vd,
 722 +                       struct adm_async_desc, vd);
 723 +
 724 +       dma_free_writecombine(async_desc->adev->dev, async_desc->dma_len,
 725 +               async_desc->cpl, async_desc->dma_addr);
 726 +       kfree(async_desc);
 727 +}
 728 +
 729 +static void adm_channel_init(struct adm_device *adev, struct adm_chan *achan,
 730 +       u32 index)
 731 +{
 732 +       achan->id = index;
 733 +       achan->adev = adev;
 734 +
 735 +       vchan_init(&achan->vc, &adev->common);
 736 +       achan->vc.desc_free = adm_dma_free_desc;
 737 +}
 738 +
 739 +static int adm_dma_probe(struct platform_device *pdev)
 740 +{
 741 +       struct adm_device *adev;
 742 +       struct resource *iores;
 743 +       int ret;
 744 +       u32 i;
 745 +
 746 +       adev = devm_kzalloc(&pdev->dev, sizeof(*adev), GFP_KERNEL);
 747 +       if (!adev)
 748 +               return -ENOMEM;
 749 +
 750 +       adev->dev = &pdev->dev;
 751 +
 752 +       iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 753 +       adev->regs = devm_ioremap_resource(&pdev->dev, iores);
 754 +       if (IS_ERR(adev->regs))
 755 +               return PTR_ERR(adev->regs);
 756 +
 757 +       adev->irq = platform_get_irq(pdev, 0);
 758 +       if (adev->irq < 0)
 759 +               return adev->irq;
 760 +
 761 +       ret = of_property_read_u32(pdev->dev.of_node, "qcom,ee", &adev->ee);
 762 +       if (ret) {
 763 +               dev_err(adev->dev, "Execution environment unspecified\n");
 764 +               return ret;
 765 +       }
 766 +
 767 +       adev->core_clk = devm_clk_get(adev->dev, "core");
 768 +       if (IS_ERR(adev->core_clk))
 769 +               return PTR_ERR(adev->core_clk);
 770 +
 771 +       ret = clk_prepare_enable(adev->core_clk);
 772 +       if (ret) {
 773 +               dev_err(adev->dev, "failed to prepare/enable core clock\n");
 774 +               return ret;
 775 +       }
 776 +
 777 +       adev->iface_clk = devm_clk_get(adev->dev, "iface");
 778 +       if (IS_ERR(adev->iface_clk)) {
 779 +               ret = PTR_ERR(adev->iface_clk);
 780 +               goto err_disable_core_clk;
 781 +       }
 782 +
 783 +       ret = clk_prepare_enable(adev->iface_clk);
 784 +       if (ret) {
 785 +               dev_err(adev->dev, "failed to prepare/enable iface clock\n");
 786 +               goto err_disable_core_clk;
 787 +       }
 788 +
 789 +       adev->clk_reset = devm_reset_control_get(&pdev->dev, "clk");
 790 +       if (IS_ERR(adev->clk_reset)) {
 791 +               dev_err(adev->dev, "failed to get ADM0 reset\n");
 792 +               ret = PTR_ERR(adev->clk_reset);
 793 +               goto err_disable_clks;
 794 +       }
 795 +
 796 +       adev->c0_reset = devm_reset_control_get(&pdev->dev, "c0");
 797 +       if (IS_ERR(adev->c0_reset)) {
 798 +               dev_err(adev->dev, "failed to get ADM0 C0 reset\n");
 799 +               ret = PTR_ERR(adev->c0_reset);
 800 +               goto err_disable_clks;
 801 +       }
 802 +
 803 +       adev->c1_reset = devm_reset_control_get(&pdev->dev, "c1");
 804 +       if (IS_ERR(adev->c1_reset)) {
 805 +               dev_err(adev->dev, "failed to get ADM0 C1 reset\n");
 806 +               ret = PTR_ERR(adev->c1_reset);
 807 +               goto err_disable_clks;
 808 +       }
 809 +
 810 +       adev->c2_reset = devm_reset_control_get(&pdev->dev, "c2");
 811 +       if (IS_ERR(adev->c2_reset)) {
 812 +               dev_err(adev->dev, "failed to get ADM0 C2 reset\n");
 813 +               ret = PTR_ERR(adev->c2_reset);
 814 +               goto err_disable_clks;
 815 +       }
 816 +
 817 +       reset_control_assert(adev->clk_reset);
 818 +       reset_control_assert(adev->c0_reset);
 819 +       reset_control_assert(adev->c1_reset);
 820 +       reset_control_assert(adev->c2_reset);
 821 +
 822 +       reset_control_deassert(adev->clk_reset);
 823 +       reset_control_deassert(adev->c0_reset);
 824 +       reset_control_deassert(adev->c1_reset);
 825 +       reset_control_deassert(adev->c2_reset);
 826 +
 827 +       adev->channels = devm_kcalloc(adev->dev, ADM_MAX_CHANNELS,
 828 +                               sizeof(*adev->channels), GFP_KERNEL);
 829 +
 830 +       if (!adev->channels) {
 831 +               ret = -ENOMEM;
 832 +               goto err_disable_clks;
 833 +       }
 834 +
 835 +       /* allocate and initialize channels */
 836 +       INIT_LIST_HEAD(&adev->common.channels);
 837 +
 838 +       for (i = 0; i < ADM_MAX_CHANNELS; i++)
 839 +               adm_channel_init(adev, &adev->channels[i], i);
 840 +
 841 +       /* reset CRCIs */
 842 +       for (i = 0; i < 16; i++)
 843 +               writel(ADM_CRCI_CTL_RST, adev->regs +
 844 +                       ADM_CRCI_CTL(i, adev->ee));
 845 +
 846 +       /* configure client interfaces */
 847 +       writel(ADM_CI_RANGE_START(0x40) | ADM_CI_RANGE_END(0xb0) |
 848 +               ADM_CI_BURST_8_WORDS, adev->regs + ADM_CI_CONF(0));
 849 +       writel(ADM_CI_RANGE_START(0x2a) | ADM_CI_RANGE_END(0x2c) |
 850 +               ADM_CI_BURST_8_WORDS, adev->regs + ADM_CI_CONF(1));
 851 +       writel(ADM_CI_RANGE_START(0x12) | ADM_CI_RANGE_END(0x28) |
 852 +               ADM_CI_BURST_8_WORDS, adev->regs + ADM_CI_CONF(2));
 853 +       writel(ADM_GP_CTL_LP_EN | ADM_GP_CTL_LP_CNT(0xf),
 854 +               adev->regs + ADM_GP_CTL);
 855 +
 856 +       ret = devm_request_irq(adev->dev, adev->irq, adm_dma_irq,
 857 +                       0, "adm_dma", adev);
 858 +       if (ret)
 859 +               goto err_disable_clks;
 860 +
 861 +       platform_set_drvdata(pdev, adev);
 862 +
 863 +       adev->common.dev = adev->dev;
 864 +       adev->common.dev->dma_parms = &adev->dma_parms;
 865 +
 866 +       /* set capabilities */
 867 +       dma_cap_zero(adev->common.cap_mask);
 868 +       dma_cap_set(DMA_SLAVE, adev->common.cap_mask);
 869 +       dma_cap_set(DMA_PRIVATE, adev->common.cap_mask);
 870 +
 871 +       /* initialize dmaengine apis */
 872 +       adev->common.directions = BIT(DMA_DEV_TO_MEM | DMA_MEM_TO_DEV);
 873 +       adev->common.residue_granularity = DMA_RESIDUE_GRANULARITY_DESCRIPTOR;
 874 +       adev->common.src_addr_widths = DMA_SLAVE_BUSWIDTH_4_BYTES;
 875 +       adev->common.dst_addr_widths = DMA_SLAVE_BUSWIDTH_4_BYTES;
 876 +       adev->common.device_free_chan_resources = adm_free_chan;
 877 +       adev->common.device_prep_slave_sg = adm_prep_slave_sg;
 878 +       adev->common.device_issue_pending = adm_issue_pending;
 879 +       adev->common.device_tx_status = adm_tx_status;
 880 +       adev->common.device_terminate_all = adm_terminate_all;
 881 +       adev->common.device_config = adm_slave_config;
 882 +
 883 +       ret = dma_async_device_register(&adev->common);
 884 +       if (ret) {
 885 +               dev_err(adev->dev, "failed to register dma async device\n");
 886 +               goto err_disable_clks;
 887 +       }
 888 +
 889 +       ret = of_dma_controller_register(pdev->dev.of_node,
 890 +                                        of_dma_xlate_by_chan_id,
 891 +                                        &adev->common);
 892 +       if (ret)
 893 +               goto err_unregister_dma;
 894 +
 895 +       return 0;
 896 +
 897 +err_unregister_dma:
 898 +       dma_async_device_unregister(&adev->common);
 899 +err_disable_clks:
 900 +       clk_disable_unprepare(adev->iface_clk);
 901 +err_disable_core_clk:
 902 +       clk_disable_unprepare(adev->core_clk);
 903 +
 904 +       return ret;
 905 +}
 906 +
 907 +static int adm_dma_remove(struct platform_device *pdev)
 908 +{
 909 +       struct adm_device *adev = platform_get_drvdata(pdev);
 910 +       struct adm_chan *achan;
 911 +       u32 i;
 912 +
 913 +       of_dma_controller_free(pdev->dev.of_node);
 914 +       dma_async_device_unregister(&adev->common);
 915 +
 916 +       for (i = 0; i < ADM_MAX_CHANNELS; i++) {
 917 +               achan = &adev->channels[i];
 918 +
 919 +               /* mask IRQs for this channel/EE pair */
 920 +               writel(0, adev->regs + ADM_CH_RSLT_CONF(achan->id, adev->ee));
 921 +
 922 +               adm_terminate_all(&adev->channels[i].vc.chan);
 923 +       }
 924 +
 925 +       devm_free_irq(adev->dev, adev->irq, adev);
 926 +
 927 +       clk_disable_unprepare(adev->core_clk);
 928 +       clk_disable_unprepare(adev->iface_clk);
 929 +
 930 +       return 0;
 931 +}
 932 +
 933 +static const struct of_device_id adm_of_match[] = {
 934 +       { .compatible = "qcom,adm", },
 935 +       {}
 936 +};
 937 +MODULE_DEVICE_TABLE(of, adm_of_match);
 938 +
 939 +static struct platform_driver adm_dma_driver = {
 940 +       .probe = adm_dma_probe,
 941 +       .remove = adm_dma_remove,
 942 +       .driver = {
 943 +               .name = "adm-dma-engine",
 944 +               .of_match_table = adm_of_match,
 945 +       },
 946 +};
 947 +
 948 +module_platform_driver(adm_dma_driver);
 949 +
 950 +MODULE_AUTHOR("Andy Gross <agross@codeaurora.org>");
 951 +MODULE_DESCRIPTION("QCOM ADM DMA engine driver");
 952 +MODULE_LICENSE("GPL v2");