target/linux/ipq806x/patches-4.4/713-spi-qup-Fix-block-mode-to-work-correctly.patch

   1 From 148f77310a9ddf4db5036066458d7aed92cea9ae Mon Sep 17 00:00:00 2001
   2 From: Andy Gross <andy.gross@linaro.org>
   3 Date: Sun, 31 Jan 2016 21:28:13 -0600
   4 Subject: [PATCH] spi: qup: Fix block mode to work correctly
   5
   6 This patch corrects the behavior of the BLOCK
   7 transactions.  During block transactions, the controller
   8 must be read/written to in block size transactions.
   9
  10 Signed-off-by: Andy Gross <andy.gross@linaro.org>
  11
  12 Change-Id: I4b4f4d25be57e6e8148f6f0d24bed376eb287ecf
  13 ---
  14  drivers/spi/spi-qup.c | 181 +++++++++++++++++++++++++++++++++++++++-----------
  15  1 file changed, 141 insertions(+), 40 deletions(-)
  16
  17 --- a/drivers/spi/spi-qup.c
  18 +++ b/drivers/spi/spi-qup.c
  19 @@ -83,6 +83,8 @@
  20  #define QUP_IO_M_MODE_BAM              3
  21
  22  /* QUP_OPERATIONAL fields */
  23 +#define QUP_OP_IN_BLOCK_READ_REQ       BIT(13)
  24 +#define QUP_OP_OUT_BLOCK_WRITE_REQ     BIT(12)
  25  #define QUP_OP_MAX_INPUT_DONE_FLAG     BIT(11)
  26  #define QUP_OP_MAX_OUTPUT_DONE_FLAG    BIT(10)
  27  #define QUP_OP_IN_SERVICE_FLAG         BIT(9)
  28 @@ -156,6 +158,12 @@ struct spi_qup {
  29         struct dma_slave_config tx_conf;
  30  };
  31
  32 +static inline bool spi_qup_is_flag_set(struct spi_qup *controller, u32 flag)
  33 +{
  34 +       u32 opflag = readl_relaxed(controller->base + QUP_OPERATIONAL);
  35 +
  36 +       return opflag & flag;
  37 +}
  38
  39  static inline bool spi_qup_is_dma_xfer(int mode)
  40  {
  41 @@ -217,29 +225,26 @@ static int spi_qup_set_state(struct spi_
  42         return 0;
  43  }
  44
  45 -static void spi_qup_fifo_read(struct spi_qup *controller,
  46 -                           struct spi_transfer *xfer)
  47 +static void spi_qup_read_from_fifo(struct spi_qup *controller,
  48 +       struct spi_transfer *xfer, u32 num_words)
  49  {
  50         u8 *rx_buf = xfer->rx_buf;
  51 -       u32 word, state;
  52 -       int idx, shift, w_size;
  53 -
  54 -       w_size = controller->w_size;
  55 +       int i, shift, num_bytes;
  56 +       u32 word;
  57
  58 -       while (controller->rx_bytes < xfer->len) {
  59 -
  60 -               state = readl_relaxed(controller->base + QUP_OPERATIONAL);
  61 -               if (0 == (state & QUP_OP_IN_FIFO_NOT_EMPTY))
  62 -                       break;
  63 +       for (; num_words; num_words--) {
  64
  65                 word = readl_relaxed(controller->base + QUP_INPUT_FIFO);
  66
  67 +               num_bytes = min_t(int, xfer->len - controller->rx_bytes,
  68 +                                       controller->w_size);
  69 +
  70                 if (!rx_buf) {
  71 -                       controller->rx_bytes += w_size;
  72 +                       controller->rx_bytes += num_bytes;
  73                         continue;
  74                 }
  75
  76 -               for (idx = 0; idx < w_size; idx++, controller->rx_bytes++) {
  77 +               for (i = 0; i < num_bytes; i++, controller->rx_bytes++) {
  78                         /*
  79                          * The data format depends on bytes per SPI word:
  80                          *  4 bytes: 0x12345678
  81 @@ -247,38 +252,80 @@ static void spi_qup_fifo_read(struct spi
  82                          *  1 byte : 0x00000012
  83                          */
  84                         shift = BITS_PER_BYTE;
  85 -                       shift *= (w_size - idx - 1);
  86 +                       shift *= (controller->w_size - i - 1);
  87                         rx_buf[controller->rx_bytes] = word >> shift;
  88                 }
  89         }
  90  }
  91
  92 -static void spi_qup_fifo_write(struct spi_qup *controller,
  93 +static void spi_qup_read(struct spi_qup *controller,
  94                             struct spi_transfer *xfer)
  95  {
  96 -       const u8 *tx_buf = xfer->tx_buf;
  97 -       u32 word, state, data;
  98 -       int idx, w_size;
  99 +       u32 remainder, words_per_block, num_words;
 100 +       bool is_block_mode = controller->mode == QUP_IO_M_MODE_BLOCK;
 101 +
 102 +       remainder = DIV_ROUND_UP(xfer->len - controller->rx_bytes,
 103 +                                controller->w_size);
 104 +       words_per_block = controller->in_blk_sz >> 2;
 105 +
 106 +       do {
 107 +               /* ACK by clearing service flag */
 108 +               writel_relaxed(QUP_OP_IN_SERVICE_FLAG,
 109 +                              controller->base + QUP_OPERATIONAL);
 110 +
 111 +               if (is_block_mode) {
 112 +                       num_words = (remainder > words_per_block) ?
 113 +                                       words_per_block : remainder;
 114 +               } else {
 115 +                       if (!spi_qup_is_flag_set(controller,
 116 +                                                QUP_OP_IN_FIFO_NOT_EMPTY))
 117 +                               break;
 118
 119 -       w_size = controller->w_size;
 120 +                       num_words = 1;
 121 +               }
 122 +
 123 +               /* read up to the maximum transfer size available */
 124 +               spi_qup_read_from_fifo(controller, xfer, num_words);
 125
 126 -       while (controller->tx_bytes < xfer->len) {
 127 +               remainder -= num_words;
 128
 129 -               state = readl_relaxed(controller->base + QUP_OPERATIONAL);
 130 -               if (state & QUP_OP_OUT_FIFO_FULL)
 131 +               /* if block mode, check to see if next block is available */
 132 +               if (is_block_mode && !spi_qup_is_flag_set(controller,
 133 +                                       QUP_OP_IN_BLOCK_READ_REQ))
 134                         break;
 135
 136 +       } while (remainder);
 137 +
 138 +       /*
 139 +        * Due to extra stickiness of the QUP_OP_IN_SERVICE_FLAG during block
 140 +        * mode reads, it has to be cleared again at the very end
 141 +        */
 142 +       if (is_block_mode && spi_qup_is_flag_set(controller,
 143 +                               QUP_OP_MAX_INPUT_DONE_FLAG))
 144 +               writel_relaxed(QUP_OP_IN_SERVICE_FLAG,
 145 +                              controller->base + QUP_OPERATIONAL);
 146 +
 147 +}
 148 +
 149 +static void spi_qup_write_to_fifo(struct spi_qup *controller,
 150 +       struct spi_transfer *xfer, u32 num_words)
 151 +{
 152 +       const u8 *tx_buf = xfer->tx_buf;
 153 +       int i, num_bytes;
 154 +       u32 word, data;
 155 +
 156 +       for (; num_words; num_words--) {
 157                 word = 0;
 158 -               for (idx = 0; idx < w_size; idx++, controller->tx_bytes++) {
 159
 160 -                       if (!tx_buf) {
 161 -                               controller->tx_bytes += w_size;
 162 -                               break;
 163 +               num_bytes = min_t(int, xfer->len - controller->tx_bytes,
 164 +                                   controller->w_size);
 165 +               if (tx_buf)
 166 +                       for (i = 0; i < num_bytes; i++) {
 167 +                               data = tx_buf[controller->tx_bytes + i];
 168 +                               word |= data << (BITS_PER_BYTE * (3 - i));
 169                         }
 170
 171 -                       data = tx_buf[controller->tx_bytes];
 172 -                       word |= data << (BITS_PER_BYTE * (3 - idx));
 173 -               }
 174 +               controller->tx_bytes += num_bytes;
 175
 176                 writel_relaxed(word, controller->base + QUP_OUTPUT_FIFO);
 177         }
 178 @@ -291,6 +338,44 @@ static void spi_qup_dma_done(void *data)
 179         complete(done);
 180  }
 181
 182 +static void spi_qup_write(struct spi_qup *controller,
 183 +                           struct spi_transfer *xfer)
 184 +{
 185 +       bool is_block_mode = controller->mode == QUP_IO_M_MODE_BLOCK;
 186 +       u32 remainder, words_per_block, num_words;
 187 +
 188 +       remainder = DIV_ROUND_UP(xfer->len - controller->tx_bytes,
 189 +                                controller->w_size);
 190 +       words_per_block = controller->out_blk_sz >> 2;
 191 +
 192 +       do {
 193 +               /* ACK by clearing service flag */
 194 +               writel_relaxed(QUP_OP_OUT_SERVICE_FLAG,
 195 +                              controller->base + QUP_OPERATIONAL);
 196 +
 197 +               if (is_block_mode) {
 198 +                       num_words = (remainder > words_per_block) ?
 199 +                               words_per_block : remainder;
 200 +               } else {
 201 +                       if (spi_qup_is_flag_set(controller,
 202 +                                               QUP_OP_OUT_FIFO_FULL))
 203 +                               break;
 204 +
 205 +                       num_words = 1;
 206 +               }
 207 +
 208 +               spi_qup_write_to_fifo(controller, xfer, num_words);
 209 +
 210 +               remainder -= num_words;
 211 +
 212 +               /* if block mode, check to see if next block is available */
 213 +               if (is_block_mode && !spi_qup_is_flag_set(controller,
 214 +                                       QUP_OP_OUT_BLOCK_WRITE_REQ))
 215 +                       break;
 216 +
 217 +       } while (remainder);
 218 +}
 219 +
 220  static int spi_qup_prep_sg(struct spi_master *master, struct spi_transfer *xfer,
 221                            enum dma_transfer_direction dir,
 222                            dma_async_tx_callback callback,
 223 @@ -348,11 +433,13 @@ unsigned long timeout)
 224                 return ret;
 225         }
 226
 227 -       if (xfer->rx_buf)
 228 -               rx_done = spi_qup_dma_done;
 229 +       if (!qup->qup_v1) {
 230 +               if (xfer->rx_buf)
 231 +                       rx_done = spi_qup_dma_done;
 232
 233 -       if (xfer->tx_buf)
 234 -               tx_done = spi_qup_dma_done;
 235 +               if (xfer->tx_buf)
 236 +                       tx_done = spi_qup_dma_done;
 237 +       }
 238
 239         if (xfer->rx_buf) {
 240                 ret = spi_qup_prep_sg(master, xfer, DMA_DEV_TO_MEM, rx_done,
 241 @@ -401,7 +488,7 @@ static int spi_qup_do_pio(struct spi_mas
 242         }
 243
 244         if (qup->mode == QUP_IO_M_MODE_FIFO)
 245 -               spi_qup_fifo_write(qup, xfer);
 246 +               spi_qup_write(qup, xfer);
 247
 248         ret = spi_qup_set_state(qup, QUP_STATE_RUN);
 249         if (ret) {
 250 @@ -434,10 +521,11 @@ static irqreturn_t spi_qup_qup_irq(int i
 251
 252         writel_relaxed(qup_err, controller->base + QUP_ERROR_FLAGS);
 253         writel_relaxed(spi_err, controller->base + SPI_ERROR_FLAGS);
 254 -       writel_relaxed(opflags, controller->base + QUP_OPERATIONAL);
 255
 256         if (!xfer) {
 257 -               dev_err_ratelimited(controller->dev, "unexpected irq %08x %08x %08x\n",
 258 +               writel_relaxed(opflags, controller->base + QUP_OPERATIONAL);
 259 +               dev_err_ratelimited(controller->dev,
 260 +                                   "unexpected irq %08x %08x %08x\n",
 261                                     qup_err, spi_err, opflags);
 262                 return IRQ_HANDLED;
 263         }
 264 @@ -463,12 +551,20 @@ static irqreturn_t spi_qup_qup_irq(int i
 265                 error = -EIO;
 266         }
 267
 268 -       if (!spi_qup_is_dma_xfer(controller->mode)) {
 269 +       if (spi_qup_is_dma_xfer(controller->mode)) {
 270 +               writel_relaxed(opflags, controller->base + QUP_OPERATIONAL);
 271 +               if (opflags & QUP_OP_IN_SERVICE_FLAG &&
 272 +                   opflags & QUP_OP_MAX_INPUT_DONE_FLAG)
 273 +                       complete(&controller->done);
 274 +               if (opflags & QUP_OP_OUT_SERVICE_FLAG &&
 275 +                   opflags & QUP_OP_MAX_OUTPUT_DONE_FLAG)
 276 +                       complete(&controller->dma_tx_done);
 277 +       } else {
 278                 if (opflags & QUP_OP_IN_SERVICE_FLAG)
 279 -                       spi_qup_fifo_read(controller, xfer);
 280 +                       spi_qup_read(controller, xfer);
 281
 282                 if (opflags & QUP_OP_OUT_SERVICE_FLAG)
 283 -                       spi_qup_fifo_write(controller, xfer);
 284 +                       spi_qup_write(controller, xfer);
 285         }
 286
 287         spin_lock_irqsave(&controller->lock, flags);
 288 @@ -476,6 +572,9 @@ static irqreturn_t spi_qup_qup_irq(int i
 289         controller->xfer = xfer;
 290         spin_unlock_irqrestore(&controller->lock, flags);
 291
 292 +       /* re-read opflags as flags may have changed due to actions above */
 293 +       opflags = readl_relaxed(controller->base + QUP_OPERATIONAL);
 294 +
 295         if ((controller->rx_bytes == xfer->len &&
 296                 (opflags & QUP_OP_MAX_INPUT_DONE_FLAG)) ||  error)
 297                 complete(&controller->done);
 298 @@ -519,11 +618,13 @@ static int spi_qup_io_config(struct spi_
 299                 /* must be zero for FIFO */
 300                 writel_relaxed(0, controller->base + QUP_MX_INPUT_CNT);
 301                 writel_relaxed(0, controller->base + QUP_MX_OUTPUT_CNT);
 302 -               controller->use_dma = 0;
 303         } else if (spi->master->can_dma &&
 304             spi->master->can_dma(spi->master, spi, xfer) &&
 305             spi->master->cur_msg_mapped) {
 306                 controller->mode = QUP_IO_M_MODE_BAM;
 307 +               writel_relaxed(n_words, controller->base + QUP_MX_INPUT_CNT);
 308 +               writel_relaxed(n_words, controller->base + QUP_MX_OUTPUT_CNT);
 309 +               /* must be zero for BLOCK and BAM */
 310                 writel_relaxed(0, controller->base + QUP_MX_READ_CNT);
 311                 writel_relaxed(0, controller->base + QUP_MX_WRITE_CNT);
 312