target/linux/ipq806x/patches-4.4/709-spi-qup-Fix-fifo-and-dma-support-for-IPQ806x.patch

   1 From 16d2871830ff3fe12a6bff582549a9264adff278 Mon Sep 17 00:00:00 2001
   2 From: Ram Chandra Jangir <rjangi@codeaurora.org>
   3 Date: Tue, 10 May 2016 20:19:31 +0530
   4 Subject: [PATCH] spi: qup: Fix fifo and dma support for IPQ806x
   5
   6 Signed-off-by: Ram Chandra Jangir <rjangi@codeaurora.org>
   7 ---
   8  drivers/spi/spi-qup.c | 54 +++++++++++++++++++++++++++++++++++++++++++++++++--
   9  1 file changed, 52 insertions(+), 2 deletions(-)
  10
  11 diff --git a/drivers/spi/spi-qup.c b/drivers/spi/spi-qup.c
  12 index 810a7fa..0808017 100644
  13 --- a/drivers/spi/spi-qup.c
  14 +++ b/drivers/spi/spi-qup.c
  15 @@ -24,6 +24,7 @@
  16  #include <linux/spi/spi.h>
  17  #include <linux/dmaengine.h>
  18  #include <linux/dma-mapping.h>
  19 +#include <linux/gpio.h>
  20
  21  #define QUP_CONFIG                     0x0000
  22  #define QUP_STATE                      0x0004
  23 @@ -152,6 +153,7 @@ struct spi_qup {
  24         int                     use_dma;
  25         struct dma_slave_config rx_conf;
  26         struct dma_slave_config tx_conf;
  27 +       int mode;
  28  };
  29
  30
  31 @@ -370,7 +372,8 @@ static int spi_qup_do_pio(struct spi_master *master, struct spi_transfer *xfer)
  32                 return ret;
  33         }
  34
  35 -       spi_qup_fifo_write(qup, xfer);
  36 +       if (qup->mode == QUP_IO_M_MODE_FIFO)
  37 +               spi_qup_fifo_write(qup, xfer);
  38
  39         return 0;
  40  }
  41 @@ -448,6 +451,7 @@ spi_qup_get_mode(struct spi_master *master, struct spi_transfer *xfer)
  42  {
  43         struct spi_qup *qup = spi_master_get_devdata(master);
  44         u32 mode;
  45 +       size_t dma_align = dma_get_cache_alignment();
  46
  47         qup->w_size = 4;
  48
  49 @@ -458,6 +462,14 @@ spi_qup_get_mode(struct spi_master *master, struct spi_transfer *xfer)
  50
  51         qup->n_words = xfer->len / qup->w_size;
  52
  53 +       if (!IS_ERR_OR_NULL(master->dma_rx) &&
  54 +                       IS_ALIGNED((size_t)xfer->tx_buf, dma_align) &&
  55 +                       IS_ALIGNED((size_t)xfer->rx_buf, dma_align) &&
  56 +                       !is_vmalloc_addr(xfer->tx_buf) &&
  57 +                       !is_vmalloc_addr(xfer->rx_buf) &&
  58 +                       (xfer->len > 3*qup->in_blk_sz))
  59 +               qup->use_dma = 1;
  60 +
  61         if (qup->n_words <= (qup->in_fifo_sz / sizeof(u32)))
  62                 mode = QUP_IO_M_MODE_FIFO;
  63         else
  64 @@ -491,7 +503,7 @@ static int spi_qup_io_config(struct spi_device *spi, struct spi_transfer *xfer)
  65                 return -EIO;
  66         }
  67
  68 -       mode = spi_qup_get_mode(spi->master, xfer);
  69 +       controller->mode = mode = spi_qup_get_mode(spi->master, xfer);
  70         n_words = controller->n_words;
  71
  72         if (mode == QUP_IO_M_MODE_FIFO) {
  73 @@ -500,6 +512,7 @@ static int spi_qup_io_config(struct spi_device *spi, struct spi_transfer *xfer)
  74                 /* must be zero for FIFO */
  75                 writel_relaxed(0, controller->base + QUP_MX_INPUT_CNT);
  76                 writel_relaxed(0, controller->base + QUP_MX_OUTPUT_CNT);
  77 +               controller->use_dma = 0;
  78         } else if (!controller->use_dma) {
  79                 writel_relaxed(n_words, controller->base + QUP_MX_INPUT_CNT);
  80                 writel_relaxed(n_words, controller->base + QUP_MX_OUTPUT_CNT);
  81 @@ -750,6 +763,38 @@ err_tx:
  82         return ret;
  83  }
  84
  85 +static void spi_qup_set_cs(struct spi_device *spi, bool val)
  86 +{
  87 +       struct spi_qup *controller;
  88 +       u32 spi_ioc;
  89 +       u32 spi_ioc_orig;
  90 +
  91 +       controller = spi_master_get_devdata(spi->master);
  92 +       spi_ioc = readl_relaxed(controller->base + SPI_IO_CONTROL);
  93 +       spi_ioc_orig = spi_ioc;
  94 +       if (!val)
  95 +               spi_ioc |= SPI_IO_C_FORCE_CS;
  96 +       else
  97 +               spi_ioc &= ~SPI_IO_C_FORCE_CS;
  98 +
  99 +       if (spi_ioc != spi_ioc_orig)
 100 +               writel_relaxed(spi_ioc, controller->base + SPI_IO_CONTROL);
 101 +}
 102 +
 103 +static int spi_qup_setup(struct spi_device *spi)
 104 +{
 105 +       if (spi->cs_gpio >= 0) {
 106 +               if (spi->mode & SPI_CS_HIGH)
 107 +                       gpio_set_value(spi->cs_gpio, 0);
 108 +               else
 109 +                       gpio_set_value(spi->cs_gpio, 1);
 110 +
 111 +               udelay(10);
 112 +       }
 113 +
 114 +       return 0;
 115 +}
 116 +
 117  static int spi_qup_probe(struct platform_device *pdev)
 118  {
 119         struct spi_master *master;
 120 @@ -846,6 +891,11 @@ static int spi_qup_probe(struct platform_device *pdev)
 121         if (of_device_is_compatible(dev->of_node, "qcom,spi-qup-v1.1.1"))
 122                 controller->qup_v1 = 1;
 123
 124 +       if (!controller->qup_v1)
 125 +               master->set_cs = spi_qup_set_cs;
 126 +       else
 127 +               master->setup = spi_qup_setup;
 128 +
 129         spin_lock_init(&controller->lock);
 130         init_completion(&controller->done);
 131
 132 --
 133 2.7.2
 134