1 From f26cc3733bdd697bd81ae505fc133fa7c9b6ea19 Mon Sep 17 00:00:00 2001
2 From: Mathieu Olivari <mathieu@codeaurora.org>
3 Date: Tue, 7 Apr 2015 19:58:58 -0700
4 Subject: [PATCH] ARM: dts: qcom: add initial DB149 device-tree
6 Add basic DB149 (IPQ806x based platform) device-tree. It supports UART,
7 SATA, USB2, USB3 and NOR flash.
9 Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
11 arch/arm/boot/dts/Makefile | 1 +
12 arch/arm/boot/dts/qcom-ipq8064-db149.dts | 132 +++++++++++++++++++++++++++++++
13 2 files changed, 133 insertions(+)
14 create mode 100644 arch/arm/boot/dts/qcom-ipq8064-db149.dts
16 --- a/arch/arm/boot/dts/Makefile
17 +++ b/arch/arm/boot/dts/Makefile
18 @@ -506,6 +506,7 @@ dtb-$(CONFIG_ARCH_QCOM) += \
19 qcom-apq8084-ifc6540.dtb \
20 qcom-apq8084-mtp.dtb \
21 qcom-ipq8064-ap148.dtb \
22 + qcom-ipq8064-db149.dtb \
23 qcom-msm8660-surf.dtb \
24 qcom-msm8960-cdp.dtb \
25 qcom-msm8974-sony-xperia-honami.dtb
27 +++ b/arch/arm/boot/dts/qcom-ipq8064-db149.dts
29 +#include "qcom-ipq8064-v1.0.dtsi"
32 + model = "Qualcomm IPQ8064/DB149";
33 + compatible = "qcom,ipq8064-db149", "qcom,ipq8064";
36 + #address-cells = <1>;
40 + reg = <0x41200000 0x300000>;
50 + linux,stdout-path = "serial0:115200n8";
55 + i2c4_pins: i2c4_pinmux {
56 + pins = "gpio12", "gpio13";
61 + spi_pins: spi_pins {
63 + pins = "gpio18", "gpio19", "gpio21";
65 + drive-strength = <10>;
71 + gsbi2: gsbi@12480000 {
72 + qcom,mode = <GSBI_PROT_I2C_UART>;
74 + uart2: serial@12490000 {
79 + gsbi5: gsbi@1a200000 {
80 + qcom,mode = <GSBI_PROT_SPI>;
83 + spi4: spi@1a280000 {
85 + spi-max-frequency = <50000000>;
87 + pinctrl-0 = <&spi_pins>;
88 + pinctrl-names = "default";
90 + cs-gpios = <&qcom_pinmux 20 0>;
93 + compatible = "s25fl256s1";
94 + #address-cells = <1>;
96 + spi-max-frequency = <50000000>;
101 + label = "lowlevel_init";
102 + reg = <0x0 0x1b0000>;
107 + reg = <0x1b0000 0x80000>;
111 + label = "u-boot-env";
112 + reg = <0x230000 0x40000>;
117 + reg = <0x270000 0x40000>;
121 + label = "firmware";
122 + reg = <0x2b0000 0x1d50000>;
128 + sata-phy@1b400000 {
136 + phy@100f8800 { /* USB3 port 1 HS phy */
140 + phy@100f8830 { /* USB3 port 1 SS phy */
144 + phy@110f8800 { /* USB3 port 0 HS phy */
148 + phy@110f8830 { /* USB3 port 0 SS phy */