target/linux/ipq806x/patches-4.19/0071-1-PCI-qcom-Fixed-IPQ806x-specific-clocks.patch

   1 From 86655aa14304ca88a8ce8847276147dbc1a83238 Mon Sep 17 00:00:00 2001
   2 From: Sham Muthayyan <smuthayy@codeaurora.org>
   3 Date: Tue, 19 Jul 2016 18:44:49 +0530
   4 Subject: PCI: qcom: Fixed IPQ806x specific clocks
   5
   6 Change-Id: I488e1bc707d6a22b37a338f41935e3922009ba5e
   7 Signed-off-by: Sham Muthayyan <smuthayy@codeaurora.org>
   8 ---
   9
  10 --- a/drivers/pci/controller/dwc/pcie-qcom.c
  11 +++ b/drivers/pci/controller/dwc/pcie-qcom.c
  12 @@ -85,6 +85,8 @@ struct qcom_pcie_resources_2_1_0 {
  13         struct clk *iface_clk;
  14         struct clk *core_clk;
  15         struct clk *phy_clk;
  16 +       struct clk *aux_clk;
  17 +       struct clk *ref_clk;
  18         struct reset_control *pci_reset;
  19         struct reset_control *axi_reset;
  20         struct reset_control *ahb_reset;
  21 @@ -235,6 +237,14 @@ static int qcom_pcie_get_resources_2_1_0
  22         if (IS_ERR(res->phy_clk))
  23                 return PTR_ERR(res->phy_clk);
  24
  25 +       res->aux_clk = devm_clk_get(dev, "aux");
  26 +       if (IS_ERR(res->aux_clk))
  27 +               return PTR_ERR(res->aux_clk);
  28 +
  29 +       res->ref_clk = devm_clk_get(dev, "ref");
  30 +       if (IS_ERR(res->ref_clk))
  31 +               return PTR_ERR(res->ref_clk);
  32 +
  33         res->pci_reset = devm_reset_control_get_exclusive(dev, "pci");
  34         if (IS_ERR(res->pci_reset))
  35                 return PTR_ERR(res->pci_reset);
  36 @@ -267,6 +277,8 @@ static void qcom_pcie_deinit_2_1_0(struc
  37         clk_disable_unprepare(res->iface_clk);
  38         clk_disable_unprepare(res->core_clk);
  39         clk_disable_unprepare(res->phy_clk);
  40 +       clk_disable_unprepare(res->aux_clk);
  41 +       clk_disable_unprepare(res->ref_clk);
  42         regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);
  43  }
  44
  45 @@ -296,16 +308,28 @@ static int qcom_pcie_init_2_1_0(struct q
  46                 goto err_assert_ahb;
  47         }
  48
  49 +       ret = clk_prepare_enable(res->core_clk);
  50 +       if (ret) {
  51 +               dev_err(dev, "cannot prepare/enable core clock\n");
  52 +               goto err_clk_core;
  53 +       }
  54 +
  55         ret = clk_prepare_enable(res->phy_clk);
  56         if (ret) {
  57                 dev_err(dev, "cannot prepare/enable phy clock\n");
  58                 goto err_clk_phy;
  59         }
  60
  61 -       ret = clk_prepare_enable(res->core_clk);
  62 +       ret = clk_prepare_enable(res->aux_clk);
  63         if (ret) {
  64 -               dev_err(dev, "cannot prepare/enable core clock\n");
  65 -               goto err_clk_core;
  66 +               dev_err(dev, "cannot prepare/enable aux clock\n");
  67 +               goto err_clk_aux;
  68 +       }
  69 +
  70 +       ret = clk_prepare_enable(res->ref_clk);
  71 +       if (ret) {
  72 +               dev_err(dev, "cannot prepare/enable ref clock\n");
  73 +               goto err_clk_ref;
  74         }
  75
  76         ret = reset_control_deassert(res->ahb_reset);
  77 @@ -361,10 +385,14 @@ static int qcom_pcie_init_2_1_0(struct q
  78         return 0;
  79
  80  err_deassert_ahb:
  81 -       clk_disable_unprepare(res->core_clk);
  82 -err_clk_core:
  83 +       clk_disable_unprepare(res->ref_clk);
  84 +err_clk_ref:
  85 +       clk_disable_unprepare(res->aux_clk);
  86 +err_clk_aux:
  87         clk_disable_unprepare(res->phy_clk);
  88  err_clk_phy:
  89 +       clk_disable_unprepare(res->core_clk);
  90 +err_clk_core:
  91         clk_disable_unprepare(res->iface_clk);
  92  err_assert_ahb:
  93         regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);