target/linux/ipq806x/patches-4.19/0034-0010-clk-qcom-Add-Krait-clock-controller-driver.patch

   1 From bb5c4a85051e5e0be39c775b6df85521f2ae807d Mon Sep 17 00:00:00 2001
   2 From: Stephen Boyd <sboyd@codeaurora.org>
   3 Date: Tue, 14 Aug 2018 17:42:29 +0530
   4 Subject: [PATCH 10/12] clk: qcom: Add Krait clock controller driver
   5
   6 The Krait CPU clocks are made up of a primary mux and secondary
   7 mux for each CPU and the L2, controlled via cp15 accessors. For
   8 Kraits within KPSSv1 each secondary mux accepts a different aux
   9 source, but on KPSSv2 each secondary mux accepts the same aux
  10 source.
  11
  12 Cc: <devicetree@vger.kernel.org>
  13 Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
  14 Signed-off-by: Sricharan R <sricharan@codeaurora.org>
  15 Tested-by: Craig Tatlor <ctatlor97@gmail.com>
  16 Signed-off-by: Stephen Boyd <sboyd@kernel.org>
  17 ---
  18  drivers/clk/qcom/Kconfig     |   8 +
  19  drivers/clk/qcom/Makefile    |   1 +
  20  drivers/clk/qcom/clk-krait.c |   4 +-
  21  drivers/clk/qcom/krait-cc.c  | 341 +++++++++++++++++++++++++++++++++++
  22  4 files changed, 352 insertions(+), 2 deletions(-)
  23  create mode 100644 drivers/clk/qcom/krait-cc.c
  24
  25 --- a/drivers/clk/qcom/Kconfig
  26 +++ b/drivers/clk/qcom/Kconfig
  27 @@ -292,3 +292,11 @@ config KPSS_XCC
  28           Support for the Krait ACC and GCC clock controllers. Say Y
  29           if you want to support CPU frequency scaling on devices such
  30           as MSM8960, APQ8064, etc.
  31 +
  32 +config KRAITCC
  33 +       tristate "Krait Clock Controller"
  34 +       depends on COMMON_CLK_QCOM && ARM
  35 +       select KRAIT_CLOCKS
  36 +       help
  37 +         Support for the Krait CPU clocks on Qualcomm devices.
  38 +         Say Y if you want to support CPU frequency scaling.
  39 --- a/drivers/clk/qcom/Makefile
  40 +++ b/drivers/clk/qcom/Makefile
  41 @@ -47,3 +47,4 @@ obj-$(CONFIG_SDM_VIDEOCC_845) += videocc
  42  obj-$(CONFIG_SPMI_PMIC_CLKDIV) += clk-spmi-pmic-div.o
  43  obj-$(CONFIG_KPSS_XCC) += kpss-xcc.o
  44  obj-$(CONFIG_QCOM_HFPLL) += hfpll.o
  45 +obj-$(CONFIG_KRAITCC) += krait-cc.o
  46 --- a/drivers/clk/qcom/clk-krait.c
  47 +++ b/drivers/clk/qcom/clk-krait.c
  48 @@ -44,7 +44,7 @@ static int krait_mux_set_parent(struct c
  49         struct krait_mux_clk *mux = to_krait_mux_clk(hw);
  50         u32 sel;
  51
  52 -       sel = clk_mux_reindex(index, mux->parent_map, 0);
  53 +       sel = clk_mux_index_to_val(mux->parent_map, 0, index);
  54         mux->en_mask = sel;
  55         /* Don't touch mux if CPU is off as it won't work */
  56         if (__clk_is_enabled(hw->clk))
  57 @@ -63,7 +63,7 @@ static u8 krait_mux_get_parent(struct cl
  58         sel &= mux->mask;
  59         mux->en_mask = sel;
  60
  61 -       return clk_mux_get_parent(hw, sel, mux->parent_map, 0);
  62 +       return clk_mux_val_to_index(hw, mux->parent_map, 0, sel);
  63  }
  64
  65  const struct clk_ops krait_mux_clk_ops = {
  66 --- /dev/null
  67 +++ b/drivers/clk/qcom/krait-cc.c
  68 @@ -0,0 +1,341 @@
  69 +// SPDX-License-Identifier: GPL-2.0
  70 +// Copyright (c) 2018, The Linux Foundation. All rights reserved.
  71 +
  72 +#include <linux/kernel.h>
  73 +#include <linux/init.h>
  74 +#include <linux/module.h>
  75 +#include <linux/platform_device.h>
  76 +#include <linux/err.h>
  77 +#include <linux/io.h>
  78 +#include <linux/of.h>
  79 +#include <linux/of_device.h>
  80 +#include <linux/clk.h>
  81 +#include <linux/clk-provider.h>
  82 +#include <linux/slab.h>
  83 +
  84 +#include "clk-krait.h"
  85 +
  86 +static unsigned int sec_mux_map[] = {
  87 +       2,
  88 +       0,
  89 +};
  90 +
  91 +static unsigned int pri_mux_map[] = {
  92 +       1,
  93 +       2,
  94 +       0,
  95 +};
  96 +
  97 +static int
  98 +krait_add_div(struct device *dev, int id, const char *s, unsigned int offset)
  99 +{
 100 +       struct krait_div2_clk *div;
 101 +       struct clk_init_data init = {
 102 +               .num_parents = 1,
 103 +               .ops = &krait_div2_clk_ops,
 104 +               .flags = CLK_SET_RATE_PARENT,
 105 +       };
 106 +       const char *p_names[1];
 107 +       struct clk *clk;
 108 +
 109 +       div = devm_kzalloc(dev, sizeof(*div), GFP_KERNEL);
 110 +       if (!div)
 111 +               return -ENOMEM;
 112 +
 113 +       div->width = 2;
 114 +       div->shift = 6;
 115 +       div->lpl = id >= 0;
 116 +       div->offset = offset;
 117 +       div->hw.init = &init;
 118 +
 119 +       init.name = kasprintf(GFP_KERNEL, "hfpll%s_div", s);
 120 +       if (!init.name)
 121 +               return -ENOMEM;
 122 +
 123 +       init.parent_names = p_names;
 124 +       p_names[0] = kasprintf(GFP_KERNEL, "hfpll%s", s);
 125 +       if (!p_names[0]) {
 126 +               kfree(init.name);
 127 +               return -ENOMEM;
 128 +       }
 129 +
 130 +       clk = devm_clk_register(dev, &div->hw);
 131 +       kfree(p_names[0]);
 132 +       kfree(init.name);
 133 +
 134 +       return PTR_ERR_OR_ZERO(clk);
 135 +}
 136 +
 137 +static int
 138 +krait_add_sec_mux(struct device *dev, int id, const char *s,
 139 +                 unsigned int offset, bool unique_aux)
 140 +{
 141 +       struct krait_mux_clk *mux;
 142 +       static const char *sec_mux_list[] = {
 143 +               "acpu_aux",
 144 +               "qsb",
 145 +       };
 146 +       struct clk_init_data init = {
 147 +               .parent_names = sec_mux_list,
 148 +               .num_parents = ARRAY_SIZE(sec_mux_list),
 149 +               .ops = &krait_mux_clk_ops,
 150 +               .flags = CLK_SET_RATE_PARENT,
 151 +       };
 152 +       struct clk *clk;
 153 +
 154 +       mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL);
 155 +       if (!mux)
 156 +               return -ENOMEM;
 157 +
 158 +       mux->offset = offset;
 159 +       mux->lpl = id >= 0;
 160 +       mux->mask = 0x3;
 161 +       mux->shift = 2;
 162 +       mux->parent_map = sec_mux_map;
 163 +       mux->hw.init = &init;
 164 +
 165 +       init.name = kasprintf(GFP_KERNEL, "krait%s_sec_mux", s);
 166 +       if (!init.name)
 167 +               return -ENOMEM;
 168 +
 169 +       if (unique_aux) {
 170 +               sec_mux_list[0] = kasprintf(GFP_KERNEL, "acpu%s_aux", s);
 171 +               if (!sec_mux_list[0]) {
 172 +                       clk = ERR_PTR(-ENOMEM);
 173 +                       goto err_aux;
 174 +               }
 175 +       }
 176 +
 177 +       clk = devm_clk_register(dev, &mux->hw);
 178 +
 179 +       if (unique_aux)
 180 +               kfree(sec_mux_list[0]);
 181 +err_aux:
 182 +       kfree(init.name);
 183 +       return PTR_ERR_OR_ZERO(clk);
 184 +}
 185 +
 186 +static struct clk *
 187 +krait_add_pri_mux(struct device *dev, int id, const char *s,
 188 +                 unsigned int offset)
 189 +{
 190 +       struct krait_mux_clk *mux;
 191 +       const char *p_names[3];
 192 +       struct clk_init_data init = {
 193 +               .parent_names = p_names,
 194 +               .num_parents = ARRAY_SIZE(p_names),
 195 +               .ops = &krait_mux_clk_ops,
 196 +               .flags = CLK_SET_RATE_PARENT,
 197 +       };
 198 +       struct clk *clk;
 199 +
 200 +       mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL);
 201 +       if (!mux)
 202 +               return ERR_PTR(-ENOMEM);
 203 +
 204 +       mux->mask = 0x3;
 205 +       mux->shift = 0;
 206 +       mux->offset = offset;
 207 +       mux->lpl = id >= 0;
 208 +       mux->parent_map = pri_mux_map;
 209 +       mux->hw.init = &init;
 210 +
 211 +       init.name = kasprintf(GFP_KERNEL, "krait%s_pri_mux", s);
 212 +       if (!init.name)
 213 +               return ERR_PTR(-ENOMEM);
 214 +
 215 +       p_names[0] = kasprintf(GFP_KERNEL, "hfpll%s", s);
 216 +       if (!p_names[0]) {
 217 +               clk = ERR_PTR(-ENOMEM);
 218 +               goto err_p0;
 219 +       }
 220 +
 221 +       p_names[1] = kasprintf(GFP_KERNEL, "hfpll%s_div", s);
 222 +       if (!p_names[1]) {
 223 +               clk = ERR_PTR(-ENOMEM);
 224 +               goto err_p1;
 225 +       }
 226 +
 227 +       p_names[2] = kasprintf(GFP_KERNEL, "krait%s_sec_mux", s);
 228 +       if (!p_names[2]) {
 229 +               clk = ERR_PTR(-ENOMEM);
 230 +               goto err_p2;
 231 +       }
 232 +
 233 +       clk = devm_clk_register(dev, &mux->hw);
 234 +
 235 +       kfree(p_names[2]);
 236 +err_p2:
 237 +       kfree(p_names[1]);
 238 +err_p1:
 239 +       kfree(p_names[0]);
 240 +err_p0:
 241 +       kfree(init.name);
 242 +       return clk;
 243 +}
 244 +
 245 +/* id < 0 for L2, otherwise id == physical CPU number */
 246 +static struct clk *krait_add_clks(struct device *dev, int id, bool unique_aux)
 247 +{
 248 +       int ret;
 249 +       unsigned int offset;
 250 +       void *p = NULL;
 251 +       const char *s;
 252 +       struct clk *clk;
 253 +
 254 +       if (id >= 0) {
 255 +               offset = 0x4501 + (0x1000 * id);
 256 +               s = p = kasprintf(GFP_KERNEL, "%d", id);
 257 +               if (!s)
 258 +                       return ERR_PTR(-ENOMEM);
 259 +       } else {
 260 +               offset = 0x500;
 261 +               s = "_l2";
 262 +       }
 263 +
 264 +       ret = krait_add_div(dev, id, s, offset);
 265 +       if (ret) {
 266 +               clk = ERR_PTR(ret);
 267 +               goto err;
 268 +       }
 269 +
 270 +       ret = krait_add_sec_mux(dev, id, s, offset, unique_aux);
 271 +       if (ret) {
 272 +               clk = ERR_PTR(ret);
 273 +               goto err;
 274 +       }
 275 +
 276 +       clk = krait_add_pri_mux(dev, id, s, offset);
 277 +err:
 278 +       kfree(p);
 279 +       return clk;
 280 +}
 281 +
 282 +static struct clk *krait_of_get(struct of_phandle_args *clkspec, void *data)
 283 +{
 284 +       unsigned int idx = clkspec->args[0];
 285 +       struct clk **clks = data;
 286 +
 287 +       if (idx >= 5) {
 288 +               pr_err("%s: invalid clock index %d\n", __func__, idx);
 289 +               return ERR_PTR(-EINVAL);
 290 +       }
 291 +
 292 +       return clks[idx] ? : ERR_PTR(-ENODEV);
 293 +}
 294 +
 295 +static const struct of_device_id krait_cc_match_table[] = {
 296 +       { .compatible = "qcom,krait-cc-v1", (void *)1UL },
 297 +       { .compatible = "qcom,krait-cc-v2" },
 298 +       {}
 299 +};
 300 +MODULE_DEVICE_TABLE(of, krait_cc_match_table);
 301 +
 302 +static int krait_cc_probe(struct platform_device *pdev)
 303 +{
 304 +       struct device *dev = &pdev->dev;
 305 +       const struct of_device_id *id;
 306 +       unsigned long cur_rate, aux_rate;
 307 +       int cpu;
 308 +       struct clk *clk;
 309 +       struct clk **clks;
 310 +       struct clk *l2_pri_mux_clk;
 311 +
 312 +       id = of_match_device(krait_cc_match_table, dev);
 313 +       if (!id)
 314 +               return -ENODEV;
 315 +
 316 +       /* Rate is 1 because 0 causes problems for __clk_mux_determine_rate */
 317 +       clk = clk_register_fixed_rate(dev, "qsb", NULL, 0, 1);
 318 +       if (IS_ERR(clk))
 319 +               return PTR_ERR(clk);
 320 +
 321 +       if (!id->data) {
 322 +               clk = clk_register_fixed_factor(dev, "acpu_aux",
 323 +                                               "gpll0_vote", 0, 1, 2);
 324 +               if (IS_ERR(clk))
 325 +                       return PTR_ERR(clk);
 326 +       }
 327 +
 328 +       /* Krait configurations have at most 4 CPUs and one L2 */
 329 +       clks = devm_kcalloc(dev, 5, sizeof(*clks), GFP_KERNEL);
 330 +       if (!clks)
 331 +               return -ENOMEM;
 332 +
 333 +       for_each_possible_cpu(cpu) {
 334 +               clk = krait_add_clks(dev, cpu, id->data);
 335 +               if (IS_ERR(clk))
 336 +                       return PTR_ERR(clk);
 337 +               clks[cpu] = clk;
 338 +       }
 339 +
 340 +       l2_pri_mux_clk = krait_add_clks(dev, -1, id->data);
 341 +       if (IS_ERR(l2_pri_mux_clk))
 342 +               return PTR_ERR(l2_pri_mux_clk);
 343 +       clks[4] = l2_pri_mux_clk;
 344 +
 345 +       /*
 346 +        * We don't want the CPU or L2 clocks to be turned off at late init
 347 +        * if CPUFREQ or HOTPLUG configs are disabled. So, bump up the
 348 +        * refcount of these clocks. Any cpufreq/hotplug manager can assume
 349 +        * that the clocks have already been prepared and enabled by the time
 350 +        * they take over.
 351 +        */
 352 +       for_each_online_cpu(cpu) {
 353 +               clk_prepare_enable(l2_pri_mux_clk);
 354 +               WARN(clk_prepare_enable(clks[cpu]),
 355 +                    "Unable to turn on CPU%d clock", cpu);
 356 +       }
 357 +
 358 +       /*
 359 +        * Force reinit of HFPLLs and muxes to overwrite any potential
 360 +        * incorrect configuration of HFPLLs and muxes by the bootloader.
 361 +        * While at it, also make sure the cores are running at known rates
 362 +        * and print the current rate.
 363 +        *
 364 +        * The clocks are set to aux clock rate first to make sure the
 365 +        * secondary mux is not sourcing off of QSB. The rate is then set to
 366 +        * two different rates to force a HFPLL reinit under all
 367 +        * circumstances.
 368 +        */
 369 +       cur_rate = clk_get_rate(l2_pri_mux_clk);
 370 +       aux_rate = 384000000;
 371 +       if (cur_rate == 1) {
 372 +               pr_info("L2 @ QSB rate. Forcing new rate.\n");
 373 +               cur_rate = aux_rate;
 374 +       }
 375 +       clk_set_rate(l2_pri_mux_clk, aux_rate);
 376 +       clk_set_rate(l2_pri_mux_clk, 2);
 377 +       clk_set_rate(l2_pri_mux_clk, cur_rate);
 378 +       pr_info("L2 @ %lu KHz\n", clk_get_rate(l2_pri_mux_clk) / 1000);
 379 +       for_each_possible_cpu(cpu) {
 380 +               clk = clks[cpu];
 381 +               cur_rate = clk_get_rate(clk);
 382 +               if (cur_rate == 1) {
 383 +                       pr_info("CPU%d @ QSB rate. Forcing new rate.\n", cpu);
 384 +                       cur_rate = aux_rate;
 385 +               }
 386 +
 387 +               clk_set_rate(clk, aux_rate);
 388 +               clk_set_rate(clk, 2);
 389 +               clk_set_rate(clk, cur_rate);
 390 +               pr_info("CPU%d @ %lu KHz\n", cpu, clk_get_rate(clk) / 1000);
 391 +       }
 392 +
 393 +       of_clk_add_provider(dev->of_node, krait_of_get, clks);
 394 +
 395 +       return 0;
 396 +}
 397 +
 398 +static struct platform_driver krait_cc_driver = {
 399 +       .probe = krait_cc_probe,
 400 +       .driver = {
 401 +               .name = "krait-cc",
 402 +               .of_match_table = krait_cc_match_table,
 403 +       },
 404 +};
 405 +module_platform_driver(krait_cc_driver);
 406 +
 407 +MODULE_DESCRIPTION("Krait CPU Clock Driver");
 408 +MODULE_LICENSE("GPL v2");
 409 +MODULE_ALIAS("platform:krait-cc");