target/linux/ipq806x/patches-4.19/0034-0005-clk-qcom-Add-MSM8960-APQ8064-s-HFPLLs.patch

   1 From 72ad7207954dd622a662ba884dc6c30a820123f2 Mon Sep 17 00:00:00 2001
   2 From: Stephen Boyd <sboyd@codeaurora.org>
   3 Date: Tue, 14 Aug 2018 17:42:24 +0530
   4 Subject: [PATCH 05/12] clk: qcom: Add MSM8960/APQ8064's HFPLLs
   5
   6 Describe the HFPLLs present on MSM8960 and APQ8064 devices.
   7
   8 Acked-by: Rob Herring <robh@kernel.org> (bindings)
   9 Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
  10 Signed-off-by: Sricharan R <sricharan@codeaurora.org>
  11 Tested-by: Craig Tatlor <ctatlor97@gmail.com>
  12 Signed-off-by: Stephen Boyd <sboyd@kernel.org>
  13 ---
  14  drivers/clk/qcom/gcc-msm8960.c               | 172 +++++++++++++++++++
  15  include/dt-bindings/clock/qcom,gcc-msm8960.h |   2 +
  16  2 files changed, 174 insertions(+)
  17
  18 --- a/drivers/clk/qcom/gcc-msm8960.c
  19 +++ b/drivers/clk/qcom/gcc-msm8960.c
  20 @@ -30,6 +30,7 @@
  21  #include "clk-pll.h"
  22  #include "clk-rcg.h"
  23  #include "clk-branch.h"
  24 +#include "clk-hfpll.h"
  25  #include "reset.h"
  26
  27  static struct clk_pll pll3 = {
  28 @@ -86,6 +87,164 @@ static struct clk_regmap pll8_vote = {
  29         },
  30  };
  31
  32 +static struct hfpll_data hfpll0_data = {
  33 +       .mode_reg = 0x3200,
  34 +       .l_reg = 0x3208,
  35 +       .m_reg = 0x320c,
  36 +       .n_reg = 0x3210,
  37 +       .config_reg = 0x3204,
  38 +       .status_reg = 0x321c,
  39 +       .config_val = 0x7845c665,
  40 +       .droop_reg = 0x3214,
  41 +       .droop_val = 0x0108c000,
  42 +       .min_rate = 600000000UL,
  43 +       .max_rate = 1800000000UL,
  44 +};
  45 +
  46 +static struct clk_hfpll hfpll0 = {
  47 +       .d = &hfpll0_data,
  48 +       .clkr.hw.init = &(struct clk_init_data){
  49 +               .parent_names = (const char *[]){ "pxo" },
  50 +               .num_parents = 1,
  51 +               .name = "hfpll0",
  52 +               .ops = &clk_ops_hfpll,
  53 +               .flags = CLK_IGNORE_UNUSED,
  54 +       },
  55 +       .lock = __SPIN_LOCK_UNLOCKED(hfpll0.lock),
  56 +};
  57 +
  58 +static struct hfpll_data hfpll1_8064_data = {
  59 +       .mode_reg = 0x3240,
  60 +       .l_reg = 0x3248,
  61 +       .m_reg = 0x324c,
  62 +       .n_reg = 0x3250,
  63 +       .config_reg = 0x3244,
  64 +       .status_reg = 0x325c,
  65 +       .config_val = 0x7845c665,
  66 +       .droop_reg = 0x3254,
  67 +       .droop_val = 0x0108c000,
  68 +       .min_rate = 600000000UL,
  69 +       .max_rate = 1800000000UL,
  70 +};
  71 +
  72 +static struct hfpll_data hfpll1_data = {
  73 +       .mode_reg = 0x3300,
  74 +       .l_reg = 0x3308,
  75 +       .m_reg = 0x330c,
  76 +       .n_reg = 0x3310,
  77 +       .config_reg = 0x3304,
  78 +       .status_reg = 0x331c,
  79 +       .config_val = 0x7845c665,
  80 +       .droop_reg = 0x3314,
  81 +       .droop_val = 0x0108c000,
  82 +       .min_rate = 600000000UL,
  83 +       .max_rate = 1800000000UL,
  84 +};
  85 +
  86 +static struct clk_hfpll hfpll1 = {
  87 +       .d = &hfpll1_data,
  88 +       .clkr.hw.init = &(struct clk_init_data){
  89 +               .parent_names = (const char *[]){ "pxo" },
  90 +               .num_parents = 1,
  91 +               .name = "hfpll1",
  92 +               .ops = &clk_ops_hfpll,
  93 +               .flags = CLK_IGNORE_UNUSED,
  94 +       },
  95 +       .lock = __SPIN_LOCK_UNLOCKED(hfpll1.lock),
  96 +};
  97 +
  98 +static struct hfpll_data hfpll2_data = {
  99 +       .mode_reg = 0x3280,
 100 +       .l_reg = 0x3288,
 101 +       .m_reg = 0x328c,
 102 +       .n_reg = 0x3290,
 103 +       .config_reg = 0x3284,
 104 +       .status_reg = 0x329c,
 105 +       .config_val = 0x7845c665,
 106 +       .droop_reg = 0x3294,
 107 +       .droop_val = 0x0108c000,
 108 +       .min_rate = 600000000UL,
 109 +       .max_rate = 1800000000UL,
 110 +};
 111 +
 112 +static struct clk_hfpll hfpll2 = {
 113 +       .d = &hfpll2_data,
 114 +       .clkr.hw.init = &(struct clk_init_data){
 115 +               .parent_names = (const char *[]){ "pxo" },
 116 +               .num_parents = 1,
 117 +               .name = "hfpll2",
 118 +               .ops = &clk_ops_hfpll,
 119 +               .flags = CLK_IGNORE_UNUSED,
 120 +       },
 121 +       .lock = __SPIN_LOCK_UNLOCKED(hfpll2.lock),
 122 +};
 123 +
 124 +static struct hfpll_data hfpll3_data = {
 125 +       .mode_reg = 0x32c0,
 126 +       .l_reg = 0x32c8,
 127 +       .m_reg = 0x32cc,
 128 +       .n_reg = 0x32d0,
 129 +       .config_reg = 0x32c4,
 130 +       .status_reg = 0x32dc,
 131 +       .config_val = 0x7845c665,
 132 +       .droop_reg = 0x32d4,
 133 +       .droop_val = 0x0108c000,
 134 +       .min_rate = 600000000UL,
 135 +       .max_rate = 1800000000UL,
 136 +};
 137 +
 138 +static struct clk_hfpll hfpll3 = {
 139 +       .d = &hfpll3_data,
 140 +       .clkr.hw.init = &(struct clk_init_data){
 141 +               .parent_names = (const char *[]){ "pxo" },
 142 +               .num_parents = 1,
 143 +               .name = "hfpll3",
 144 +               .ops = &clk_ops_hfpll,
 145 +               .flags = CLK_IGNORE_UNUSED,
 146 +       },
 147 +       .lock = __SPIN_LOCK_UNLOCKED(hfpll3.lock),
 148 +};
 149 +
 150 +static struct hfpll_data hfpll_l2_8064_data = {
 151 +       .mode_reg = 0x3300,
 152 +       .l_reg = 0x3308,
 153 +       .m_reg = 0x330c,
 154 +       .n_reg = 0x3310,
 155 +       .config_reg = 0x3304,
 156 +       .status_reg = 0x331c,
 157 +       .config_val = 0x7845c665,
 158 +       .droop_reg = 0x3314,
 159 +       .droop_val = 0x0108c000,
 160 +       .min_rate = 600000000UL,
 161 +       .max_rate = 1800000000UL,
 162 +};
 163 +
 164 +static struct hfpll_data hfpll_l2_data = {
 165 +       .mode_reg = 0x3400,
 166 +       .l_reg = 0x3408,
 167 +       .m_reg = 0x340c,
 168 +       .n_reg = 0x3410,
 169 +       .config_reg = 0x3404,
 170 +       .status_reg = 0x341c,
 171 +       .config_val = 0x7845c665,
 172 +       .droop_reg = 0x3414,
 173 +       .droop_val = 0x0108c000,
 174 +       .min_rate = 600000000UL,
 175 +       .max_rate = 1800000000UL,
 176 +};
 177 +
 178 +static struct clk_hfpll hfpll_l2 = {
 179 +       .d = &hfpll_l2_data,
 180 +       .clkr.hw.init = &(struct clk_init_data){
 181 +               .parent_names = (const char *[]){ "pxo" },
 182 +               .num_parents = 1,
 183 +               .name = "hfpll_l2",
 184 +               .ops = &clk_ops_hfpll,
 185 +               .flags = CLK_IGNORE_UNUSED,
 186 +       },
 187 +       .lock = __SPIN_LOCK_UNLOCKED(hfpll_l2.lock),
 188 +};
 189 +
 190  static struct clk_pll pll14 = {
 191         .l_reg = 0x31c4,
 192         .m_reg = 0x31c8,
 193 @@ -3107,6 +3266,9 @@ static struct clk_regmap *gcc_msm8960_cl
 194         [PMIC_ARB1_H_CLK] = &pmic_arb1_h_clk.clkr,
 195         [PMIC_SSBI2_CLK] = &pmic_ssbi2_clk.clkr,
 196         [RPM_MSG_RAM_H_CLK] = &rpm_msg_ram_h_clk.clkr,
 197 +       [PLL9] = &hfpll0.clkr,
 198 +       [PLL10] = &hfpll1.clkr,
 199 +       [PLL12] = &hfpll_l2.clkr,
 200  };
 201
 202  static const struct qcom_reset_map gcc_msm8960_resets[] = {
 203 @@ -3318,6 +3480,11 @@ static struct clk_regmap *gcc_apq8064_cl
 204         [PMIC_ARB1_H_CLK] = &pmic_arb1_h_clk.clkr,
 205         [PMIC_SSBI2_CLK] = &pmic_ssbi2_clk.clkr,
 206         [RPM_MSG_RAM_H_CLK] = &rpm_msg_ram_h_clk.clkr,
 207 +       [PLL9] = &hfpll0.clkr,
 208 +       [PLL10] = &hfpll1.clkr,
 209 +       [PLL12] = &hfpll_l2.clkr,
 210 +       [PLL16] = &hfpll2.clkr,
 211 +       [PLL17] = &hfpll3.clkr,
 212  };
 213
 214  static const struct qcom_reset_map gcc_apq8064_resets[] = {
 215 @@ -3477,6 +3644,11 @@ static int gcc_msm8960_probe(struct plat
 216         if (ret)
 217                 return ret;
 218
 219 +       if (match->data == &gcc_apq8064_desc) {
 220 +               hfpll1.d = &hfpll1_8064_data;
 221 +               hfpll_l2.d = &hfpll_l2_8064_data;
 222 +       }
 223 +
 224         tsens = platform_device_register_data(&pdev->dev, "qcom-tsens", -1,
 225                                               NULL, 0);
 226         if (IS_ERR(tsens))
 227 --- a/include/dt-bindings/clock/qcom,gcc-msm8960.h
 228 +++ b/include/dt-bindings/clock/qcom,gcc-msm8960.h
 229 @@ -319,5 +319,7 @@
 230  #define CE3_SRC                                        303
 231  #define CE3_CORE_CLK                           304
 232  #define CE3_H_CLK                              305
 233 +#define PLL16                                  306
 234 +#define PLL17                                  307
 235
 236  #endif