target/linux/ipq806x/patches-4.19/0034-0003-clk-qcom-Add-HFPLL-driver.patch

   1 From cb546b797a0da4dbb1a0c76a2a357921887b6189 Mon Sep 17 00:00:00 2001
   2 From: Stephen Boyd <sboyd@codeaurora.org>
   3 Date: Tue, 14 Aug 2018 17:42:22 +0530
   4 Subject: [PATCH 03/12] clk: qcom: Add HFPLL driver
   5
   6 On some devices (MSM8974 for example), the HFPLLs are
   7 instantiated within the Krait processor subsystem as separate
   8 register regions. Add a driver for these PLLs so that we can
   9 provide HFPLL clocks for use by the system.
  10
  11 Cc: <devicetree@vger.kernel.org>
  12 Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
  13 Signed-off-by: Sricharan R <sricharan@codeaurora.org>
  14 Tested-by: Craig Tatlor <ctatlor97@gmail.com>
  15 Signed-off-by: Stephen Boyd <sboyd@kernel.org>
  16 ---
  17  drivers/clk/qcom/Kconfig  |  8 ++++
  18  drivers/clk/qcom/Makefile |  1 +
  19  drivers/clk/qcom/hfpll.c  | 96 +++++++++++++++++++++++++++++++++++++++
  20  3 files changed, 105 insertions(+)
  21  create mode 100644 drivers/clk/qcom/hfpll.c
  22
  23 --- a/drivers/clk/qcom/Kconfig
  24 +++ b/drivers/clk/qcom/Kconfig
  25 @@ -272,3 +272,11 @@ config SPMI_PMIC_CLKDIV
  26           Technologies, Inc. SPMI PMIC. It configures the frequency of
  27           clkdiv outputs of the PMIC. These clocks are typically wired
  28           through alternate functions on GPIO pins.
  29 +
  30 +config QCOM_HFPLL
  31 +       tristate "High-Frequency PLL (HFPLL) Clock Controller"
  32 +       depends on COMMON_CLK_QCOM
  33 +       help
  34 +         Support for the high-frequency PLLs present on Qualcomm devices.
  35 +         Say Y if you want to support CPU frequency scaling on devices
  36 +         such as MSM8974, APQ8084, etc.
  37 --- a/drivers/clk/qcom/Makefile
  38 +++ b/drivers/clk/qcom/Makefile
  39 @@ -44,3 +44,4 @@ obj-$(CONFIG_SDM_DISPCC_845) += dispcc-s
  40  obj-$(CONFIG_SDM_GCC_845) += gcc-sdm845.o
  41  obj-$(CONFIG_SDM_VIDEOCC_845) += videocc-sdm845.o
  42  obj-$(CONFIG_SPMI_PMIC_CLKDIV) += clk-spmi-pmic-div.o
  43 +obj-$(CONFIG_QCOM_HFPLL) += hfpll.o
  44 --- /dev/null
  45 +++ b/drivers/clk/qcom/hfpll.c
  46 @@ -0,0 +1,96 @@
  47 +// SPDX-License-Identifier: GPL-2.0
  48 +// Copyright (c) 2018, The Linux Foundation. All rights reserved.
  49 +
  50 +#include <linux/kernel.h>
  51 +#include <linux/init.h>
  52 +#include <linux/module.h>
  53 +#include <linux/platform_device.h>
  54 +#include <linux/of.h>
  55 +#include <linux/clk.h>
  56 +#include <linux/clk-provider.h>
  57 +#include <linux/regmap.h>
  58 +
  59 +#include "clk-regmap.h"
  60 +#include "clk-hfpll.h"
  61 +
  62 +static const struct hfpll_data hdata = {
  63 +       .mode_reg = 0x00,
  64 +       .l_reg = 0x04,
  65 +       .m_reg = 0x08,
  66 +       .n_reg = 0x0c,
  67 +       .user_reg = 0x10,
  68 +       .config_reg = 0x14,
  69 +       .config_val = 0x430405d,
  70 +       .status_reg = 0x1c,
  71 +       .lock_bit = 16,
  72 +
  73 +       .user_val = 0x8,
  74 +       .user_vco_mask = 0x100000,
  75 +       .low_vco_max_rate = 1248000000,
  76 +       .min_rate = 537600000UL,
  77 +       .max_rate = 2900000000UL,
  78 +};
  79 +
  80 +static const struct of_device_id qcom_hfpll_match_table[] = {
  81 +       { .compatible = "qcom,hfpll" },
  82 +       { }
  83 +};
  84 +MODULE_DEVICE_TABLE(of, qcom_hfpll_match_table);
  85 +
  86 +static const struct regmap_config hfpll_regmap_config = {
  87 +       .reg_bits       = 32,
  88 +       .reg_stride     = 4,
  89 +       .val_bits       = 32,
  90 +       .max_register   = 0x30,
  91 +       .fast_io        = true,
  92 +};
  93 +
  94 +static int qcom_hfpll_probe(struct platform_device *pdev)
  95 +{
  96 +       struct resource *res;
  97 +       struct device *dev = &pdev->dev;
  98 +       void __iomem *base;
  99 +       struct regmap *regmap;
 100 +       struct clk_hfpll *h;
 101 +       struct clk_init_data init = {
 102 +               .parent_names = (const char *[]){ "xo" },
 103 +               .num_parents = 1,
 104 +               .ops = &clk_ops_hfpll,
 105 +       };
 106 +
 107 +       h = devm_kzalloc(dev, sizeof(*h), GFP_KERNEL);
 108 +       if (!h)
 109 +               return -ENOMEM;
 110 +
 111 +       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 112 +       base = devm_ioremap_resource(dev, res);
 113 +       if (IS_ERR(base))
 114 +               return PTR_ERR(base);
 115 +
 116 +       regmap = devm_regmap_init_mmio(&pdev->dev, base, &hfpll_regmap_config);
 117 +       if (IS_ERR(regmap))
 118 +               return PTR_ERR(regmap);
 119 +
 120 +       if (of_property_read_string_index(dev->of_node, "clock-output-names",
 121 +                                         0, &init.name))
 122 +               return -ENODEV;
 123 +
 124 +       h->d = &hdata;
 125 +       h->clkr.hw.init = &init;
 126 +       spin_lock_init(&h->lock);
 127 +
 128 +       return devm_clk_register_regmap(&pdev->dev, &h->clkr);
 129 +}
 130 +
 131 +static struct platform_driver qcom_hfpll_driver = {
 132 +       .probe          = qcom_hfpll_probe,
 133 +       .driver         = {
 134 +               .name   = "qcom-hfpll",
 135 +               .of_match_table = qcom_hfpll_match_table,
 136 +       },
 137 +};
 138 +module_platform_driver(qcom_hfpll_driver);
 139 +
 140 +MODULE_DESCRIPTION("QCOM HFPLL Clock Driver");
 141 +MODULE_LICENSE("GPL v2");
 142 +MODULE_ALIAS("platform:qcom-hfpll");