target/linux/ipq806x/patches-4.14/850-soc-add-qualcomm-syscon.patch

   1 From: Christian Lamparter <chunkeey@googlemail.com>
   2 Subject: SoC: add qualcomm syscon
   3 --- a/drivers/soc/qcom/Makefile
   4 +++ b/drivers/soc/qcom/Makefile
   5 @@ -9,3 +9,4 @@ obj-$(CONFIG_QCOM_SMEM_STATE) += smem_st
   6  obj-$(CONFIG_QCOM_SMP2P)       += smp2p.o
   7  obj-$(CONFIG_QCOM_SMSM)        += smsm.o
   8  obj-$(CONFIG_QCOM_WCNSS_CTRL) += wcnss_ctrl.o
   9 +obj-$(CONFIG_QCOM_TCSR)         += qcom_tcsr.o
  10 --- a/drivers/soc/qcom/Kconfig
  11 +++ b/drivers/soc/qcom/Kconfig
  12 @@ -78,6 +78,13 @@ config QCOM_SMSM
  13           Say yes here to support the Qualcomm Shared Memory State Machine.
  14           The state machine is represented by bits in shared memory.
  15
  16 +config QCOM_TCSR
  17 +       tristate "QCOM Top Control and Status Registers"
  18 +       depends on ARCH_QCOM
  19 +       help
  20 +         Say y here to enable TCSR support.  The TCSR provides control
  21 +         functions for various peripherals.
  22 +
  23  config QCOM_WCNSS_CTRL
  24         tristate "Qualcomm WCNSS control driver"
  25         depends on ARCH_QCOM
  26 --- /dev/null
  27 +++ b/drivers/soc/qcom/qcom_tcsr.c
  28 @@ -0,0 +1,98 @@
  29 +/*
  30 + * Copyright (c) 2014, The Linux foundation. All rights reserved.
  31 + *
  32 + * This program is free software; you can redistribute it and/or modify
  33 + * it under the terms of the GNU General Public License rev 2 and
  34 + * only rev 2 as published by the free Software foundation.
  35 + *
  36 + * This program is distributed in the hope that it will be useful,
  37 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  38 + * MERCHANTABILITY or fITNESS fOR A PARTICULAR PURPOSE.  See the
  39 + * GNU General Public License for more details.
  40 + */
  41 +
  42 +#include <linux/clk.h>
  43 +#include <linux/err.h>
  44 +#include <linux/io.h>
  45 +#include <linux/module.h>
  46 +#include <linux/of.h>
  47 +#include <linux/of_platform.h>
  48 +#include <linux/platform_device.h>
  49 +
  50 +#define TCSR_USB_PORT_SEL      0xb0
  51 +#define TCSR_USB_HSPHY_CONFIG  0xC
  52 +
  53 +#define TCSR_ESS_INTERFACE_SEL_OFFSET   0x0
  54 +#define TCSR_ESS_INTERFACE_SEL_MASK     0xf
  55 +
  56 +#define TCSR_WIFI0_GLB_CFG_OFFSET      0x0
  57 +#define TCSR_WIFI1_GLB_CFG_OFFSET      0x4
  58 +#define TCSR_PNOC_SNOC_MEMTYPE_M0_M2   0x4
  59 +
  60 +static int tcsr_probe(struct platform_device *pdev)
  61 +{
  62 +       struct resource *res;
  63 +       const struct device_node *node = pdev->dev.of_node;
  64 +       void __iomem *base;
  65 +       u32 val;
  66 +
  67 +       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  68 +       base = devm_ioremap_resource(&pdev->dev, res);
  69 +       if (IS_ERR(base))
  70 +               return PTR_ERR(base);
  71 +
  72 +       if (!of_property_read_u32(node, "qcom,usb-ctrl-select", &val)) {
  73 +               dev_err(&pdev->dev, "setting usb port select = %d\n", val);
  74 +               writel(val, base + TCSR_USB_PORT_SEL);
  75 +       }
  76 +
  77 +       if (!of_property_read_u32(node, "qcom,usb-hsphy-mode-select", &val)) {
  78 +               dev_info(&pdev->dev, "setting usb hs phy mode select = %x\n", val);
  79 +               writel(val, base + TCSR_USB_HSPHY_CONFIG);
  80 +       }
  81 +
  82 +       if (!of_property_read_u32(node, "qcom,ess-interface-select", &val)) {
  83 +               u32 tmp = 0;
  84 +               dev_info(&pdev->dev, "setting ess interface select = %x\n", val);
  85 +               tmp = readl(base + TCSR_ESS_INTERFACE_SEL_OFFSET);
  86 +               tmp = tmp & (~TCSR_ESS_INTERFACE_SEL_MASK);
  87 +               tmp = tmp | (val&TCSR_ESS_INTERFACE_SEL_MASK);
  88 +               writel(tmp, base + TCSR_ESS_INTERFACE_SEL_OFFSET);
  89 +        }
  90 +
  91 +       if (!of_property_read_u32(node, "qcom,wifi_glb_cfg", &val)) {
  92 +               dev_info(&pdev->dev, "setting wifi_glb_cfg = %x\n", val);
  93 +               writel(val, base + TCSR_WIFI0_GLB_CFG_OFFSET);
  94 +               writel(val, base + TCSR_WIFI1_GLB_CFG_OFFSET);
  95 +       }
  96 +
  97 +       if (!of_property_read_u32(node, "qcom,wifi_noc_memtype_m0_m2", &val)) {
  98 +               dev_info(&pdev->dev,
  99 +                       "setting wifi_noc_memtype_m0_m2 = %x\n", val);
 100 +               writel(val, base + TCSR_PNOC_SNOC_MEMTYPE_M0_M2);
 101 +       }
 102 +
 103 +       return 0;
 104 +}
 105 +
 106 +static const struct of_device_id tcsr_dt_match[] = {
 107 +       { .compatible = "qcom,tcsr", },
 108 +       { },
 109 +};
 110 +
 111 +MODULE_DEVICE_TABLE(of, tcsr_dt_match);
 112 +
 113 +static struct platform_driver tcsr_driver = {
 114 +       .driver = {
 115 +               .name           = "tcsr",
 116 +               .owner          = THIS_MODULE,
 117 +               .of_match_table = tcsr_dt_match,
 118 +       },
 119 +       .probe = tcsr_probe,
 120 +};
 121 +
 122 +module_platform_driver(tcsr_driver);
 123 +
 124 +MODULE_AUTHOR("Andy Gross <agross@codeaurora.org>");
 125 +MODULE_DESCRIPTION("QCOM TCSR driver");
 126 +MODULE_LICENSE("GPL v2");
 127 --- /dev/null
 128 +++ b/include/dt-bindings/soc/qcom,tcsr.h
 129 @@ -0,0 +1,48 @@
 130 +/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
 131 + *
 132 + * This program is free software; you can redistribute it and/or modify
 133 + * it under the terms of the GNU General Public License version 2 and
 134 + * only version 2 as published by the Free Software Foundation.
 135 + *
 136 + * This program is distributed in the hope that it will be useful,
 137 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
 138 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 139 + * GNU General Public License for more details.
 140 + */
 141 +#ifndef __DT_BINDINGS_QCOM_TCSR_H
 142 +#define __DT_BINDINGS_QCOM_TCSR_H
 143 +
 144 +#define TCSR_USB_SELECT_USB3_P0                0x1
 145 +#define TCSR_USB_SELECT_USB3_P1                0x2
 146 +#define TCSR_USB_SELECT_USB3_DUAL      0x3
 147 +
 148 +/* IPQ40xx HS PHY Mode Select */
 149 +#define TCSR_USB_HSPHY_HOST_MODE       0x00E700E7
 150 +#define TCSR_USB_HSPHY_DEVICE_MODE     0x00C700E7
 151 +
 152 +/* IPQ40xx ess interface mode select */
 153 +#define TCSR_ESS_PSGMII              0
 154 +#define TCSR_ESS_PSGMII_RGMII5       1
 155 +#define TCSR_ESS_PSGMII_RMII0        2
 156 +#define TCSR_ESS_PSGMII_RMII1        4
 157 +#define TCSR_ESS_PSGMII_RMII0_RMII1  6
 158 +#define TCSR_ESS_PSGMII_RGMII4       9
 159 +
 160 +/*
 161 + * IPQ40xx WiFi Global Config
 162 + * Bit 30:AXID_EN
 163 + * Enable AXI master bus Axid translating to confirm all txn submitted by order
 164 + * Bit 24: Use locally generated socslv_wxi_bvalid
 165 + * 1:  use locally generate socslv_wxi_bvalid for performance.
 166 + * 0:  use SNOC socslv_wxi_bvalid.
 167 + */
 168 +#define TCSR_WIFI_GLB_CFG              0x41000000
 169 +
 170 +/* IPQ40xx MEM_TYPE_SEL_M0_M2 Select Bit 26:24 - 2 NORMAL */
 171 +#define TCSR_WIFI_NOC_MEMTYPE_M0_M2    0x02222222
 172 +
 173 +/* TCSR A/B REG */
 174 +#define IPQ806X_TCSR_REG_A_ADM_CRCI_MUX_SEL     0
 175 +#define IPQ806X_TCSR_REG_B_ADM_CRCI_MUX_SEL     1
 176 +
 177 +#endif