target/linux/ipq806x/patches-4.14/0071-1-PCI-qcom-Fixed-IPQ806x-specific-clocks.patch

   1 From 86655aa14304ca88a8ce8847276147dbc1a83238 Mon Sep 17 00:00:00 2001
   2 From: Sham Muthayyan <smuthayy@codeaurora.org>
   3 Date: Tue, 19 Jul 2016 18:44:49 +0530
   4 Subject: PCI: qcom: Fixed IPQ806x specific clocks
   5
   6 Change-Id: I488e1bc707d6a22b37a338f41935e3922009ba5e
   7 Signed-off-by: Sham Muthayyan <smuthayy@codeaurora.org>
   8 ---
   9  drivers/pci/host/pcie-qcom.c | 38 +++++++++++++++++++++++++++++++++-----
  10  1 file changed, 33 insertions(+), 5 deletions(-)
  11
  12 --- a/drivers/pci/dwc/pcie-qcom.c
  13 +++ b/drivers/pci/dwc/pcie-qcom.c
  14 @@ -91,6 +91,8 @@ struct qcom_pcie_resources_2_1_0 {
  15         struct clk *iface_clk;
  16         struct clk *core_clk;
  17         struct clk *phy_clk;
  18 +       struct clk *aux_clk;
  19 +       struct clk *ref_clk;
  20         struct reset_control *pci_reset;
  21         struct reset_control *axi_reset;
  22         struct reset_control *ahb_reset;
  23 @@ -249,6 +251,14 @@ static int qcom_pcie_get_resources_2_1_0
  24         if (IS_ERR(res->phy_clk))
  25                 return PTR_ERR(res->phy_clk);
  26
  27 +       res->aux_clk = devm_clk_get(dev, "aux");
  28 +       if (IS_ERR(res->aux_clk))
  29 +               return PTR_ERR(res->aux_clk);
  30 +
  31 +       res->ref_clk = devm_clk_get(dev, "ref");
  32 +       if (IS_ERR(res->ref_clk))
  33 +               return PTR_ERR(res->ref_clk);
  34 +
  35         res->pci_reset = devm_reset_control_get_exclusive(dev, "pci");
  36         if (IS_ERR(res->pci_reset))
  37                 return PTR_ERR(res->pci_reset);
  38 @@ -281,6 +291,8 @@ static void qcom_pcie_deinit_2_1_0(struc
  39         clk_disable_unprepare(res->iface_clk);
  40         clk_disable_unprepare(res->core_clk);
  41         clk_disable_unprepare(res->phy_clk);
  42 +       clk_disable_unprepare(res->aux_clk);
  43 +       clk_disable_unprepare(res->ref_clk);
  44         regulator_disable(res->vdda);
  45         regulator_disable(res->vdda_phy);
  46         regulator_disable(res->vdda_refclk);
  47 @@ -324,16 +336,28 @@ static int qcom_pcie_init_2_1_0(struct q
  48                 goto err_assert_ahb;
  49         }
  50
  51 +       ret = clk_prepare_enable(res->core_clk);
  52 +       if (ret) {
  53 +               dev_err(dev, "cannot prepare/enable core clock\n");
  54 +               goto err_clk_core;
  55 +       }
  56 +
  57         ret = clk_prepare_enable(res->phy_clk);
  58         if (ret) {
  59                 dev_err(dev, "cannot prepare/enable phy clock\n");
  60                 goto err_clk_phy;
  61         }
  62
  63 -       ret = clk_prepare_enable(res->core_clk);
  64 +       ret = clk_prepare_enable(res->aux_clk);
  65         if (ret) {
  66 -               dev_err(dev, "cannot prepare/enable core clock\n");
  67 -               goto err_clk_core;
  68 +               dev_err(dev, "cannot prepare/enable aux clock\n");
  69 +               goto err_clk_aux;
  70 +       }
  71 +
  72 +       ret = clk_prepare_enable(res->ref_clk);
  73 +       if (ret) {
  74 +               dev_err(dev, "cannot prepare/enable ref clock\n");
  75 +               goto err_clk_ref;
  76         }
  77
  78         ret = reset_control_deassert(res->ahb_reset);
  79 @@ -389,10 +413,14 @@ static int qcom_pcie_init_2_1_0(struct q
  80         return 0;
  81
  82  err_deassert_ahb:
  83 -       clk_disable_unprepare(res->core_clk);
  84 -err_clk_core:
  85 +       clk_disable_unprepare(res->ref_clk);
  86 +err_clk_ref:
  87 +       clk_disable_unprepare(res->aux_clk);
  88 +err_clk_aux:
  89         clk_disable_unprepare(res->phy_clk);
  90  err_clk_phy:
  91 +       clk_disable_unprepare(res->core_clk);
  92 +err_clk_core:
  93         clk_disable_unprepare(res->iface_clk);
  94  err_assert_ahb:
  95         regulator_disable(res->vdda_phy);