target/linux/ipq806x/patches-3.18/160-clk-qcom-Add-EBI2-clocks-for-IPQ806x.patch

   1 From 4c385b25fab119144bffb255ad77712fe586ac10 Mon Sep 17 00:00:00 2001
   2 From: Archit Taneja <architt@codeaurora.org>
   3 Date: Thu, 2 Apr 2015 11:20:41 +0530
   4 Subject: [PATCH] clk: qcom: Add EBI2 clocks for IPQ806x
   5
   6 The NAND controller within EBI2 requires EBI2_CLK and
   7 EBI2_ALWAYS_ON_CLK clocks.  Create structs for these clocks so
   8 that they can be used by the NAND controller driver. Add an entry
   9 for EBI2_AON_CLK in the gcc-ipq806x DT binding document.
  10
  11 Signed-off-by: Archit Taneja <architt@codeaurora.org>
  12 Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
  13 ---
  14  drivers/clk/qcom/gcc-ipq806x.c               | 32 ++++++++++++++++++++++++++++
  15  include/dt-bindings/clock/qcom,gcc-ipq806x.h |  1 +
  16  2 files changed, 33 insertions(+)
  17
  18 --- a/drivers/clk/qcom/gcc-ipq806x.c
  19 +++ b/drivers/clk/qcom/gcc-ipq806x.c
  20 @@ -2239,6 +2239,36 @@ static struct clk_branch usb_fs1_h_clk =
  21         },
  22  };
  23
  24 +static struct clk_branch ebi2_clk = {
  25 +       .hwcg_reg = 0x3b00,
  26 +       .hwcg_bit = 6,
  27 +       .halt_reg = 0x2fcc,
  28 +       .halt_bit = 1,
  29 +       .clkr = {
  30 +               .enable_reg = 0x3b00,
  31 +               .enable_mask = BIT(4),
  32 +               .hw.init = &(struct clk_init_data){
  33 +                       .name = "ebi2_clk",
  34 +                       .ops = &clk_branch_ops,
  35 +                       .flags = CLK_IS_ROOT,
  36 +               },
  37 +       },
  38 +};
  39 +
  40 +static struct clk_branch ebi2_aon_clk = {
  41 +       .halt_reg = 0x2fcc,
  42 +       .halt_bit = 0,
  43 +       .clkr = {
  44 +               .enable_reg = 0x3b00,
  45 +               .enable_mask = BIT(8),
  46 +               .hw.init = &(struct clk_init_data){
  47 +                       .name = "ebi2_always_on_clk",
  48 +                       .ops = &clk_branch_ops,
  49 +                       .flags = CLK_IS_ROOT,
  50 +               },
  51 +       },
  52 +};
  53 +
  54  static struct clk_regmap *gcc_ipq806x_clks[] = {
  55         [PLL0] = &pll0.clkr,
  56         [PLL0_VOTE] = &pll0_vote,
  57 @@ -2341,6 +2371,8 @@ static struct clk_regmap *gcc_ipq806x_cl
  58         [USB_FS1_XCVR_SRC] = &usb_fs1_xcvr_clk_src.clkr,
  59         [USB_FS1_XCVR_CLK] = &usb_fs1_xcvr_clk.clkr,
  60         [USB_FS1_SYSTEM_CLK] = &usb_fs1_sys_clk.clkr,
  61 +       [EBI2_CLK] = &ebi2_clk.clkr,
  62 +       [EBI2_AON_CLK] = &ebi2_aon_clk.clkr,
  63         [PLL9] = &hfpll0.clkr,
  64         [PLL10] = &hfpll1.clkr,
  65         [PLL12] = &hfpll_l2.clkr,
  66 --- a/include/dt-bindings/clock/qcom,gcc-ipq806x.h
  67 +++ b/include/dt-bindings/clock/qcom,gcc-ipq806x.h
  68 @@ -289,5 +289,6 @@
  69  #define UBI32_CORE2_CLK_SRC                    278
  70  #define UBI32_CORE1_CLK                                279
  71  #define UBI32_CORE2_CLK                                280
  72 +#define EBI2_AON_CLK                           281
  73
  74  #endif