target/linux/ipq806x/patches/0105-clk-qcom-Support-display-RCG-clocks.patch

   1 From 3123079878e29eb8c541111e30de4d1bb42ac6f9 Mon Sep 17 00:00:00 2001
   2 From: Stephen Boyd <sboyd@codeaurora.org>
   3 Date: Fri, 16 May 2014 16:07:11 -0700
   4 Subject: [PATCH 105/182] clk: qcom: Support display RCG clocks
   5
   6 Add support for the DSI/EDP/HDMI RCG clocks. With the proper
   7 display driver in place this should allow us to support display
   8 clocks on msm8974 based devices.
   9
  10 Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
  11 Signed-off-by: Mike Turquette <mturquette@linaro.org>
  12 ---
  13  drivers/clk/qcom/clk-rcg.h  |    3 +
  14  drivers/clk/qcom/clk-rcg2.c |  299 ++++++++++++++++++++++++++++++++++++++++---
  15  2 files changed, 287 insertions(+), 15 deletions(-)
  16
  17 --- a/drivers/clk/qcom/clk-rcg.h
  18 +++ b/drivers/clk/qcom/clk-rcg.h
  19 @@ -155,5 +155,8 @@ struct clk_rcg2 {
  20  #define to_clk_rcg2(_hw) container_of(to_clk_regmap(_hw), struct clk_rcg2, clkr)
  21
  22  extern const struct clk_ops clk_rcg2_ops;
  23 +extern const struct clk_ops clk_edp_pixel_ops;
  24 +extern const struct clk_ops clk_byte_ops;
  25 +extern const struct clk_ops clk_pixel_ops;
  26
  27  #endif
  28 --- a/drivers/clk/qcom/clk-rcg2.c
  29 +++ b/drivers/clk/qcom/clk-rcg2.c
  30 @@ -19,6 +19,7 @@
  31  #include <linux/clk-provider.h>
  32  #include <linux/delay.h>
  33  #include <linux/regmap.h>
  34 +#include <linux/math64.h>
  35
  36  #include <asm/div64.h>
  37
  38 @@ -225,31 +226,25 @@ static long clk_rcg2_determine_rate(stru
  39         return _freq_tbl_determine_rate(hw, rcg->freq_tbl, rate, p_rate, p);
  40  }
  41
  42 -static int __clk_rcg2_set_rate(struct clk_hw *hw, unsigned long rate)
  43 +static int clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f)
  44  {
  45 -       struct clk_rcg2 *rcg = to_clk_rcg2(hw);
  46 -       const struct freq_tbl *f;
  47         u32 cfg, mask;
  48         int ret;
  49
  50 -       f = find_freq(rcg->freq_tbl, rate);
  51 -       if (!f)
  52 -               return -EINVAL;
  53 -
  54         if (rcg->mnd_width && f->n) {
  55                 mask = BIT(rcg->mnd_width) - 1;
  56 -               ret = regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + M_REG,
  57 -                                        mask, f->m);
  58 +               ret = regmap_update_bits(rcg->clkr.regmap,
  59 +                               rcg->cmd_rcgr + M_REG, mask, f->m);
  60                 if (ret)
  61                         return ret;
  62
  63 -               ret = regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + N_REG,
  64 -                                        mask, ~(f->n - f->m));
  65 +               ret = regmap_update_bits(rcg->clkr.regmap,
  66 +                               rcg->cmd_rcgr + N_REG, mask, ~(f->n - f->m));
  67                 if (ret)
  68                         return ret;
  69
  70 -               ret = regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + D_REG,
  71 -                                        mask, ~f->n);
  72 +               ret = regmap_update_bits(rcg->clkr.regmap,
  73 +                               rcg->cmd_rcgr + D_REG, mask, ~f->n);
  74                 if (ret)
  75                         return ret;
  76         }
  77 @@ -260,14 +255,26 @@ static int __clk_rcg2_set_rate(struct cl
  78         cfg |= rcg->parent_map[f->src] << CFG_SRC_SEL_SHIFT;
  79         if (rcg->mnd_width && f->n)
  80                 cfg |= CFG_MODE_DUAL_EDGE;
  81 -       ret = regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, mask,
  82 -                       cfg);
  83 +       ret = regmap_update_bits(rcg->clkr.regmap,
  84 +                       rcg->cmd_rcgr + CFG_REG, mask, cfg);
  85         if (ret)
  86                 return ret;
  87
  88         return update_config(rcg);
  89  }
  90
  91 +static int __clk_rcg2_set_rate(struct clk_hw *hw, unsigned long rate)
  92 +{
  93 +       struct clk_rcg2 *rcg = to_clk_rcg2(hw);
  94 +       const struct freq_tbl *f;
  95 +
  96 +       f = find_freq(rcg->freq_tbl, rate);
  97 +       if (!f)
  98 +               return -EINVAL;
  99 +
 100 +       return clk_rcg2_configure(rcg, f);
 101 +}
 102 +
 103  static int clk_rcg2_set_rate(struct clk_hw *hw, unsigned long rate,
 104                             unsigned long parent_rate)
 105  {
 106 @@ -290,3 +297,265 @@ const struct clk_ops clk_rcg2_ops = {
 107         .set_rate_and_parent = clk_rcg2_set_rate_and_parent,
 108  };
 109  EXPORT_SYMBOL_GPL(clk_rcg2_ops);
 110 +
 111 +struct frac_entry {
 112 +       int num;
 113 +       int den;
 114 +};
 115 +
 116 +static const struct frac_entry frac_table_675m[] = {   /* link rate of 270M */
 117 +       { 52, 295 },    /* 119 M */
 118 +       { 11, 57 },     /* 130.25 M */
 119 +       { 63, 307 },    /* 138.50 M */
 120 +       { 11, 50 },     /* 148.50 M */
 121 +       { 47, 206 },    /* 154 M */
 122 +       { 31, 100 },    /* 205.25 M */
 123 +       { 107, 269 },   /* 268.50 M */
 124 +       { },
 125 +};
 126 +
 127 +static struct frac_entry frac_table_810m[] = { /* Link rate of 162M */
 128 +       { 31, 211 },    /* 119 M */
 129 +       { 32, 199 },    /* 130.25 M */
 130 +       { 63, 307 },    /* 138.50 M */
 131 +       { 11, 60 },     /* 148.50 M */
 132 +       { 50, 263 },    /* 154 M */
 133 +       { 31, 120 },    /* 205.25 M */
 134 +       { 119, 359 },   /* 268.50 M */
 135 +       { },
 136 +};
 137 +
 138 +static int clk_edp_pixel_set_rate(struct clk_hw *hw, unsigned long rate,
 139 +                             unsigned long parent_rate)
 140 +{
 141 +       struct clk_rcg2 *rcg = to_clk_rcg2(hw);
 142 +       struct freq_tbl f = *rcg->freq_tbl;
 143 +       const struct frac_entry *frac;
 144 +       int delta = 100000;
 145 +       s64 src_rate = parent_rate;
 146 +       s64 request;
 147 +       u32 mask = BIT(rcg->hid_width) - 1;
 148 +       u32 hid_div;
 149 +
 150 +       if (src_rate == 810000000)
 151 +               frac = frac_table_810m;
 152 +       else
 153 +               frac = frac_table_675m;
 154 +
 155 +       for (; frac->num; frac++) {
 156 +               request = rate;
 157 +               request *= frac->den;
 158 +               request = div_s64(request, frac->num);
 159 +               if ((src_rate < (request - delta)) ||
 160 +                   (src_rate > (request + delta)))
 161 +                       continue;
 162 +
 163 +               regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG,
 164 +                               &hid_div);
 165 +               f.pre_div = hid_div;
 166 +               f.pre_div >>= CFG_SRC_DIV_SHIFT;
 167 +               f.pre_div &= mask;
 168 +               f.m = frac->num;
 169 +               f.n = frac->den;
 170 +
 171 +               return clk_rcg2_configure(rcg, &f);
 172 +       }
 173 +
 174 +       return -EINVAL;
 175 +}
 176 +
 177 +static int clk_edp_pixel_set_rate_and_parent(struct clk_hw *hw,
 178 +               unsigned long rate, unsigned long parent_rate, u8 index)
 179 +{
 180 +       /* Parent index is set statically in frequency table */
 181 +       return clk_edp_pixel_set_rate(hw, rate, parent_rate);
 182 +}
 183 +
 184 +static long clk_edp_pixel_determine_rate(struct clk_hw *hw, unsigned long rate,
 185 +                                unsigned long *p_rate, struct clk **p)
 186 +{
 187 +       struct clk_rcg2 *rcg = to_clk_rcg2(hw);
 188 +       const struct freq_tbl *f = rcg->freq_tbl;
 189 +       const struct frac_entry *frac;
 190 +       int delta = 100000;
 191 +       s64 src_rate = *p_rate;
 192 +       s64 request;
 193 +       u32 mask = BIT(rcg->hid_width) - 1;
 194 +       u32 hid_div;
 195 +
 196 +       /* Force the correct parent */
 197 +       *p = clk_get_parent_by_index(hw->clk, f->src);
 198 +
 199 +       if (src_rate == 810000000)
 200 +               frac = frac_table_810m;
 201 +       else
 202 +               frac = frac_table_675m;
 203 +
 204 +       for (; frac->num; frac++) {
 205 +               request = rate;
 206 +               request *= frac->den;
 207 +               request = div_s64(request, frac->num);
 208 +               if ((src_rate < (request - delta)) ||
 209 +                   (src_rate > (request + delta)))
 210 +                       continue;
 211 +
 212 +               regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG,
 213 +                               &hid_div);
 214 +               hid_div >>= CFG_SRC_DIV_SHIFT;
 215 +               hid_div &= mask;
 216 +
 217 +               return calc_rate(src_rate, frac->num, frac->den, !!frac->den,
 218 +                                hid_div);
 219 +       }
 220 +
 221 +       return -EINVAL;
 222 +}
 223 +
 224 +const struct clk_ops clk_edp_pixel_ops = {
 225 +       .is_enabled = clk_rcg2_is_enabled,
 226 +       .get_parent = clk_rcg2_get_parent,
 227 +       .set_parent = clk_rcg2_set_parent,
 228 +       .recalc_rate = clk_rcg2_recalc_rate,
 229 +       .set_rate = clk_edp_pixel_set_rate,
 230 +       .set_rate_and_parent = clk_edp_pixel_set_rate_and_parent,
 231 +       .determine_rate = clk_edp_pixel_determine_rate,
 232 +};
 233 +EXPORT_SYMBOL_GPL(clk_edp_pixel_ops);
 234 +
 235 +static long clk_byte_determine_rate(struct clk_hw *hw, unsigned long rate,
 236 +                        unsigned long *p_rate, struct clk **p)
 237 +{
 238 +       struct clk_rcg2 *rcg = to_clk_rcg2(hw);
 239 +       const struct freq_tbl *f = rcg->freq_tbl;
 240 +       unsigned long parent_rate, div;
 241 +       u32 mask = BIT(rcg->hid_width) - 1;
 242 +
 243 +       if (rate == 0)
 244 +               return -EINVAL;
 245 +
 246 +       *p = clk_get_parent_by_index(hw->clk, f->src);
 247 +       *p_rate = parent_rate = __clk_round_rate(*p, rate);
 248 +
 249 +       div = DIV_ROUND_UP((2 * parent_rate), rate) - 1;
 250 +       div = min_t(u32, div, mask);
 251 +
 252 +       return calc_rate(parent_rate, 0, 0, 0, div);
 253 +}
 254 +
 255 +static int clk_byte_set_rate(struct clk_hw *hw, unsigned long rate,
 256 +                        unsigned long parent_rate)
 257 +{
 258 +       struct clk_rcg2 *rcg = to_clk_rcg2(hw);
 259 +       struct freq_tbl f = *rcg->freq_tbl;
 260 +       unsigned long div;
 261 +       u32 mask = BIT(rcg->hid_width) - 1;
 262 +
 263 +       div = DIV_ROUND_UP((2 * parent_rate), rate) - 1;
 264 +       div = min_t(u32, div, mask);
 265 +
 266 +       f.pre_div = div;
 267 +
 268 +       return clk_rcg2_configure(rcg, &f);
 269 +}
 270 +
 271 +static int clk_byte_set_rate_and_parent(struct clk_hw *hw,
 272 +               unsigned long rate, unsigned long parent_rate, u8 index)
 273 +{
 274 +       /* Parent index is set statically in frequency table */
 275 +       return clk_byte_set_rate(hw, rate, parent_rate);
 276 +}
 277 +
 278 +const struct clk_ops clk_byte_ops = {
 279 +       .is_enabled = clk_rcg2_is_enabled,
 280 +       .get_parent = clk_rcg2_get_parent,
 281 +       .set_parent = clk_rcg2_set_parent,
 282 +       .recalc_rate = clk_rcg2_recalc_rate,
 283 +       .set_rate = clk_byte_set_rate,
 284 +       .set_rate_and_parent = clk_byte_set_rate_and_parent,
 285 +       .determine_rate = clk_byte_determine_rate,
 286 +};
 287 +EXPORT_SYMBOL_GPL(clk_byte_ops);
 288 +
 289 +static const struct frac_entry frac_table_pixel[] = {
 290 +       { 3, 8 },
 291 +       { 2, 9 },
 292 +       { 4, 9 },
 293 +       { 1, 1 },
 294 +       { }
 295 +};
 296 +
 297 +static long clk_pixel_determine_rate(struct clk_hw *hw, unsigned long rate,
 298 +                                unsigned long *p_rate, struct clk **p)
 299 +{
 300 +       struct clk_rcg2 *rcg = to_clk_rcg2(hw);
 301 +       unsigned long request, src_rate;
 302 +       int delta = 100000;
 303 +       const struct freq_tbl *f = rcg->freq_tbl;
 304 +       const struct frac_entry *frac = frac_table_pixel;
 305 +       struct clk *parent = *p = clk_get_parent_by_index(hw->clk, f->src);
 306 +
 307 +       for (; frac->num; frac++) {
 308 +               request = (rate * frac->den) / frac->num;
 309 +
 310 +               src_rate = __clk_round_rate(parent, request);
 311 +               if ((src_rate < (request - delta)) ||
 312 +                       (src_rate > (request + delta)))
 313 +                       continue;
 314 +
 315 +               *p_rate = src_rate;
 316 +               return (src_rate * frac->num) / frac->den;
 317 +       }
 318 +
 319 +       return -EINVAL;
 320 +}
 321 +
 322 +static int clk_pixel_set_rate(struct clk_hw *hw, unsigned long rate,
 323 +               unsigned long parent_rate)
 324 +{
 325 +       struct clk_rcg2 *rcg = to_clk_rcg2(hw);
 326 +       struct freq_tbl f = *rcg->freq_tbl;
 327 +       const struct frac_entry *frac = frac_table_pixel;
 328 +       unsigned long request, src_rate;
 329 +       int delta = 100000;
 330 +       u32 mask = BIT(rcg->hid_width) - 1;
 331 +       u32 hid_div;
 332 +       struct clk *parent = clk_get_parent_by_index(hw->clk, f.src);
 333 +
 334 +       for (; frac->num; frac++) {
 335 +               request = (rate * frac->den) / frac->num;
 336 +
 337 +               src_rate = __clk_round_rate(parent, request);
 338 +               if ((src_rate < (request - delta)) ||
 339 +                       (src_rate > (request + delta)))
 340 +                       continue;
 341 +
 342 +               regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG,
 343 +                               &hid_div);
 344 +               f.pre_div = hid_div;
 345 +               f.pre_div >>= CFG_SRC_DIV_SHIFT;
 346 +               f.pre_div &= mask;
 347 +               f.m = frac->num;
 348 +               f.n = frac->den;
 349 +
 350 +               return clk_rcg2_configure(rcg, &f);
 351 +       }
 352 +       return -EINVAL;
 353 +}
 354 +
 355 +static int clk_pixel_set_rate_and_parent(struct clk_hw *hw, unsigned long rate,
 356 +               unsigned long parent_rate, u8 index)
 357 +{
 358 +       /* Parent index is set statically in frequency table */
 359 +       return clk_pixel_set_rate(hw, rate, parent_rate);
 360 +}
 361 +
 362 +const struct clk_ops clk_pixel_ops = {
 363 +       .is_enabled = clk_rcg2_is_enabled,
 364 +       .get_parent = clk_rcg2_get_parent,
 365 +       .set_parent = clk_rcg2_set_parent,
 366 +       .recalc_rate = clk_rcg2_recalc_rate,
 367 +       .set_rate = clk_pixel_set_rate,
 368 +       .set_rate_and_parent = clk_pixel_set_rate_and_parent,
 369 +       .determine_rate = clk_pixel_determine_rate,
 370 +};
 371 +EXPORT_SYMBOL_GPL(clk_pixel_ops);