target/linux/ipq806x/patches/0093-ARM-dts-qcom-Update-msm8660-device-trees.patch

   1 From 355bf7c6410f5b6e37b5c2b28ebe59bb701c42d6 Mon Sep 17 00:00:00 2001
   2 From: Kumar Gala <galak@codeaurora.org>
   3 Date: Wed, 28 May 2014 12:12:40 -0500
   4 Subject: [PATCH 093/182] ARM: dts: qcom: Update msm8660 device trees
   5
   6 * Move SoC peripherals into an SoC container node
   7 * Move serial enabling into board file (qcom-msm8660-surf.dts)
   8 * Cleanup cpu node to match binding spec, enable-method and compatible
   9   should be per cpu, not part of the container
  10 * Add GSBI node and configuration of GSBI controller
  11
  12 Signed-off-by: Kumar Gala <galak@codeaurora.org>
  13 ---
  14  arch/arm/boot/dts/qcom-msm8660-surf.dts |   10 +++
  15  arch/arm/boot/dts/qcom-msm8660.dtsi     |  115 ++++++++++++++++++-------------
  16  2 files changed, 78 insertions(+), 47 deletions(-)
  17
  18 --- a/arch/arm/boot/dts/qcom-msm8660-surf.dts
  19 +++ b/arch/arm/boot/dts/qcom-msm8660-surf.dts
  20 @@ -3,4 +3,14 @@
  21  / {
  22         model = "Qualcomm MSM8660 SURF";
  23         compatible = "qcom,msm8660-surf", "qcom,msm8660";
  24 +
  25 +       soc {
  26 +               gsbi@19c00000 {
  27 +                       status = "ok";
  28 +                       qcom,mode = <GSBI_PROT_I2C_UART>;
  29 +                       serial@19c40000 {
  30 +                               status = "ok";
  31 +                       };
  32 +               };
  33 +       };
  34  };
  35 --- a/arch/arm/boot/dts/qcom-msm8660.dtsi
  36 +++ b/arch/arm/boot/dts/qcom-msm8660.dtsi
  37 @@ -3,6 +3,7 @@
  38  /include/ "skeleton.dtsi"
  39
  40  #include <dt-bindings/clock/qcom,gcc-msm8660.h>
  41 +#include <dt-bindings/soc/qcom,gsbi.h>
  42
  43  / {
  44         model = "Qualcomm MSM8660";
  45 @@ -12,16 +13,18 @@
  46         cpus {
  47                 #address-cells = <1>;
  48                 #size-cells = <0>;
  49 -               compatible = "qcom,scorpion";
  50 -               enable-method = "qcom,gcc-msm8660";
  51
  52                 cpu@0 {
  53 +                       compatible = "qcom,scorpion";
  54 +                       enable-method = "qcom,gcc-msm8660";
  55                         device_type = "cpu";
  56                         reg = <0>;
  57                         next-level-cache = <&L2>;
  58                 };
  59
  60                 cpu@1 {
  61 +                       compatible = "qcom,scorpion";
  62 +                       enable-method = "qcom,gcc-msm8660";
  63                         device_type = "cpu";
  64                         reg = <1>;
  65                         next-level-cache = <&L2>;
  66 @@ -33,55 +36,73 @@
  67                 };
  68         };
  69
  70 -       intc: interrupt-controller@2080000 {
  71 -               compatible = "qcom,msm-8660-qgic";
  72 -               interrupt-controller;
  73 -               #interrupt-cells = <3>;
  74 -               reg = < 0x02080000 0x1000 >,
  75 -                     < 0x02081000 0x1000 >;
  76 -       };
  77 +       soc: soc {
  78 +               #address-cells = <1>;
  79 +               #size-cells = <1>;
  80 +               ranges;
  81 +               compatible = "simple-bus";
  82 +
  83 +               intc: interrupt-controller@2080000 {
  84 +                       compatible = "qcom,msm-8660-qgic";
  85 +                       interrupt-controller;
  86 +                       #interrupt-cells = <3>;
  87 +                       reg = < 0x02080000 0x1000 >,
  88 +                             < 0x02081000 0x1000 >;
  89 +               };
  90
  91 -       timer@2000000 {
  92 -               compatible = "qcom,scss-timer", "qcom,msm-timer";
  93 -               interrupts = <1 0 0x301>,
  94 -                            <1 1 0x301>,
  95 -                            <1 2 0x301>;
  96 -               reg = <0x02000000 0x100>;
  97 -               clock-frequency = <27000000>,
  98 -                                 <32768>;
  99 -               cpu-offset = <0x40000>;
 100 -       };
 101 +               timer@2000000 {
 102 +                       compatible = "qcom,scss-timer", "qcom,msm-timer";
 103 +                       interrupts = <1 0 0x301>,
 104 +                                    <1 1 0x301>,
 105 +                                    <1 2 0x301>;
 106 +                       reg = <0x02000000 0x100>;
 107 +                       clock-frequency = <27000000>,
 108 +                                         <32768>;
 109 +                       cpu-offset = <0x40000>;
 110 +               };
 111
 112 -       msmgpio: gpio@800000 {
 113 -               compatible = "qcom,msm-gpio";
 114 -               reg = <0x00800000 0x4000>;
 115 -               gpio-controller;
 116 -               #gpio-cells = <2>;
 117 -               ngpio = <173>;
 118 -               interrupts = <0 16 0x4>;
 119 -               interrupt-controller;
 120 -               #interrupt-cells = <2>;
 121 -       };
 122 +               msmgpio: gpio@800000 {
 123 +                       compatible = "qcom,msm-gpio";
 124 +                       reg = <0x00800000 0x4000>;
 125 +                       gpio-controller;
 126 +                       #gpio-cells = <2>;
 127 +                       ngpio = <173>;
 128 +                       interrupts = <0 16 0x4>;
 129 +                       interrupt-controller;
 130 +                       #interrupt-cells = <2>;
 131 +               };
 132
 133 -       gcc: clock-controller@900000 {
 134 -               compatible = "qcom,gcc-msm8660";
 135 -               #clock-cells = <1>;
 136 -               #reset-cells = <1>;
 137 -               reg = <0x900000 0x4000>;
 138 -       };
 139 +               gcc: clock-controller@900000 {
 140 +                       compatible = "qcom,gcc-msm8660";
 141 +                       #clock-cells = <1>;
 142 +                       #reset-cells = <1>;
 143 +                       reg = <0x900000 0x4000>;
 144 +               };
 145
 146 -       serial@19c40000 {
 147 -               compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
 148 -               reg = <0x19c40000 0x1000>,
 149 -                     <0x19c00000 0x1000>;
 150 -               interrupts = <0 195 0x0>;
 151 -               clocks = <&gcc GSBI12_UART_CLK>, <&gcc GSBI12_H_CLK>;
 152 -               clock-names = "core", "iface";
 153 -       };
 154 +               gsbi12: gsbi@19c00000 {
 155 +                       compatible = "qcom,gsbi-v1.0.0";
 156 +                       reg = <0x19c00000 0x100>;
 157 +                       clocks = <&gcc GSBI12_H_CLK>;
 158 +                       clock-names = "iface";
 159 +                       #address-cells = <1>;
 160 +                       #size-cells = <1>;
 161 +                       ranges;
 162 +
 163 +                       serial@19c40000 {
 164 +                               compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
 165 +                               reg = <0x19c40000 0x1000>,
 166 +                                     <0x19c00000 0x1000>;
 167 +                               interrupts = <0 195 0x0>;
 168 +                               clocks = <&gcc GSBI12_UART_CLK>, <&gcc GSBI12_H_CLK>;
 169 +                               clock-names = "core", "iface";
 170 +                               status = "disabled";
 171 +                       };
 172 +               };
 173
 174 -       qcom,ssbi@500000 {
 175 -               compatible = "qcom,ssbi";
 176 -               reg = <0x500000 0x1000>;
 177 -               qcom,controller-type = "pmic-arbiter";
 178 +               qcom,ssbi@500000 {
 179 +                       compatible = "qcom,ssbi";
 180 +                       reg = <0x500000 0x1000>;
 181 +                       qcom,controller-type = "pmic-arbiter";
 182 +               };
 183         };
 184  };