target/linux/ipq806x/patches/0060-i2c-qup-New-bus-driver-for-the-Qualcomm-QUP-I2C-cont.patch

   1 From 226eff10dc11af5d6b1bc31e5cedc079aa564fb3 Mon Sep 17 00:00:00 2001
   2 From: Bjorn Andersson <bjorn.andersson@sonymobile.com>
   3 Date: Thu, 13 Mar 2014 19:07:43 -0700
   4 Subject: [PATCH 060/182] i2c: qup: New bus driver for the Qualcomm QUP I2C
   5  controller
   6
   7 This bus driver supports the QUP i2c hardware controller in the Qualcomm SOCs.
   8 The Qualcomm Universal Peripheral Engine (QUP) is a general purpose data path
   9 engine with input/output FIFOs and an embedded i2c mini-core. The driver
  10 supports FIFO mode (for low bandwidth applications) and block mode (interrupt
  11 generated for each block-size data transfer).
  12
  13 Signed-off-by: Ivan T. Ivanov <iivanov@mm-sol.com>
  14 Signed-off-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
  15 Reviewed-by: Andy Gross <agross@codeaurora.org>
  16 Tested-by: Philip Elcan <pelcan@codeaurora.org>
  17 [wsa: removed needless IS_ERR_VALUE]
  18 Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
  19 ---
  20  drivers/i2c/busses/Kconfig   |   10 +
  21  drivers/i2c/busses/Makefile  |    1 +
  22  drivers/i2c/busses/i2c-qup.c |  768 ++++++++++++++++++++++++++++++++++++++++++
  23  3 files changed, 779 insertions(+)
  24  create mode 100644 drivers/i2c/busses/i2c-qup.c
  25
  26 --- a/drivers/i2c/busses/Kconfig
  27 +++ b/drivers/i2c/busses/Kconfig
  28 @@ -649,6 +649,16 @@ config I2C_PXA_SLAVE
  29           is necessary for systems where the PXA may be a target on the
  30           I2C bus.
  31
  32 +config I2C_QUP
  33 +       tristate "Qualcomm QUP based I2C controller"
  34 +       depends on ARCH_QCOM
  35 +       help
  36 +         If you say yes to this option, support will be included for the
  37 +         built-in I2C interface on the Qualcomm SoCs.
  38 +
  39 +         This driver can also be built as a module.  If so, the module
  40 +         will be called i2c-qup.
  41 +
  42  config I2C_RIIC
  43         tristate "Renesas RIIC adapter"
  44         depends on ARCH_SHMOBILE || COMPILE_TEST
  45 --- a/drivers/i2c/busses/Makefile
  46 +++ b/drivers/i2c/busses/Makefile
  47 @@ -63,6 +63,7 @@ obj-$(CONFIG_I2C_PNX)         += i2c-pnx.o
  48  obj-$(CONFIG_I2C_PUV3)         += i2c-puv3.o
  49  obj-$(CONFIG_I2C_PXA)          += i2c-pxa.o
  50  obj-$(CONFIG_I2C_PXA_PCI)      += i2c-pxa-pci.o
  51 +obj-$(CONFIG_I2C_QUP)          += i2c-qup.o
  52  obj-$(CONFIG_I2C_RIIC)         += i2c-riic.o
  53  obj-$(CONFIG_I2C_S3C2410)      += i2c-s3c2410.o
  54  obj-$(CONFIG_I2C_S6000)                += i2c-s6000.o
  55 --- /dev/null
  56 +++ b/drivers/i2c/busses/i2c-qup.c
  57 @@ -0,0 +1,768 @@
  58 +/*
  59 + * Copyright (c) 2009-2013, The Linux Foundation. All rights reserved.
  60 + * Copyright (c) 2014, Sony Mobile Communications AB.
  61 + *
  62 + *
  63 + * This program is free software; you can redistribute it and/or modify
  64 + * it under the terms of the GNU General Public License version 2 and
  65 + * only version 2 as published by the Free Software Foundation.
  66 + *
  67 + * This program is distributed in the hope that it will be useful,
  68 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  69 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  70 + * GNU General Public License for more details.
  71 + *
  72 + */
  73 +
  74 +#include <linux/clk.h>
  75 +#include <linux/delay.h>
  76 +#include <linux/err.h>
  77 +#include <linux/i2c.h>
  78 +#include <linux/interrupt.h>
  79 +#include <linux/io.h>
  80 +#include <linux/module.h>
  81 +#include <linux/of.h>
  82 +#include <linux/platform_device.h>
  83 +#include <linux/pm_runtime.h>
  84 +
  85 +/* QUP Registers */
  86 +#define QUP_CONFIG             0x000
  87 +#define QUP_STATE              0x004
  88 +#define QUP_IO_MODE            0x008
  89 +#define QUP_SW_RESET           0x00c
  90 +#define QUP_OPERATIONAL                0x018
  91 +#define QUP_ERROR_FLAGS                0x01c
  92 +#define QUP_ERROR_FLAGS_EN     0x020
  93 +#define QUP_HW_VERSION         0x030
  94 +#define QUP_MX_OUTPUT_CNT      0x100
  95 +#define QUP_OUT_FIFO_BASE      0x110
  96 +#define QUP_MX_WRITE_CNT       0x150
  97 +#define QUP_MX_INPUT_CNT       0x200
  98 +#define QUP_MX_READ_CNT                0x208
  99 +#define QUP_IN_FIFO_BASE       0x218
 100 +#define QUP_I2C_CLK_CTL                0x400
 101 +#define QUP_I2C_STATUS         0x404
 102 +
 103 +/* QUP States and reset values */
 104 +#define QUP_RESET_STATE                0
 105 +#define QUP_RUN_STATE          1
 106 +#define QUP_PAUSE_STATE                3
 107 +#define QUP_STATE_MASK         3
 108 +
 109 +#define QUP_STATE_VALID                BIT(2)
 110 +#define QUP_I2C_MAST_GEN       BIT(4)
 111 +
 112 +#define QUP_OPERATIONAL_RESET  0x000ff0
 113 +#define QUP_I2C_STATUS_RESET   0xfffffc
 114 +
 115 +/* QUP OPERATIONAL FLAGS */
 116 +#define QUP_I2C_NACK_FLAG      BIT(3)
 117 +#define QUP_OUT_NOT_EMPTY      BIT(4)
 118 +#define QUP_IN_NOT_EMPTY       BIT(5)
 119 +#define QUP_OUT_FULL           BIT(6)
 120 +#define QUP_OUT_SVC_FLAG       BIT(8)
 121 +#define QUP_IN_SVC_FLAG                BIT(9)
 122 +#define QUP_MX_OUTPUT_DONE     BIT(10)
 123 +#define QUP_MX_INPUT_DONE      BIT(11)
 124 +
 125 +/* I2C mini core related values */
 126 +#define QUP_CLOCK_AUTO_GATE    BIT(13)
 127 +#define I2C_MINI_CORE          (2 << 8)
 128 +#define I2C_N_VAL              15
 129 +/* Most significant word offset in FIFO port */
 130 +#define QUP_MSW_SHIFT          (I2C_N_VAL + 1)
 131 +
 132 +/* Packing/Unpacking words in FIFOs, and IO modes */
 133 +#define QUP_OUTPUT_BLK_MODE    (1 << 10)
 134 +#define QUP_INPUT_BLK_MODE     (1 << 12)
 135 +#define QUP_UNPACK_EN          BIT(14)
 136 +#define QUP_PACK_EN            BIT(15)
 137 +
 138 +#define QUP_REPACK_EN          (QUP_UNPACK_EN | QUP_PACK_EN)
 139 +
 140 +#define QUP_OUTPUT_BLOCK_SIZE(x)(((x) >> 0) & 0x03)
 141 +#define QUP_OUTPUT_FIFO_SIZE(x)        (((x) >> 2) & 0x07)
 142 +#define QUP_INPUT_BLOCK_SIZE(x)        (((x) >> 5) & 0x03)
 143 +#define QUP_INPUT_FIFO_SIZE(x) (((x) >> 7) & 0x07)
 144 +
 145 +/* QUP tags */
 146 +#define QUP_TAG_START          (1 << 8)
 147 +#define QUP_TAG_DATA           (2 << 8)
 148 +#define QUP_TAG_STOP           (3 << 8)
 149 +#define QUP_TAG_REC            (4 << 8)
 150 +
 151 +/* Status, Error flags */
 152 +#define I2C_STATUS_WR_BUFFER_FULL      BIT(0)
 153 +#define I2C_STATUS_BUS_ACTIVE          BIT(8)
 154 +#define I2C_STATUS_ERROR_MASK          0x38000fc
 155 +#define QUP_STATUS_ERROR_FLAGS         0x7c
 156 +
 157 +#define QUP_READ_LIMIT                 256
 158 +
 159 +struct qup_i2c_dev {
 160 +       struct device           *dev;
 161 +       void __iomem            *base;
 162 +       int                     irq;
 163 +       struct clk              *clk;
 164 +       struct clk              *pclk;
 165 +       struct i2c_adapter      adap;
 166 +
 167 +       int                     clk_ctl;
 168 +       int                     out_fifo_sz;
 169 +       int                     in_fifo_sz;
 170 +       int                     out_blk_sz;
 171 +       int                     in_blk_sz;
 172 +
 173 +       unsigned long           one_byte_t;
 174 +
 175 +       struct i2c_msg          *msg;
 176 +       /* Current posion in user message buffer */
 177 +       int                     pos;
 178 +       /* I2C protocol errors */
 179 +       u32                     bus_err;
 180 +       /* QUP core errors */
 181 +       u32                     qup_err;
 182 +
 183 +       struct completion       xfer;
 184 +};
 185 +
 186 +static irqreturn_t qup_i2c_interrupt(int irq, void *dev)
 187 +{
 188 +       struct qup_i2c_dev *qup = dev;
 189 +       u32 bus_err;
 190 +       u32 qup_err;
 191 +       u32 opflags;
 192 +
 193 +       bus_err = readl(qup->base + QUP_I2C_STATUS);
 194 +       qup_err = readl(qup->base + QUP_ERROR_FLAGS);
 195 +       opflags = readl(qup->base + QUP_OPERATIONAL);
 196 +
 197 +       if (!qup->msg) {
 198 +               /* Clear Error interrupt */
 199 +               writel(QUP_RESET_STATE, qup->base + QUP_STATE);
 200 +               return IRQ_HANDLED;
 201 +       }
 202 +
 203 +       bus_err &= I2C_STATUS_ERROR_MASK;
 204 +       qup_err &= QUP_STATUS_ERROR_FLAGS;
 205 +
 206 +       if (qup_err) {
 207 +               /* Clear Error interrupt */
 208 +               writel(qup_err, qup->base + QUP_ERROR_FLAGS);
 209 +               goto done;
 210 +       }
 211 +
 212 +       if (bus_err) {
 213 +               /* Clear Error interrupt */
 214 +               writel(QUP_RESET_STATE, qup->base + QUP_STATE);
 215 +               goto done;
 216 +       }
 217 +
 218 +       if (opflags & QUP_IN_SVC_FLAG)
 219 +               writel(QUP_IN_SVC_FLAG, qup->base + QUP_OPERATIONAL);
 220 +
 221 +       if (opflags & QUP_OUT_SVC_FLAG)
 222 +               writel(QUP_OUT_SVC_FLAG, qup->base + QUP_OPERATIONAL);
 223 +
 224 +done:
 225 +       qup->qup_err = qup_err;
 226 +       qup->bus_err = bus_err;
 227 +       complete(&qup->xfer);
 228 +       return IRQ_HANDLED;
 229 +}
 230 +
 231 +static int qup_i2c_poll_state_mask(struct qup_i2c_dev *qup,
 232 +                                  u32 req_state, u32 req_mask)
 233 +{
 234 +       int retries = 1;
 235 +       u32 state;
 236 +
 237 +       /*
 238 +        * State transition takes 3 AHB clocks cycles + 3 I2C master clock
 239 +        * cycles. So retry once after a 1uS delay.
 240 +        */
 241 +       do {
 242 +               state = readl(qup->base + QUP_STATE);
 243 +
 244 +               if (state & QUP_STATE_VALID &&
 245 +                   (state & req_mask) == req_state)
 246 +                       return 0;
 247 +
 248 +               udelay(1);
 249 +       } while (retries--);
 250 +
 251 +       return -ETIMEDOUT;
 252 +}
 253 +
 254 +static int qup_i2c_poll_state(struct qup_i2c_dev *qup, u32 req_state)
 255 +{
 256 +       return qup_i2c_poll_state_mask(qup, req_state, QUP_STATE_MASK);
 257 +}
 258 +
 259 +static int qup_i2c_poll_state_valid(struct qup_i2c_dev *qup)
 260 +{
 261 +       return qup_i2c_poll_state_mask(qup, 0, 0);
 262 +}
 263 +
 264 +static int qup_i2c_poll_state_i2c_master(struct qup_i2c_dev *qup)
 265 +{
 266 +       return qup_i2c_poll_state_mask(qup, QUP_I2C_MAST_GEN, QUP_I2C_MAST_GEN);
 267 +}
 268 +
 269 +static int qup_i2c_change_state(struct qup_i2c_dev *qup, u32 state)
 270 +{
 271 +       if (qup_i2c_poll_state_valid(qup) != 0)
 272 +               return -EIO;
 273 +
 274 +       writel(state, qup->base + QUP_STATE);
 275 +
 276 +       if (qup_i2c_poll_state(qup, state) != 0)
 277 +               return -EIO;
 278 +       return 0;
 279 +}
 280 +
 281 +static int qup_i2c_wait_writeready(struct qup_i2c_dev *qup)
 282 +{
 283 +       unsigned long timeout;
 284 +       u32 opflags;
 285 +       u32 status;
 286 +
 287 +       timeout = jiffies + HZ;
 288 +
 289 +       for (;;) {
 290 +               opflags = readl(qup->base + QUP_OPERATIONAL);
 291 +               status = readl(qup->base + QUP_I2C_STATUS);
 292 +
 293 +               if (!(opflags & QUP_OUT_NOT_EMPTY) &&
 294 +                   !(status & I2C_STATUS_BUS_ACTIVE))
 295 +                       return 0;
 296 +
 297 +               if (time_after(jiffies, timeout))
 298 +                       return -ETIMEDOUT;
 299 +
 300 +               usleep_range(qup->one_byte_t, qup->one_byte_t * 2);
 301 +       }
 302 +}
 303 +
 304 +static void qup_i2c_set_write_mode(struct qup_i2c_dev *qup, struct i2c_msg *msg)
 305 +{
 306 +       /* Number of entries to shift out, including the start */
 307 +       int total = msg->len + 1;
 308 +
 309 +       if (total < qup->out_fifo_sz) {
 310 +               /* FIFO mode */
 311 +               writel(QUP_REPACK_EN, qup->base + QUP_IO_MODE);
 312 +               writel(total, qup->base + QUP_MX_WRITE_CNT);
 313 +       } else {
 314 +               /* BLOCK mode (transfer data on chunks) */
 315 +               writel(QUP_OUTPUT_BLK_MODE | QUP_REPACK_EN,
 316 +                      qup->base + QUP_IO_MODE);
 317 +               writel(total, qup->base + QUP_MX_OUTPUT_CNT);
 318 +       }
 319 +}
 320 +
 321 +static void qup_i2c_issue_write(struct qup_i2c_dev *qup, struct i2c_msg *msg)
 322 +{
 323 +       u32 addr = msg->addr << 1;
 324 +       u32 qup_tag;
 325 +       u32 opflags;
 326 +       int idx;
 327 +       u32 val;
 328 +
 329 +       if (qup->pos == 0) {
 330 +               val = QUP_TAG_START | addr;
 331 +               idx = 1;
 332 +       } else {
 333 +               val = 0;
 334 +               idx = 0;
 335 +       }
 336 +
 337 +       while (qup->pos < msg->len) {
 338 +               /* Check that there's space in the FIFO for our pair */
 339 +               opflags = readl(qup->base + QUP_OPERATIONAL);
 340 +               if (opflags & QUP_OUT_FULL)
 341 +                       break;
 342 +
 343 +               if (qup->pos == msg->len - 1)
 344 +                       qup_tag = QUP_TAG_STOP;
 345 +               else
 346 +                       qup_tag = QUP_TAG_DATA;
 347 +
 348 +               if (idx & 1)
 349 +                       val |= (qup_tag | msg->buf[qup->pos]) << QUP_MSW_SHIFT;
 350 +               else
 351 +                       val = qup_tag | msg->buf[qup->pos];
 352 +
 353 +               /* Write out the pair and the last odd value */
 354 +               if (idx & 1 || qup->pos == msg->len - 1)
 355 +                       writel(val, qup->base + QUP_OUT_FIFO_BASE);
 356 +
 357 +               qup->pos++;
 358 +               idx++;
 359 +       }
 360 +}
 361 +
 362 +static int qup_i2c_write_one(struct qup_i2c_dev *qup, struct i2c_msg *msg)
 363 +{
 364 +       unsigned long left;
 365 +       int ret;
 366 +
 367 +       qup->msg = msg;
 368 +       qup->pos = 0;
 369 +
 370 +       enable_irq(qup->irq);
 371 +
 372 +       qup_i2c_set_write_mode(qup, msg);
 373 +
 374 +       ret = qup_i2c_change_state(qup, QUP_RUN_STATE);
 375 +       if (ret)
 376 +               goto err;
 377 +
 378 +       writel(qup->clk_ctl, qup->base + QUP_I2C_CLK_CTL);
 379 +
 380 +       do {
 381 +               ret = qup_i2c_change_state(qup, QUP_PAUSE_STATE);
 382 +               if (ret)
 383 +                       goto err;
 384 +
 385 +               qup_i2c_issue_write(qup, msg);
 386 +
 387 +               ret = qup_i2c_change_state(qup, QUP_RUN_STATE);
 388 +               if (ret)
 389 +                       goto err;
 390 +
 391 +               left = wait_for_completion_timeout(&qup->xfer, HZ);
 392 +               if (!left) {
 393 +                       writel(1, qup->base + QUP_SW_RESET);
 394 +                       ret = -ETIMEDOUT;
 395 +                       goto err;
 396 +               }
 397 +
 398 +               if (qup->bus_err || qup->qup_err) {
 399 +                       if (qup->bus_err & QUP_I2C_NACK_FLAG)
 400 +                               dev_err(qup->dev, "NACK from %x\n", msg->addr);
 401 +                       ret = -EIO;
 402 +                       goto err;
 403 +               }
 404 +       } while (qup->pos < msg->len);
 405 +
 406 +       /* Wait for the outstanding data in the fifo to drain */
 407 +       ret = qup_i2c_wait_writeready(qup);
 408 +
 409 +err:
 410 +       disable_irq(qup->irq);
 411 +       qup->msg = NULL;
 412 +
 413 +       return ret;
 414 +}
 415 +
 416 +static void qup_i2c_set_read_mode(struct qup_i2c_dev *qup, int len)
 417 +{
 418 +       if (len < qup->in_fifo_sz) {
 419 +               /* FIFO mode */
 420 +               writel(QUP_REPACK_EN, qup->base + QUP_IO_MODE);
 421 +               writel(len, qup->base + QUP_MX_READ_CNT);
 422 +       } else {
 423 +               /* BLOCK mode (transfer data on chunks) */
 424 +               writel(QUP_INPUT_BLK_MODE | QUP_REPACK_EN,
 425 +                      qup->base + QUP_IO_MODE);
 426 +               writel(len, qup->base + QUP_MX_INPUT_CNT);
 427 +       }
 428 +}
 429 +
 430 +static void qup_i2c_issue_read(struct qup_i2c_dev *qup, struct i2c_msg *msg)
 431 +{
 432 +       u32 addr, len, val;
 433 +
 434 +       addr = (msg->addr << 1) | 1;
 435 +
 436 +       /* 0 is used to specify a length 256 (QUP_READ_LIMIT) */
 437 +       len = (msg->len == QUP_READ_LIMIT) ? 0 : msg->len;
 438 +
 439 +       val = ((QUP_TAG_REC | len) << QUP_MSW_SHIFT) | QUP_TAG_START | addr;
 440 +       writel(val, qup->base + QUP_OUT_FIFO_BASE);
 441 +}
 442 +
 443 +
 444 +static void qup_i2c_read_fifo(struct qup_i2c_dev *qup, struct i2c_msg *msg)
 445 +{
 446 +       u32 opflags;
 447 +       u32 val = 0;
 448 +       int idx;
 449 +
 450 +       for (idx = 0; qup->pos < msg->len; idx++) {
 451 +               if ((idx & 1) == 0) {
 452 +                       /* Check that FIFO have data */
 453 +                       opflags = readl(qup->base + QUP_OPERATIONAL);
 454 +                       if (!(opflags & QUP_IN_NOT_EMPTY))
 455 +                               break;
 456 +
 457 +                       /* Reading 2 words at time */
 458 +                       val = readl(qup->base + QUP_IN_FIFO_BASE);
 459 +
 460 +                       msg->buf[qup->pos++] = val & 0xFF;
 461 +               } else {
 462 +                       msg->buf[qup->pos++] = val >> QUP_MSW_SHIFT;
 463 +               }
 464 +       }
 465 +}
 466 +
 467 +static int qup_i2c_read_one(struct qup_i2c_dev *qup, struct i2c_msg *msg)
 468 +{
 469 +       unsigned long left;
 470 +       int ret;
 471 +
 472 +       /*
 473 +        * The QUP block will issue a NACK and STOP on the bus when reaching
 474 +        * the end of the read, the length of the read is specified as one byte
 475 +        * which limits the possible read to 256 (QUP_READ_LIMIT) bytes.
 476 +        */
 477 +       if (msg->len > QUP_READ_LIMIT) {
 478 +               dev_err(qup->dev, "HW not capable of reads over %d bytes\n",
 479 +                       QUP_READ_LIMIT);
 480 +               return -EINVAL;
 481 +       }
 482 +
 483 +       qup->msg = msg;
 484 +       qup->pos  = 0;
 485 +
 486 +       enable_irq(qup->irq);
 487 +
 488 +       qup_i2c_set_read_mode(qup, msg->len);
 489 +
 490 +       ret = qup_i2c_change_state(qup, QUP_RUN_STATE);
 491 +       if (ret)
 492 +               goto err;
 493 +
 494 +       writel(qup->clk_ctl, qup->base + QUP_I2C_CLK_CTL);
 495 +
 496 +       ret = qup_i2c_change_state(qup, QUP_PAUSE_STATE);
 497 +       if (ret)
 498 +               goto err;
 499 +
 500 +       qup_i2c_issue_read(qup, msg);
 501 +
 502 +       ret = qup_i2c_change_state(qup, QUP_RUN_STATE);
 503 +       if (ret)
 504 +               goto err;
 505 +
 506 +       do {
 507 +               left = wait_for_completion_timeout(&qup->xfer, HZ);
 508 +               if (!left) {
 509 +                       writel(1, qup->base + QUP_SW_RESET);
 510 +                       ret = -ETIMEDOUT;
 511 +                       goto err;
 512 +               }
 513 +
 514 +               if (qup->bus_err || qup->qup_err) {
 515 +                       if (qup->bus_err & QUP_I2C_NACK_FLAG)
 516 +                               dev_err(qup->dev, "NACK from %x\n", msg->addr);
 517 +                       ret = -EIO;
 518 +                       goto err;
 519 +               }
 520 +
 521 +               qup_i2c_read_fifo(qup, msg);
 522 +       } while (qup->pos < msg->len);
 523 +
 524 +err:
 525 +       disable_irq(qup->irq);
 526 +       qup->msg = NULL;
 527 +
 528 +       return ret;
 529 +}
 530 +
 531 +static int qup_i2c_xfer(struct i2c_adapter *adap,
 532 +                       struct i2c_msg msgs[],
 533 +                       int num)
 534 +{
 535 +       struct qup_i2c_dev *qup = i2c_get_adapdata(adap);
 536 +       int ret, idx;
 537 +
 538 +       ret = pm_runtime_get_sync(qup->dev);
 539 +       if (ret)
 540 +               goto out;
 541 +
 542 +       writel(1, qup->base + QUP_SW_RESET);
 543 +       ret = qup_i2c_poll_state(qup, QUP_RESET_STATE);
 544 +       if (ret)
 545 +               goto out;
 546 +
 547 +       /* Configure QUP as I2C mini core */
 548 +       writel(I2C_MINI_CORE | I2C_N_VAL, qup->base + QUP_CONFIG);
 549 +
 550 +       for (idx = 0; idx < num; idx++) {
 551 +               if (msgs[idx].len == 0) {
 552 +                       ret = -EINVAL;
 553 +                       goto out;
 554 +               }
 555 +
 556 +               if (qup_i2c_poll_state_i2c_master(qup)) {
 557 +                       ret = -EIO;
 558 +                       goto out;
 559 +               }
 560 +
 561 +               if (msgs[idx].flags & I2C_M_RD)
 562 +                       ret = qup_i2c_read_one(qup, &msgs[idx]);
 563 +               else
 564 +                       ret = qup_i2c_write_one(qup, &msgs[idx]);
 565 +
 566 +               if (ret)
 567 +                       break;
 568 +
 569 +               ret = qup_i2c_change_state(qup, QUP_RESET_STATE);
 570 +               if (ret)
 571 +                       break;
 572 +       }
 573 +
 574 +       if (ret == 0)
 575 +               ret = num;
 576 +out:
 577 +
 578 +       pm_runtime_mark_last_busy(qup->dev);
 579 +       pm_runtime_put_autosuspend(qup->dev);
 580 +
 581 +       return ret;
 582 +}
 583 +
 584 +static u32 qup_i2c_func(struct i2c_adapter *adap)
 585 +{
 586 +       return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
 587 +}
 588 +
 589 +static const struct i2c_algorithm qup_i2c_algo = {
 590 +       .master_xfer    = qup_i2c_xfer,
 591 +       .functionality  = qup_i2c_func,
 592 +};
 593 +
 594 +static void qup_i2c_enable_clocks(struct qup_i2c_dev *qup)
 595 +{
 596 +       clk_prepare_enable(qup->clk);
 597 +       clk_prepare_enable(qup->pclk);
 598 +}
 599 +
 600 +static void qup_i2c_disable_clocks(struct qup_i2c_dev *qup)
 601 +{
 602 +       u32 config;
 603 +
 604 +       qup_i2c_change_state(qup, QUP_RESET_STATE);
 605 +       clk_disable_unprepare(qup->clk);
 606 +       config = readl(qup->base + QUP_CONFIG);
 607 +       config |= QUP_CLOCK_AUTO_GATE;
 608 +       writel(config, qup->base + QUP_CONFIG);
 609 +       clk_disable_unprepare(qup->pclk);
 610 +}
 611 +
 612 +static int qup_i2c_probe(struct platform_device *pdev)
 613 +{
 614 +       static const int blk_sizes[] = {4, 16, 32};
 615 +       struct device_node *node = pdev->dev.of_node;
 616 +       struct qup_i2c_dev *qup;
 617 +       unsigned long one_bit_t;
 618 +       struct resource *res;
 619 +       u32 io_mode, hw_ver, size;
 620 +       int ret, fs_div, hs_div;
 621 +       int src_clk_freq;
 622 +       int clk_freq = 100000;
 623 +
 624 +       qup = devm_kzalloc(&pdev->dev, sizeof(*qup), GFP_KERNEL);
 625 +       if (!qup)
 626 +               return -ENOMEM;
 627 +
 628 +       qup->dev = &pdev->dev;
 629 +       init_completion(&qup->xfer);
 630 +       platform_set_drvdata(pdev, qup);
 631 +
 632 +       of_property_read_u32(node, "clock-frequency", &clk_freq);
 633 +
 634 +       /* We support frequencies up to FAST Mode (400KHz) */
 635 +       if (!clk_freq || clk_freq > 400000) {
 636 +               dev_err(qup->dev, "clock frequency not supported %d\n",
 637 +                       clk_freq);
 638 +               return -EINVAL;
 639 +       }
 640 +
 641 +       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 642 +       qup->base = devm_ioremap_resource(qup->dev, res);
 643 +       if (IS_ERR(qup->base))
 644 +               return PTR_ERR(qup->base);
 645 +
 646 +       qup->irq = platform_get_irq(pdev, 0);
 647 +       if (qup->irq < 0) {
 648 +               dev_err(qup->dev, "No IRQ defined\n");
 649 +               return qup->irq;
 650 +       }
 651 +
 652 +       qup->clk = devm_clk_get(qup->dev, "core");
 653 +       if (IS_ERR(qup->clk)) {
 654 +               dev_err(qup->dev, "Could not get core clock\n");
 655 +               return PTR_ERR(qup->clk);
 656 +       }
 657 +
 658 +       qup->pclk = devm_clk_get(qup->dev, "iface");
 659 +       if (IS_ERR(qup->pclk)) {
 660 +               dev_err(qup->dev, "Could not get iface clock\n");
 661 +               return PTR_ERR(qup->pclk);
 662 +       }
 663 +
 664 +       qup_i2c_enable_clocks(qup);
 665 +
 666 +       /*
 667 +        * Bootloaders might leave a pending interrupt on certain QUP's,
 668 +        * so we reset the core before registering for interrupts.
 669 +        */
 670 +       writel(1, qup->base + QUP_SW_RESET);
 671 +       ret = qup_i2c_poll_state_valid(qup);
 672 +       if (ret)
 673 +               goto fail;
 674 +
 675 +       ret = devm_request_irq(qup->dev, qup->irq, qup_i2c_interrupt,
 676 +                              IRQF_TRIGGER_HIGH, "i2c_qup", qup);
 677 +       if (ret) {
 678 +               dev_err(qup->dev, "Request %d IRQ failed\n", qup->irq);
 679 +               goto fail;
 680 +       }
 681 +       disable_irq(qup->irq);
 682 +
 683 +       hw_ver = readl(qup->base + QUP_HW_VERSION);
 684 +       dev_dbg(qup->dev, "Revision %x\n", hw_ver);
 685 +
 686 +       io_mode = readl(qup->base + QUP_IO_MODE);
 687 +
 688 +       /*
 689 +        * The block/fifo size w.r.t. 'actual data' is 1/2 due to 'tag'
 690 +        * associated with each byte written/received
 691 +        */
 692 +       size = QUP_OUTPUT_BLOCK_SIZE(io_mode);
 693 +       if (size > ARRAY_SIZE(blk_sizes))
 694 +               return -EIO;
 695 +       qup->out_blk_sz = blk_sizes[size] / 2;
 696 +
 697 +       size = QUP_INPUT_BLOCK_SIZE(io_mode);
 698 +       if (size > ARRAY_SIZE(blk_sizes))
 699 +               return -EIO;
 700 +       qup->in_blk_sz = blk_sizes[size] / 2;
 701 +
 702 +       size = QUP_OUTPUT_FIFO_SIZE(io_mode);
 703 +       qup->out_fifo_sz = qup->out_blk_sz * (2 << size);
 704 +
 705 +       size = QUP_INPUT_FIFO_SIZE(io_mode);
 706 +       qup->in_fifo_sz = qup->in_blk_sz * (2 << size);
 707 +
 708 +       src_clk_freq = clk_get_rate(qup->clk);
 709 +       fs_div = ((src_clk_freq / clk_freq) / 2) - 3;
 710 +       hs_div = 3;
 711 +       qup->clk_ctl = (hs_div << 8) | (fs_div & 0xff);
 712 +
 713 +       /*
 714 +        * Time it takes for a byte to be clocked out on the bus.
 715 +        * Each byte takes 9 clock cycles (8 bits + 1 ack).
 716 +        */
 717 +       one_bit_t = (USEC_PER_SEC / clk_freq) + 1;
 718 +       qup->one_byte_t = one_bit_t * 9;
 719 +
 720 +       dev_dbg(qup->dev, "IN:block:%d, fifo:%d, OUT:block:%d, fifo:%d\n",
 721 +               qup->in_blk_sz, qup->in_fifo_sz,
 722 +               qup->out_blk_sz, qup->out_fifo_sz);
 723 +
 724 +       i2c_set_adapdata(&qup->adap, qup);
 725 +       qup->adap.algo = &qup_i2c_algo;
 726 +       qup->adap.dev.parent = qup->dev;
 727 +       qup->adap.dev.of_node = pdev->dev.of_node;
 728 +       strlcpy(qup->adap.name, "QUP I2C adapter", sizeof(qup->adap.name));
 729 +
 730 +       ret = i2c_add_adapter(&qup->adap);
 731 +       if (ret)
 732 +               goto fail;
 733 +
 734 +       pm_runtime_set_autosuspend_delay(qup->dev, MSEC_PER_SEC);
 735 +       pm_runtime_use_autosuspend(qup->dev);
 736 +       pm_runtime_set_active(qup->dev);
 737 +       pm_runtime_enable(qup->dev);
 738 +       return 0;
 739 +
 740 +fail:
 741 +       qup_i2c_disable_clocks(qup);
 742 +       return ret;
 743 +}
 744 +
 745 +static int qup_i2c_remove(struct platform_device *pdev)
 746 +{
 747 +       struct qup_i2c_dev *qup = platform_get_drvdata(pdev);
 748 +
 749 +       disable_irq(qup->irq);
 750 +       qup_i2c_disable_clocks(qup);
 751 +       i2c_del_adapter(&qup->adap);
 752 +       pm_runtime_disable(qup->dev);
 753 +       pm_runtime_set_suspended(qup->dev);
 754 +       return 0;
 755 +}
 756 +
 757 +#ifdef CONFIG_PM
 758 +static int qup_i2c_pm_suspend_runtime(struct device *device)
 759 +{
 760 +       struct qup_i2c_dev *qup = dev_get_drvdata(device);
 761 +
 762 +       dev_dbg(device, "pm_runtime: suspending...\n");
 763 +       qup_i2c_disable_clocks(qup);
 764 +       return 0;
 765 +}
 766 +
 767 +static int qup_i2c_pm_resume_runtime(struct device *device)
 768 +{
 769 +       struct qup_i2c_dev *qup = dev_get_drvdata(device);
 770 +
 771 +       dev_dbg(device, "pm_runtime: resuming...\n");
 772 +       qup_i2c_enable_clocks(qup);
 773 +       return 0;
 774 +}
 775 +#endif
 776 +
 777 +#ifdef CONFIG_PM_SLEEP
 778 +static int qup_i2c_suspend(struct device *device)
 779 +{
 780 +       qup_i2c_pm_suspend_runtime(device);
 781 +       return 0;
 782 +}
 783 +
 784 +static int qup_i2c_resume(struct device *device)
 785 +{
 786 +       qup_i2c_pm_resume_runtime(device);
 787 +       pm_runtime_mark_last_busy(device);
 788 +       pm_request_autosuspend(device);
 789 +       return 0;
 790 +}
 791 +#endif
 792 +
 793 +static const struct dev_pm_ops qup_i2c_qup_pm_ops = {
 794 +       SET_SYSTEM_SLEEP_PM_OPS(
 795 +               qup_i2c_suspend,
 796 +               qup_i2c_resume)
 797 +       SET_RUNTIME_PM_OPS(
 798 +               qup_i2c_pm_suspend_runtime,
 799 +               qup_i2c_pm_resume_runtime,
 800 +               NULL)
 801 +};
 802 +
 803 +static const struct of_device_id qup_i2c_dt_match[] = {
 804 +       { .compatible = "qcom,i2c-qup-v1.1.1" },
 805 +       { .compatible = "qcom,i2c-qup-v2.1.1" },
 806 +       { .compatible = "qcom,i2c-qup-v2.2.1" },
 807 +       {}
 808 +};
 809 +MODULE_DEVICE_TABLE(of, qup_i2c_dt_match);
 810 +
 811 +static struct platform_driver qup_i2c_driver = {
 812 +       .probe  = qup_i2c_probe,
 813 +       .remove = qup_i2c_remove,
 814 +       .driver = {
 815 +               .name = "i2c_qup",
 816 +               .owner = THIS_MODULE,
 817 +               .pm = &qup_i2c_qup_pm_ops,
 818 +               .of_match_table = qup_i2c_dt_match,
 819 +       },
 820 +};
 821 +
 822 +module_platform_driver(qup_i2c_driver);
 823 +
 824 +MODULE_LICENSE("GPL v2");
 825 +MODULE_ALIAS("platform:i2c_qup");