target/linux/ipq806x/files-4.9/arch/arm/boot/dts/qcom-ipq8064.dtsi

   1 /dts-v1/;
   2
   3 #include "skeleton.dtsi"
   4 #include <dt-bindings/clock/qcom,gcc-ipq806x.h>
   5 #include <dt-bindings/mfd/qcom-rpm.h>
   6 #include <dt-bindings/clock/qcom,rpmcc.h>
   7 #include <dt-bindings/clock/qcom,lcc-ipq806x.h>
   8 #include <dt-bindings/soc/qcom,gsbi.h>
   9 #include <dt-bindings/reset/qcom,gcc-ipq806x.h>
  10 #include <dt-bindings/interrupt-controller/arm-gic.h>
  11 #include <dt-bindings/gpio/gpio.h>
  12
  13 / {
  14         model = "Qualcomm IPQ8064";
  15         compatible = "qcom,ipq8064";
  16         interrupt-parent = <&intc>;
  17
  18         cpus {
  19                 #address-cells = <1>;
  20                 #size-cells = <0>;
  21
  22                 cpu0: cpu@0 {
  23                         compatible = "qcom,krait";
  24                         enable-method = "qcom,kpss-acc-v1";
  25                         device_type = "cpu";
  26                         reg = <0>;
  27                         next-level-cache = <&L2>;
  28                         qcom,acc = <&acc0>;
  29                         qcom,saw = <&saw0>;
  30                         clocks = <&kraitcc 0>, <&kraitcc 4>;
  31                         clock-names = "cpu", "l2";
  32                         clock-latency = <100000>;
  33                         cpu-supply = <&smb208_s2a>;
  34                         voltage-tolerance = <5>;
  35                         cooling-min-state = <0>;
  36                         cooling-max-state = <10>;
  37                         #cooling-cells = <2>;
  38                         cpu-idle-states = <&CPU_SPC>;
  39                 };
  40
  41                 cpu1: cpu@1 {
  42                         compatible = "qcom,krait";
  43                         enable-method = "qcom,kpss-acc-v1";
  44                         device_type = "cpu";
  45                         reg = <1>;
  46                         next-level-cache = <&L2>;
  47                         qcom,acc = <&acc1>;
  48                         qcom,saw = <&saw1>;
  49                         clocks = <&kraitcc 1>, <&kraitcc 4>;
  50                         clock-names = "cpu", "l2";
  51                         clock-latency = <100000>;
  52                         cpu-supply = <&smb208_s2b>;
  53                         cooling-min-state = <0>;
  54                         cooling-max-state = <10>;
  55                         #cooling-cells = <2>;
  56                         cpu-idle-states = <&CPU_SPC>;
  57                 };
  58
  59                 L2: l2-cache {
  60                         compatible = "cache";
  61                         cache-level = <2>;
  62                         qcom,saw = <&saw_l2>;
  63                 };
  64
  65                 qcom,l2 {
  66                         qcom,l2-rates = <384000000 1000000000 1200000000>;
  67                 };
  68
  69                 idle-states {
  70                         CPU_SPC: spc {
  71                                 compatible = "qcom,idle-state-spc",
  72                                                 "arm,idle-state";
  73                                 entry-latency-us = <400>;
  74                                 exit-latency-us = <900>;
  75                                 min-residency-us = <3000>;
  76                         };
  77                 };
  78         };
  79
  80         thermal-zones {
  81                 cpu-thermal0 {
  82                         polling-delay-passive = <250>;
  83                         polling-delay = <1000>;
  84
  85                         thermal-sensors = <&gcc 5>;
  86                         coefficients = <1132 0>;
  87
  88                         trips {
  89                                 cpu_alert0: trip0 {
  90                                         temperature = <75000>;
  91                                         hysteresis = <2000>;
  92                                         type = "passive";
  93                                 };
  94                                 cpu_crit0: trip1 {
  95                                         temperature = <110000>;
  96                                         hysteresis = <2000>;
  97                                         type = "critical";
  98                                 };
  99                         };
 100                 };
 101
 102                 cpu-thermal1 {
 103                         polling-delay-passive = <250>;
 104                         polling-delay = <1000>;
 105
 106                         thermal-sensors = <&gcc 6>;
 107                         coefficients = <1132 0>;
 108
 109                         trips {
 110                                 cpu_alert1: trip0 {
 111                                         temperature = <75000>;
 112                                         hysteresis = <2000>;
 113                                         type = "passive";
 114                                 };
 115                                 cpu_crit1: trip1 {
 116                                         temperature = <110000>;
 117                                         hysteresis = <2000>;
 118                                         type = "critical";
 119                                 };
 120                         };
 121                 };
 122
 123                 cpu-thermal2 {
 124                         polling-delay-passive = <250>;
 125                         polling-delay = <1000>;
 126
 127                         thermal-sensors = <&gcc 7>;
 128                         coefficients = <1199 0>;
 129
 130                         trips {
 131                                 cpu_alert2: trip0 {
 132                                         temperature = <75000>;
 133                                         hysteresis = <2000>;
 134                                         type = "passive";
 135                                 };
 136                                 cpu_crit2: trip1 {
 137                                         temperature = <110000>;
 138                                         hysteresis = <2000>;
 139                                         type = "critical";
 140                                 };
 141                         };
 142                 };
 143
 144                 cpu-thermal3 {
 145                         polling-delay-passive = <250>;
 146                         polling-delay = <1000>;
 147
 148                         thermal-sensors = <&gcc 8>;
 149                         coefficients = <1132 0>;
 150
 151                         trips {
 152                                 cpu_alert3: trip0 {
 153                                         temperature = <75000>;
 154                                         hysteresis = <2000>;
 155                                         type = "passive";
 156                                 };
 157                                 cpu_crit3: trip1 {
 158                                         temperature = <110000>;
 159                                         hysteresis = <2000>;
 160                                         type = "critical";
 161                                 };
 162                         };
 163                 };
 164         };
 165
 166         cpu-pmu {
 167                 compatible = "qcom,krait-pmu";
 168                 interrupts = <1 10 0x304>;
 169         };
 170
 171         reserved-memory {
 172                 #address-cells = <1>;
 173                 #size-cells = <1>;
 174                 ranges;
 175
 176                 nss@40000000 {
 177                         reg = <0x40000000 0x1000000>;
 178                         no-map;
 179                 };
 180
 181                 smem: smem@41000000 {
 182                         reg = <0x41000000 0x200000>;
 183                         no-map;
 184                 };
 185         };
 186
 187         clocks {
 188                 cxo_board {
 189                         compatible = "fixed-clock";
 190                         #clock-cells = <0>;
 191                         clock-frequency = <25000000>;
 192                 };
 193
 194                 pxo_board {
 195                         compatible = "fixed-clock";
 196                         #clock-cells = <0>;
 197                         clock-frequency = <25000000>;
 198                 };
 199
 200                 sleep_clk: sleep_clk {
 201                         compatible = "fixed-clock";
 202                         clock-frequency = <32768>;
 203                         #clock-cells = <0>;
 204                 };
 205         };
 206
 207         firmware {
 208                 scm {
 209                         compatible = "qcom,scm-apq8064";
 210
 211                         clocks = <&rpmcc RPM_DAYTONA_FABRIC_CLK>;
 212                         clock-names = "core";
 213                 };
 214         };
 215
 216         kraitcc: clock-controller {
 217                 compatible = "qcom,krait-cc-v1";
 218                 #clock-cells = <1>;
 219         };
 220
 221         qcom,pvs {
 222                 qcom,pvs-format-a;
 223                 qcom,speed0-pvs0-bin-v0 =
 224                         < 1400000000 1250000 >,
 225                         < 1200000000 1200000 >,
 226                         < 1000000000 1150000 >,
 227                          < 800000000 1100000 >,
 228                          < 600000000 1050000 >,
 229                          < 384000000 1000000 >;
 230
 231                 qcom,speed0-pvs1-bin-v0 =
 232                         < 1400000000 1175000 >,
 233                         < 1200000000 1125000 >,
 234                         < 1000000000 1075000 >,
 235                          < 800000000 1025000 >,
 236                          < 600000000  975000 >,
 237                          < 384000000  925000 >;
 238
 239                 qcom,speed0-pvs2-bin-v0 =
 240                         < 1400000000 1125000 >,
 241                         < 1200000000 1075000 >,
 242                         < 1000000000 1025000 >,
 243                          < 800000000  995000 >,
 244                          < 600000000  925000 >,
 245                          < 384000000  875000 >;
 246
 247                 qcom,speed0-pvs3-bin-v0 =
 248                         < 1400000000 1050000 >,
 249                         < 1200000000 1000000 >,
 250                         < 1000000000  950000 >,
 251                          < 800000000  900000 >,
 252                          < 600000000  850000 >,
 253                          < 384000000  800000 >;
 254         };
 255
 256         soc: soc {
 257                 #address-cells = <1>;
 258                 #size-cells = <1>;
 259                 ranges;
 260                 compatible = "simple-bus";
 261
 262                 lpass@28100000 {
 263                         compatible = "qcom,lpass-cpu";
 264                         status = "disabled";
 265                         clocks = <&lcc AHBIX_CLK>,
 266                                         <&lcc MI2S_OSR_CLK>,
 267                                         <&lcc MI2S_BIT_CLK>;
 268                         clock-names = "ahbix-clk",
 269                                         "mi2s-osr-clk",
 270                                         "mi2s-bit-clk";
 271                         interrupts = <0 85 1>;
 272                         interrupt-names = "lpass-irq-lpaif";
 273                         reg = <0x28100000 0x10000>;
 274                         reg-names = "lpass-lpaif";
 275                 };
 276
 277                 qfprom: qfprom@700000 {
 278                         compatible = "qcom,qfprom", "syscon";
 279                         reg = <0x00700000 0x1000>;
 280                         #address-cells = <1>;
 281                         #size-cells = <1>;
 282                         ranges;
 283
 284                         tsens_calib: calib {
 285                                 reg = <0x400 0x10>;
 286                         };
 287                         tsens_backup: backup_calib {
 288                                 reg = <0x410 0x10>;
 289                         };
 290                 };
 291
 292                 rpm@108000 {
 293                         compatible = "qcom,rpm-ipq8064";
 294                         reg = <0x108000 0x1000>;
 295                         qcom,ipc = <&l2cc 0x8 2>;
 296
 297                         interrupts = <0 19 0>,
 298                                      <0 21 0>,
 299                                      <0 22 0>;
 300                         interrupt-names = "ack",
 301                                           "err",
 302                                           "wakeup";
 303
 304                         clocks = <&gcc RPM_MSG_RAM_H_CLK>;
 305                         clock-names = "ram";
 306
 307                         #address-cells = <1>;
 308                         #size-cells = <0>;
 309
 310                         rpmcc: clock-controller {
 311                                 compatible      = "qcom,rpmcc-ipq806x", "qcom,rpmcc";
 312                                 #clock-cells = <1>;
 313                         };
 314
 315                         regulators {
 316                                 compatible = "qcom,rpm-smb208-regulators";
 317
 318                                 smb208_s1a: s1a {
 319                                         regulator-min-microvolt = <1050000>;
 320                                         regulator-max-microvolt = <1150000>;
 321
 322                                         qcom,switch-mode-frequency = <1200000>;
 323
 324                                 };
 325
 326                                 smb208_s1b: s1b {
 327                                         regulator-min-microvolt = <1050000>;
 328                                         regulator-max-microvolt = <1150000>;
 329
 330                                         qcom,switch-mode-frequency = <1200000>;
 331                                 };
 332
 333                                 smb208_s2a: s2a {
 334                                         regulator-min-microvolt = < 800000>;
 335                                         regulator-max-microvolt = <1250000>;
 336
 337                                         qcom,switch-mode-frequency = <1200000>;
 338                                 };
 339
 340                                 smb208_s2b: s2b {
 341                                         regulator-min-microvolt = < 800000>;
 342                                         regulator-max-microvolt = <1250000>;
 343
 344                                         qcom,switch-mode-frequency = <1200000>;
 345                                 };
 346                         };
 347                 };
 348
 349                 rng@1a500000 {
 350                         compatible = "qcom,prng";
 351                         reg = <0x1a500000 0x200>;
 352                         clocks = <&gcc PRNG_CLK>;
 353                         clock-names = "core";
 354                 };
 355
 356                 qcom_pinmux: pinmux@800000 {
 357                         compatible = "qcom,ipq8064-pinctrl";
 358                         reg = <0x800000 0x4000>;
 359
 360                         gpio-controller;
 361                         #gpio-cells = <2>;
 362                         interrupt-controller;
 363                         #interrupt-cells = <2>;
 364                         interrupts = <0 16 0x4>;
 365
 366                         pcie0_pins: pcie0_pinmux {
 367                                 mux {
 368                                         pins = "gpio3";
 369                                         function = "pcie1_rst";
 370                                         drive-strength = <2>;
 371                                         bias-disable;
 372                                 };
 373                         };
 374
 375                         pcie1_pins: pcie1_pinmux {
 376                                 mux {
 377                                         pins = "gpio48";
 378                                         function = "pcie2_rst";
 379                                         drive-strength = <2>;
 380                                         bias-disable;
 381                                 };
 382                         };
 383
 384                         pcie2_pins: pcie2_pinmux {
 385                                 mux {
 386                                         pins = "gpio63";
 387                                         function = "pcie3_rst";
 388                                         drive-strength = <2>;
 389                                         bias-disable;
 390                                         output-low;
 391                                 };
 392                         };
 393                 };
 394
 395                 intc: interrupt-controller@2000000 {
 396                         compatible = "qcom,msm-qgic2";
 397                         interrupt-controller;
 398                         #interrupt-cells = <3>;
 399                         reg = <0x02000000 0x1000>,
 400                               <0x02002000 0x1000>;
 401                 };
 402
 403                 timer@200a000 {
 404                         compatible = "qcom,kpss-timer", "qcom,msm-timer";
 405                         interrupts = <1 1 0x301>,
 406                                      <1 2 0x301>,
 407                                      <1 3 0x301>,
 408                                      <1 4 0x301>,
 409                                      <1 5 0x301>;
 410                         reg = <0x0200a000 0x100>;
 411                         clock-frequency = <25000000>,
 412                                           <32768>;
 413                         clocks = <&sleep_clk>;
 414                         clock-names = "sleep";
 415                         cpu-offset = <0x80000>;
 416                 };
 417
 418                 acc0: clock-controller@2088000 {
 419                         compatible = "qcom,kpss-acc-v1";
 420                         reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
 421                         clock-output-names = "acpu0_aux";
 422                 };
 423
 424                 acc1: clock-controller@2098000 {
 425                         compatible = "qcom,kpss-acc-v1";
 426                         reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
 427                         clock-output-names = "acpu1_aux";
 428                 };
 429
 430                 l2cc: clock-controller@2011000 {
 431                         compatible = "qcom,kpss-gcc", "syscon";
 432                         reg = <0x2011000 0x1000>;
 433                         clock-output-names = "acpu_l2_aux";
 434                 };
 435
 436                 saw0: regulator@2089000 {
 437                         compatible = "qcom,saw2", "syscon";
 438                         reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
 439                         regulator;
 440                 };
 441
 442                 saw1: regulator@2099000 {
 443                         compatible = "qcom,saw2", "syscon";
 444                         reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
 445                         regulator;
 446                 };
 447
 448                 saw_l2: regulator@02012000 {
 449                         compatible = "qcom,saw2", "syscon";
 450                         reg = <0x02012000 0x1000>;
 451                         regulator;
 452                 };
 453
 454                 sic_non_secure: sic-non-secure@12100000 {
 455                         compatible = "syscon";
 456                         reg = <0x12100000 0x10000>;
 457                 };
 458
 459                 gsbi2: gsbi@12480000 {
 460                         compatible = "qcom,gsbi-v1.0.0";
 461                         cell-index = <2>;
 462                         reg = <0x12480000 0x100>;
 463                         clocks = <&gcc GSBI2_H_CLK>;
 464                         clock-names = "iface";
 465                         #address-cells = <1>;
 466                         #size-cells = <1>;
 467                         ranges;
 468                         status = "disabled";
 469
 470                         syscon-tcsr = <&tcsr>;
 471
 472                         uart2: serial@12490000 {
 473                                 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
 474                                 reg = <0x12490000 0x1000>,
 475                                       <0x12480000 0x1000>;
 476                                 interrupts = <0 195 0x0>;
 477                                 clocks = <&gcc GSBI2_UART_CLK>, <&gcc GSBI2_H_CLK>;
 478                                 clock-names = "core", "iface";
 479                                 status = "disabled";
 480                         };
 481
 482                         i2c@124a0000 {
 483                                 compatible = "qcom,i2c-qup-v1.1.1";
 484                                 reg = <0x124a0000 0x1000>;
 485                                 interrupts = <0 196 0>;
 486
 487                                 clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
 488                                 clock-names = "core", "iface";
 489                                 status = "disabled";
 490
 491                                 #address-cells = <1>;
 492                                 #size-cells = <0>;
 493                         };
 494
 495                 };
 496
 497                 gsbi4: gsbi@16300000 {
 498                         compatible = "qcom,gsbi-v1.0.0";
 499                         cell-index = <4>;
 500                         reg = <0x16300000 0x100>;
 501                         clocks = <&gcc GSBI4_H_CLK>;
 502                         clock-names = "iface";
 503                         #address-cells = <1>;
 504                         #size-cells = <1>;
 505                         ranges;
 506                         status = "disabled";
 507
 508                         syscon-tcsr = <&tcsr>;
 509
 510                         gsbi4_serial: serial@16340000 {
 511                                 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
 512                                 reg = <0x16340000 0x1000>,
 513                                       <0x16300000 0x1000>;
 514                                 interrupts = <0 152 0x0>;
 515                                 clocks = <&gcc GSBI4_UART_CLK>, <&gcc GSBI4_H_CLK>;
 516                                 clock-names = "core", "iface";
 517                                 status = "disabled";
 518                         };
 519
 520                         i2c@16380000 {
 521                                 compatible = "qcom,i2c-qup-v1.1.1";
 522                                 reg = <0x16380000 0x1000>;
 523                                 interrupts = <0 153 0>;
 524
 525                                 clocks = <&gcc GSBI4_QUP_CLK>, <&gcc GSBI4_H_CLK>;
 526                                 clock-names = "core", "iface";
 527                                 status = "disabled";
 528
 529                                 #address-cells = <1>;
 530                                 #size-cells = <0>;
 531                         };
 532                 };
 533
 534                 gsbi5: gsbi@1a200000 {
 535                         compatible = "qcom,gsbi-v1.0.0";
 536                         cell-index = <5>;
 537                         reg = <0x1a200000 0x100>;
 538                         clocks = <&gcc GSBI5_H_CLK>;
 539                         clock-names = "iface";
 540                         #address-cells = <1>;
 541                         #size-cells = <1>;
 542                         ranges;
 543                         status = "disabled";
 544
 545                         syscon-tcsr = <&tcsr>;
 546
 547                         uart5: serial@1a240000 {
 548                                 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
 549                                 reg = <0x1a240000 0x1000>,
 550                                       <0x1a200000 0x1000>;
 551                                 interrupts = <0 154 0x0>;
 552                                 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
 553                                 clock-names = "core", "iface";
 554                                 status = "disabled";
 555                         };
 556
 557                         i2c@1a280000 {
 558                                 compatible = "qcom,i2c-qup-v1.1.1";
 559                                 reg = <0x1a280000 0x1000>;
 560                                 interrupts = <0 155 0>;
 561
 562                                 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
 563                                 clock-names = "core", "iface";
 564                                 status = "disabled";
 565
 566                                 #address-cells = <1>;
 567                                 #size-cells = <0>;
 568                         };
 569
 570                         spi@1a280000 {
 571                                 compatible = "qcom,spi-qup-v1.1.1";
 572                                 reg = <0x1a280000 0x1000>;
 573                                 interrupts = <0 155 0>;
 574
 575                                 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
 576                                 clock-names = "core", "iface";
 577                                 status = "disabled";
 578
 579                                 #address-cells = <1>;
 580                                 #size-cells = <0>;
 581                         };
 582                 };
 583
 584                 sata_phy: sata-phy@1b400000 {
 585                         compatible = "qcom,ipq806x-sata-phy";
 586                         reg = <0x1b400000 0x200>;
 587
 588                         clocks = <&gcc SATA_PHY_CFG_CLK>;
 589                         clock-names = "cfg";
 590
 591                         #phy-cells = <0>;
 592                         status = "disabled";
 593                 };
 594
 595                 sata@29000000 {
 596                         compatible = "qcom,ipq806x-ahci", "generic-ahci";
 597                         reg = <0x29000000 0x180>;
 598
 599                         interrupts = <0 209 0x0>;
 600
 601                         clocks = <&gcc SFAB_SATA_S_H_CLK>,
 602                                  <&gcc SATA_H_CLK>,
 603                                  <&gcc SATA_A_CLK>,
 604                                  <&gcc SATA_RXOOB_CLK>,
 605                                  <&gcc SATA_PMALIVE_CLK>;
 606                         clock-names = "slave_face", "iface", "core",
 607                                         "rxoob", "pmalive";
 608
 609                         assigned-clocks = <&gcc SATA_RXOOB_CLK>, <&gcc SATA_PMALIVE_CLK>;
 610                         assigned-clock-rates = <100000000>, <100000000>;
 611
 612                         phys = <&sata_phy>;
 613                         phy-names = "sata-phy";
 614                         status = "disabled";
 615                 };
 616
 617                 qcom,ssbi@500000 {
 618                         compatible = "qcom,ssbi";
 619                         reg = <0x00500000 0x1000>;
 620                         qcom,controller-type = "pmic-arbiter";
 621                 };
 622
 623                 gcc: clock-controller@900000 {
 624                         compatible = "qcom,gcc-ipq8064";
 625                         reg = <0x00900000 0x4000>;
 626                         nvmem-cells = <&tsens_calib>, <&tsens_backup>;
 627                         nvmem-cell-names = "calib", "calib_backup";
 628                         #clock-cells = <1>;
 629                         #reset-cells = <1>;
 630                         #power-domain-cells = <1>;
 631                         #thermal-sensor-cells = <1>;
 632                 };
 633
 634                 tcsr: syscon@1a400000 {
 635                         compatible = "qcom,tcsr-ipq8064", "syscon";
 636                         reg = <0x1a400000 0x100>;
 637                 };
 638
 639                 lcc: clock-controller@28000000 {
 640                         compatible = "qcom,lcc-ipq8064";
 641                         reg = <0x28000000 0x1000>;
 642                         #clock-cells = <1>;
 643                         #reset-cells = <1>;
 644                 };
 645
 646                 sfpb_mutex_block: syscon@1200600 {
 647                         compatible = "syscon";
 648                         reg = <0x01200600 0x100>;
 649                 };
 650
 651                 hs_phy_1: phy@100f8800 {
 652                         compatible = "qcom,dwc3-hs-usb-phy";
 653                         reg = <0x100f8800 0x30>;
 654                         clocks = <&gcc USB30_1_UTMI_CLK>;
 655                         clock-names = "ref";
 656                         #phy-cells = <0>;
 657
 658                         status = "disabled";
 659                 };
 660
 661                 ss_phy_1: phy@100f8830 {
 662                         compatible = "qcom,dwc3-ss-usb-phy";
 663                         reg = <0x100f8830 0x30>;
 664                         clocks = <&gcc USB30_1_MASTER_CLK>;
 665                         clock-names = "ref";
 666                         #phy-cells = <0>;
 667
 668                         status = "disabled";
 669                 };
 670
 671                 hs_phy_0: phy@110f8800 {
 672                         compatible = "qcom,dwc3-hs-usb-phy";
 673                         reg = <0x110f8800 0x30>;
 674                         clocks = <&gcc USB30_0_UTMI_CLK>;
 675                         clock-names = "ref";
 676                         #phy-cells = <0>;
 677
 678                         status = "disabled";
 679                 };
 680
 681                 ss_phy_0: phy@110f8830 {
 682                         compatible = "qcom,dwc3-ss-usb-phy";
 683                         reg = <0x110f8830 0x30>;
 684                         clocks = <&gcc USB30_0_MASTER_CLK>;
 685                         clock-names = "ref";
 686                         #phy-cells = <0>;
 687
 688                         status = "disabled";
 689                 };
 690
 691                 usb3_0: usb30@0 {
 692                         compatible = "qcom,dwc3";
 693                         #address-cells = <1>;
 694                         #size-cells = <1>;
 695                         clocks = <&gcc USB30_0_MASTER_CLK>;
 696                         clock-names = "core";
 697
 698                         syscon-tcsr = <&tcsr 0xb0 1>;
 699
 700                         ranges;
 701
 702                         status = "disabled";
 703
 704                         dwc3@11000000 {
 705                                 compatible = "snps,dwc3";
 706                                 reg = <0x11000000 0xcd00>;
 707                                 interrupts = <0 110 0x4>;
 708                                 phys = <&hs_phy_0>, <&ss_phy_0>;
 709                                 phy-names = "usb2-phy", "usb3-phy";
 710                                 dr_mode = "host";
 711                                 snps,dis_u3_susphy_quirk;
 712                         };
 713                 };
 714
 715                 usb3_1: usb30@1 {
 716                         compatible = "qcom,dwc3";
 717                         #address-cells = <1>;
 718                         #size-cells = <1>;
 719                         clocks = <&gcc USB30_1_MASTER_CLK>;
 720                         clock-names = "core";
 721
 722                         syscon-tcsr = <&tcsr 0xb0 0>;
 723
 724                         ranges;
 725
 726                         status = "disabled";
 727
 728                         dwc3@10000000 {
 729                                 compatible = "snps,dwc3";
 730                                 reg = <0x10000000 0xcd00>;
 731                                 interrupts = <0 205 0x4>;
 732                                 phys = <&hs_phy_1>, <&ss_phy_1>;
 733                                 phy-names = "usb2-phy", "usb3-phy";
 734                                 dr_mode = "host";
 735                                 snps,dis_u3_susphy_quirk;
 736                         };
 737                 };
 738
 739                 pcie0: pci@1b500000 {
 740                         compatible = "qcom,pcie-ipq8064";
 741                         reg = <0x1b500000 0x1000
 742                                0x1b502000 0x80
 743                                0x1b600000 0x100
 744                                0x0ff00000 0x100000>;
 745                         reg-names = "dbi", "elbi", "parf", "config";
 746                         device_type = "pci";
 747                         linux,pci-domain = <0>;
 748                         bus-range = <0x00 0xff>;
 749                         num-lanes = <1>;
 750                         #address-cells = <3>;
 751                         #size-cells = <2>;
 752
 753                         ranges = <0x81000000 0 0x0fe00000 0x0fe00000 0 0x00100000   /* downstream I/O */
 754                                   0x82000000 0 0x08000000 0x08000000 0 0x07e00000>; /* non-prefetchable memory */
 755
 756                         interrupts = <GIC_SPI 35 IRQ_TYPE_NONE>;
 757                         interrupt-names = "msi";
 758                         #interrupt-cells = <1>;
 759                         interrupt-map-mask = <0 0 0 0x7>;
 760                         interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
 761                                         <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
 762                                         <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
 763                                         <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
 764
 765                         clocks = <&gcc PCIE_A_CLK>,
 766                                  <&gcc PCIE_H_CLK>,
 767                                  <&gcc PCIE_PHY_CLK>,
 768                                  <&gcc PCIE_AUX_CLK>,
 769                                  <&gcc PCIE_ALT_REF_CLK>;
 770                         clock-names = "core", "iface", "phy", "aux", "ref";
 771
 772                         assigned-clocks = <&gcc PCIE_ALT_REF_CLK>;
 773                         assigned-clock-rates = <100000000>;
 774
 775                         resets = <&gcc PCIE_ACLK_RESET>,
 776                                  <&gcc PCIE_HCLK_RESET>,
 777                                  <&gcc PCIE_POR_RESET>,
 778                                  <&gcc PCIE_PCI_RESET>,
 779                                  <&gcc PCIE_PHY_RESET>,
 780                                  <&gcc PCIE_EXT_RESET>;
 781                         reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
 782
 783                         pinctrl-0 = <&pcie0_pins>;
 784                         pinctrl-names = "default";
 785
 786                         perst-gpios = <&qcom_pinmux 3 GPIO_ACTIVE_LOW>;
 787
 788                         status = "disabled";
 789                 };
 790
 791                 pcie1: pci@1b700000 {
 792                         compatible = "qcom,pcie-ipq8064";
 793                         reg = <0x1b700000 0x1000
 794                                0x1b702000 0x80
 795                                0x1b800000 0x100
 796                                0x31f00000 0x100000>;
 797                         reg-names = "dbi", "elbi", "parf", "config";
 798                         device_type = "pci";
 799                         linux,pci-domain = <1>;
 800                         bus-range = <0x00 0xff>;
 801                         num-lanes = <1>;
 802                         #address-cells = <3>;
 803                         #size-cells = <2>;
 804
 805                         ranges = <0x81000000 0 0x31e00000 0x31e00000 0 0x00100000   /* downstream I/O */
 806                                   0x82000000 0 0x2e000000 0x2e000000 0 0x03e00000>; /* non-prefetchable memory */
 807
 808                         interrupts = <GIC_SPI 57 IRQ_TYPE_NONE>;
 809                         interrupt-names = "msi";
 810                         #interrupt-cells = <1>;
 811                         interrupt-map-mask = <0 0 0 0x7>;
 812                         interrupt-map = <0 0 0 1 &intc 0 58 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
 813                                         <0 0 0 2 &intc 0 59 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
 814                                         <0 0 0 3 &intc 0 60 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
 815                                         <0 0 0 4 &intc 0 61 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
 816
 817                         clocks = <&gcc PCIE_1_A_CLK>,
 818                                  <&gcc PCIE_1_H_CLK>,
 819                                  <&gcc PCIE_1_PHY_CLK>,
 820                                  <&gcc PCIE_1_AUX_CLK>,
 821                                  <&gcc PCIE_1_ALT_REF_CLK>;
 822                         clock-names = "core", "iface", "phy", "aux", "ref";
 823
 824                         assigned-clocks = <&gcc PCIE_1_ALT_REF_CLK>;
 825                         assigned-clock-rates = <100000000>;
 826
 827                         resets = <&gcc PCIE_1_ACLK_RESET>,
 828                                  <&gcc PCIE_1_HCLK_RESET>,
 829                                  <&gcc PCIE_1_POR_RESET>,
 830                                  <&gcc PCIE_1_PCI_RESET>,
 831                                  <&gcc PCIE_1_PHY_RESET>,
 832                                  <&gcc PCIE_1_EXT_RESET>;
 833                         reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
 834
 835                         pinctrl-0 = <&pcie1_pins>;
 836                         pinctrl-names = "default";
 837
 838                         perst-gpios = <&qcom_pinmux 48 GPIO_ACTIVE_LOW>;
 839
 840                         status = "disabled";
 841                 };
 842
 843                 pcie2: pci@1b900000 {
 844                         compatible = "qcom,pcie-ipq8064";
 845                         reg = <0x1b900000 0x1000
 846                                0x1b902000 0x80
 847                                0x1ba00000 0x100
 848                                0x35f00000 0x100000>;
 849                         reg-names = "dbi", "elbi", "parf", "config";
 850                         device_type = "pci";
 851                         linux,pci-domain = <2>;
 852                         bus-range = <0x00 0xff>;
 853                         num-lanes = <1>;
 854                         #address-cells = <3>;
 855                         #size-cells = <2>;
 856
 857                         ranges = <0x81000000 0 0x35e00000 0x35e00000 0 0x00100000   /* downstream I/O */
 858                                   0x82000000 0 0x32000000 0x32000000 0 0x03e00000>; /* non-prefetchable memory */
 859
 860                         interrupts = <GIC_SPI 71 IRQ_TYPE_NONE>;
 861                         interrupt-names = "msi";
 862                         #interrupt-cells = <1>;
 863                         interrupt-map-mask = <0 0 0 0x7>;
 864                         interrupt-map = <0 0 0 1 &intc 0 72 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
 865                                         <0 0 0 2 &intc 0 73 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
 866                                         <0 0 0 3 &intc 0 74 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
 867                                         <0 0 0 4 &intc 0 75 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
 868
 869                         clocks = <&gcc PCIE_2_A_CLK>,
 870                                  <&gcc PCIE_2_H_CLK>,
 871                                  <&gcc PCIE_2_PHY_CLK>,
 872                                  <&gcc PCIE_2_AUX_CLK>,
 873                                  <&gcc PCIE_2_ALT_REF_CLK>;
 874                         clock-names = "core", "iface", "phy", "aux", "ref";
 875
 876                         assigned-clocks = <&gcc PCIE_2_ALT_REF_CLK>;
 877                         assigned-clock-rates = <100000000>;
 878
 879                         resets = <&gcc PCIE_2_ACLK_RESET>,
 880                                  <&gcc PCIE_2_HCLK_RESET>,
 881                                  <&gcc PCIE_2_POR_RESET>,
 882                                  <&gcc PCIE_2_PCI_RESET>,
 883                                  <&gcc PCIE_2_PHY_RESET>,
 884                                  <&gcc PCIE_2_EXT_RESET>;
 885                         reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
 886
 887                         pinctrl-0 = <&pcie2_pins>;
 888                         pinctrl-names = "default";
 889
 890                         perst-gpios = <&qcom_pinmux 63 GPIO_ACTIVE_LOW>;
 891
 892                         status = "disabled";
 893                 };
 894
 895                 adm_dma: dma@18300000 {
 896                         compatible = "qcom,adm";
 897                         reg = <0x18300000 0x100000>;
 898                         interrupts = <0 170 0>;
 899                         #dma-cells = <1>;
 900
 901                         clocks = <&gcc ADM0_CLK>, <&gcc ADM0_PBUS_CLK>;
 902                         clock-names = "core", "iface";
 903
 904                         resets = <&gcc ADM0_RESET>,
 905                                  <&gcc ADM0_PBUS_RESET>,
 906                                  <&gcc ADM0_C0_RESET>,
 907                                  <&gcc ADM0_C1_RESET>,
 908                                  <&gcc ADM0_C2_RESET>;
 909                         reset-names = "clk", "pbus", "c0", "c1", "c2";
 910                         qcom,ee = <0>;
 911
 912                         status = "disabled";
 913                 };
 914
 915                 nand@1ac00000 {
 916                         compatible = "qcom,ipq806x-nand";
 917                         reg = <0x1ac00000 0x800>;
 918
 919                         clocks = <&gcc EBI2_CLK>,
 920                                  <&gcc EBI2_AON_CLK>;
 921                         clock-names = "core", "aon";
 922
 923                         dmas = <&adm_dma 3>;
 924                         dma-names = "rxtx";
 925                         qcom,cmd-crci = <15>;
 926                         qcom,data-crci = <3>;
 927
 928                         status = "disabled";
 929
 930                         #address-cells = <1>;
 931                         #size-cells = <0>;
 932                 };
 933
 934                 nss_common: syscon@03000000 {
 935                         compatible = "syscon";
 936                         reg = <0x03000000 0x0000FFFF>;
 937                 };
 938
 939                 qsgmii_csr: syscon@1bb00000 {
 940                         compatible = "syscon";
 941                         reg = <0x1bb00000 0x000001FF>;
 942                 };
 943
 944                 stmmac_axi_setup: stmmac-axi-config {
 945                         snps,wr_osr_lmt = <7>;
 946                         snps,rd_osr_lmt = <7>;
 947                         snps,blen = <16 0 0 0 0 0 0>;
 948                 };
 949
 950                 gmac0: ethernet@37000000 {
 951                         device_type = "network";
 952                         compatible = "qcom,ipq806x-gmac";
 953                         reg = <0x37000000 0x200000>;
 954                         interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
 955                         interrupt-names = "macirq";
 956
 957                         snps,axi-config = <&stmmac_axi_setup>;
 958                         snps,pbl = <32>;
 959                         snps,aal = <1>;
 960
 961                         qcom,nss-common = <&nss_common>;
 962                         qcom,qsgmii-csr = <&qsgmii_csr>;
 963
 964                         clocks = <&gcc GMAC_CORE1_CLK>;
 965                         clock-names = "stmmaceth";
 966
 967                         resets = <&gcc GMAC_CORE1_RESET>;
 968                         reset-names = "stmmaceth";
 969
 970                         status = "disabled";
 971                 };
 972
 973                 gmac1: ethernet@37200000 {
 974                         device_type = "network";
 975                         compatible = "qcom,ipq806x-gmac";
 976                         reg = <0x37200000 0x200000>;
 977                         interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
 978                         interrupt-names = "macirq";
 979
 980                         snps,axi-config = <&stmmac_axi_setup>;
 981                         snps,pbl = <32>;
 982                         snps,aal = <1>;
 983
 984                         qcom,nss-common = <&nss_common>;
 985                         qcom,qsgmii-csr = <&qsgmii_csr>;
 986
 987                         clocks = <&gcc GMAC_CORE2_CLK>;
 988                         clock-names = "stmmaceth";
 989
 990                         resets = <&gcc GMAC_CORE2_RESET>;
 991                         reset-names = "stmmaceth";
 992
 993                         status = "disabled";
 994                 };
 995
 996                 gmac2: ethernet@37400000 {
 997                         device_type = "network";
 998                         compatible = "qcom,ipq806x-gmac";
 999                         reg = <0x37400000 0x200000>;
1000                         interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
1001                         interrupt-names = "macirq";
1002
1003                         snps,axi-config = <&stmmac_axi_setup>;
1004                         snps,pbl = <32>;
1005                         snps,aal = <1>;
1006
1007                         qcom,nss-common = <&nss_common>;
1008                         qcom,qsgmii-csr = <&qsgmii_csr>;
1009
1010                         clocks = <&gcc GMAC_CORE3_CLK>;
1011                         clock-names = "stmmaceth";
1012
1013                         resets = <&gcc GMAC_CORE3_RESET>;
1014                         reset-names = "stmmaceth";
1015
1016                         status = "disabled";
1017                 };
1018
1019                 gmac3: ethernet@37600000 {
1020                         device_type = "network";
1021                         compatible = "qcom,ipq806x-gmac";
1022                         reg = <0x37600000 0x200000>;
1023                         interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
1024                         interrupt-names = "macirq";
1025
1026                         snps,axi-config = <&stmmac_axi_setup>;
1027                         snps,pbl = <32>;
1028                         snps,aal = <1>;
1029
1030                         qcom,nss-common = <&nss_common>;
1031                         qcom,qsgmii-csr = <&qsgmii_csr>;
1032
1033                         clocks = <&gcc GMAC_CORE4_CLK>;
1034                         clock-names = "stmmaceth";
1035
1036                         resets = <&gcc GMAC_CORE4_RESET>;
1037                         reset-names = "stmmaceth";
1038
1039                         status = "disabled";
1040                 };
1041         };
1042
1043         sfpb_mutex: sfpb-mutex {
1044                 compatible = "qcom,sfpb-mutex";
1045                 syscon = <&sfpb_mutex_block 4 4>;
1046
1047                 #hwlock-cells = <1>;
1048         };
1049
1050         smem {
1051                 compatible = "qcom,smem";
1052                 memory-region = <&smem>;
1053                 hwlocks = <&sfpb_mutex 3>;
1054         };
1055 };