target/linux/ipq806x/files-4.9/arch/arm/boot/dts/qcom-ipq8064.dtsi

   1 /dts-v1/;
   2
   3 #include "skeleton.dtsi"
   4 #include <dt-bindings/clock/qcom,gcc-ipq806x.h>
   5 #include <dt-bindings/mfd/qcom-rpm.h>
   6 #include <dt-bindings/clock/qcom,rpmcc.h>
   7 #include <dt-bindings/clock/qcom,lcc-ipq806x.h>
   8 #include <dt-bindings/soc/qcom,gsbi.h>
   9 #include <dt-bindings/reset/qcom,gcc-ipq806x.h>
  10 #include <dt-bindings/interrupt-controller/arm-gic.h>
  11 #include <dt-bindings/gpio/gpio.h>
  12
  13 / {
  14         model = "Qualcomm IPQ8064";
  15         compatible = "qcom,ipq8064";
  16         interrupt-parent = <&intc>;
  17
  18         cpus {
  19                 #address-cells = <1>;
  20                 #size-cells = <0>;
  21
  22                 cpu0: cpu@0 {
  23                         compatible = "qcom,krait";
  24                         enable-method = "qcom,kpss-acc-v1";
  25                         device_type = "cpu";
  26                         reg = <0>;
  27                         next-level-cache = <&L2>;
  28                         qcom,acc = <&acc0>;
  29                         qcom,saw = <&saw0>;
  30                         clocks = <&kraitcc 0>, <&kraitcc 4>;
  31                         clock-names = "cpu", "l2";
  32                         clock-latency = <100000>;
  33                         cpu-supply = <&smb208_s2a>;
  34                         voltage-tolerance = <5>;
  35                         cooling-min-state = <0>;
  36                         cooling-max-state = <10>;
  37                         #cooling-cells = <2>;
  38                         cpu-idle-states = <&CPU_SPC>;
  39                 };
  40
  41                 cpu1: cpu@1 {
  42                         compatible = "qcom,krait";
  43                         enable-method = "qcom,kpss-acc-v1";
  44                         device_type = "cpu";
  45                         reg = <1>;
  46                         next-level-cache = <&L2>;
  47                         qcom,acc = <&acc1>;
  48                         qcom,saw = <&saw1>;
  49                         clocks = <&kraitcc 1>, <&kraitcc 4>;
  50                         clock-names = "cpu", "l2";
  51                         clock-latency = <100000>;
  52                         cpu-supply = <&smb208_s2b>;
  53                         cooling-min-state = <0>;
  54                         cooling-max-state = <10>;
  55                         #cooling-cells = <2>;
  56                         cpu-idle-states = <&CPU_SPC>;
  57                 };
  58
  59                 L2: l2-cache {
  60                         compatible = "cache";
  61                         cache-level = <2>;
  62                         qcom,saw = <&saw_l2>;
  63                 };
  64
  65                 qcom,l2 {
  66                         qcom,l2-rates = <384000000 1000000000 1200000000>;
  67                 };
  68
  69                 idle-states {
  70                         CPU_SPC: spc {
  71                                 compatible = "qcom,idle-state-spc",
  72                                                 "arm,idle-state";
  73                                 entry-latency-us = <400>;
  74                                 exit-latency-us = <900>;
  75                                 min-residency-us = <3000>;
  76                         };
  77                 };
  78         };
  79
  80         thermal-zones {
  81                 cpu-thermal0 {
  82                         polling-delay-passive = <250>;
  83                         polling-delay = <1000>;
  84
  85                         thermal-sensors = <&gcc 5>;
  86                         coefficients = <1132 0>;
  87
  88                         trips {
  89                                 cpu_alert0: trip0 {
  90                                         temperature = <75000>;
  91                                         hysteresis = <2000>;
  92                                         type = "passive";
  93                                 };
  94                                 cpu_crit0: trip1 {
  95                                         temperature = <110000>;
  96                                         hysteresis = <2000>;
  97                                         type = "critical";
  98                                 };
  99                         };
 100                 };
 101
 102                 cpu-thermal1 {
 103                         polling-delay-passive = <250>;
 104                         polling-delay = <1000>;
 105
 106                         thermal-sensors = <&gcc 6>;
 107                         coefficients = <1132 0>;
 108
 109                         trips {
 110                                 cpu_alert1: trip0 {
 111                                         temperature = <75000>;
 112                                         hysteresis = <2000>;
 113                                         type = "passive";
 114                                 };
 115                                 cpu_crit1: trip1 {
 116                                         temperature = <110000>;
 117                                         hysteresis = <2000>;
 118                                         type = "critical";
 119                                 };
 120                         };
 121                 };
 122
 123                 cpu-thermal2 {
 124                         polling-delay-passive = <250>;
 125                         polling-delay = <1000>;
 126
 127                         thermal-sensors = <&gcc 7>;
 128                         coefficients = <1199 0>;
 129
 130                         trips {
 131                                 cpu_alert2: trip0 {
 132                                         temperature = <75000>;
 133                                         hysteresis = <2000>;
 134                                         type = "passive";
 135                                 };
 136                                 cpu_crit2: trip1 {
 137                                         temperature = <110000>;
 138                                         hysteresis = <2000>;
 139                                         type = "critical";
 140                                 };
 141                         };
 142                 };
 143
 144                 cpu-thermal3 {
 145                         polling-delay-passive = <250>;
 146                         polling-delay = <1000>;
 147
 148                         thermal-sensors = <&gcc 8>;
 149                         coefficients = <1132 0>;
 150
 151                         trips {
 152                                 cpu_alert3: trip0 {
 153                                         temperature = <75000>;
 154                                         hysteresis = <2000>;
 155                                         type = "passive";
 156                                 };
 157                                 cpu_crit3: trip1 {
 158                                         temperature = <110000>;
 159                                         hysteresis = <2000>;
 160                                         type = "critical";
 161                                 };
 162                         };
 163                 };
 164         };
 165
 166         cpu-pmu {
 167                 compatible = "qcom,krait-pmu";
 168                 interrupts = <1 10 0x304>;
 169         };
 170
 171         reserved-memory {
 172                 #address-cells = <1>;
 173                 #size-cells = <1>;
 174                 ranges;
 175
 176                 nss@40000000 {
 177                         reg = <0x40000000 0x1000000>;
 178                         no-map;
 179                 };
 180
 181                 smem: smem@41000000 {
 182                         reg = <0x41000000 0x200000>;
 183                         no-map;
 184                 };
 185         };
 186
 187         clocks {
 188                 cxo_board {
 189                         compatible = "fixed-clock";
 190                         #clock-cells = <0>;
 191                         clock-frequency = <25000000>;
 192                 };
 193
 194                 pxo_board {
 195                         compatible = "fixed-clock";
 196                         #clock-cells = <0>;
 197                         clock-frequency = <25000000>;
 198                 };
 199
 200                 sleep_clk: sleep_clk {
 201                         compatible = "fixed-clock";
 202                         clock-frequency = <32768>;
 203                         #clock-cells = <0>;
 204                 };
 205         };
 206
 207         firmware {
 208                 scm {
 209                         compatible = "qcom,scm-ipq806x";
 210                 };
 211         };
 212
 213         kraitcc: clock-controller {
 214                 compatible = "qcom,krait-cc-v1";
 215                 #clock-cells = <1>;
 216         };
 217
 218         qcom,pvs {
 219                 qcom,pvs-format-a;
 220                 qcom,speed0-pvs0-bin-v0 =
 221                         < 1400000000 1250000 >,
 222                         < 1200000000 1200000 >,
 223                         < 1000000000 1150000 >,
 224                          < 800000000 1100000 >,
 225                          < 600000000 1050000 >,
 226                          < 384000000 1000000 >;
 227
 228                 qcom,speed0-pvs1-bin-v0 =
 229                         < 1400000000 1175000 >,
 230                         < 1200000000 1125000 >,
 231                         < 1000000000 1075000 >,
 232                          < 800000000 1025000 >,
 233                          < 600000000  975000 >,
 234                          < 384000000  925000 >;
 235
 236                 qcom,speed0-pvs2-bin-v0 =
 237                         < 1400000000 1125000 >,
 238                         < 1200000000 1075000 >,
 239                         < 1000000000 1025000 >,
 240                          < 800000000  995000 >,
 241                          < 600000000  925000 >,
 242                          < 384000000  875000 >;
 243
 244                 qcom,speed0-pvs3-bin-v0 =
 245                         < 1400000000 1050000 >,
 246                         < 1200000000 1000000 >,
 247                         < 1000000000  950000 >,
 248                          < 800000000  900000 >,
 249                          < 600000000  850000 >,
 250                          < 384000000  800000 >;
 251         };
 252
 253         soc: soc {
 254                 #address-cells = <1>;
 255                 #size-cells = <1>;
 256                 ranges;
 257                 compatible = "simple-bus";
 258
 259                 lpass@28100000 {
 260                         compatible = "qcom,lpass-cpu";
 261                         status = "disabled";
 262                         clocks = <&lcc AHBIX_CLK>,
 263                                         <&lcc MI2S_OSR_CLK>,
 264                                         <&lcc MI2S_BIT_CLK>;
 265                         clock-names = "ahbix-clk",
 266                                         "mi2s-osr-clk",
 267                                         "mi2s-bit-clk";
 268                         interrupts = <0 85 1>;
 269                         interrupt-names = "lpass-irq-lpaif";
 270                         reg = <0x28100000 0x10000>;
 271                         reg-names = "lpass-lpaif";
 272                 };
 273
 274                 qfprom: qfprom@700000 {
 275                         compatible = "qcom,qfprom", "syscon";
 276                         reg = <0x00700000 0x1000>;
 277                         #address-cells = <1>;
 278                         #size-cells = <1>;
 279                         ranges;
 280
 281                         tsens_calib: calib {
 282                                 reg = <0x400 0x10>;
 283                         };
 284                         tsens_backup: backup_calib {
 285                                 reg = <0x410 0x10>;
 286                         };
 287                 };
 288
 289                 rpm@108000 {
 290                         compatible = "qcom,rpm-ipq8064";
 291                         reg = <0x108000 0x1000>;
 292                         qcom,ipc = <&l2cc 0x8 2>;
 293
 294                         interrupts = <0 19 0>,
 295                                      <0 21 0>,
 296                                      <0 22 0>;
 297                         interrupt-names = "ack",
 298                                           "err",
 299                                           "wakeup";
 300
 301                         clocks = <&gcc RPM_MSG_RAM_H_CLK>;
 302                         clock-names = "ram";
 303
 304                         #address-cells = <1>;
 305                         #size-cells = <0>;
 306
 307                         rpmcc: clock-controller {
 308                                 compatible      = "qcom,rpmcc-ipq806x", "qcom,rpmcc";
 309                                 #clock-cells = <1>;
 310                         };
 311
 312                         regulators {
 313                                 compatible = "qcom,rpm-smb208-regulators";
 314
 315                                 smb208_s1a: s1a {
 316                                         regulator-min-microvolt = <1050000>;
 317                                         regulator-max-microvolt = <1150000>;
 318
 319                                         qcom,switch-mode-frequency = <1200000>;
 320
 321                                 };
 322
 323                                 smb208_s1b: s1b {
 324                                         regulator-min-microvolt = <1050000>;
 325                                         regulator-max-microvolt = <1150000>;
 326
 327                                         qcom,switch-mode-frequency = <1200000>;
 328                                 };
 329
 330                                 smb208_s2a: s2a {
 331                                         regulator-min-microvolt = < 800000>;
 332                                         regulator-max-microvolt = <1250000>;
 333
 334                                         qcom,switch-mode-frequency = <1200000>;
 335                                 };
 336
 337                                 smb208_s2b: s2b {
 338                                         regulator-min-microvolt = < 800000>;
 339                                         regulator-max-microvolt = <1250000>;
 340
 341                                         qcom,switch-mode-frequency = <1200000>;
 342                                 };
 343                         };
 344                 };
 345
 346                 rng@1a500000 {
 347                         compatible = "qcom,prng";
 348                         reg = <0x1a500000 0x200>;
 349                         clocks = <&gcc PRNG_CLK>;
 350                         clock-names = "core";
 351                 };
 352
 353                 qcom_pinmux: pinmux@800000 {
 354                         compatible = "qcom,ipq8064-pinctrl";
 355                         reg = <0x800000 0x4000>;
 356
 357                         gpio-controller;
 358                         #gpio-cells = <2>;
 359                         interrupt-controller;
 360                         #interrupt-cells = <2>;
 361                         interrupts = <0 16 0x4>;
 362
 363                         pcie0_pins: pcie0_pinmux {
 364                                 mux {
 365                                         pins = "gpio3";
 366                                         function = "pcie1_rst";
 367                                         drive-strength = <2>;
 368                                         bias-disable;
 369                                 };
 370                         };
 371
 372                         pcie1_pins: pcie1_pinmux {
 373                                 mux {
 374                                         pins = "gpio48";
 375                                         function = "pcie2_rst";
 376                                         drive-strength = <2>;
 377                                         bias-disable;
 378                                 };
 379                         };
 380
 381                         pcie2_pins: pcie2_pinmux {
 382                                 mux {
 383                                         pins = "gpio63";
 384                                         function = "pcie3_rst";
 385                                         drive-strength = <2>;
 386                                         bias-disable;
 387                                         output-low;
 388                                 };
 389                         };
 390                 };
 391
 392                 intc: interrupt-controller@2000000 {
 393                         compatible = "qcom,msm-qgic2";
 394                         interrupt-controller;
 395                         #interrupt-cells = <3>;
 396                         reg = <0x02000000 0x1000>,
 397                               <0x02002000 0x1000>;
 398                 };
 399
 400                 timer@200a000 {
 401                         compatible = "qcom,kpss-timer", "qcom,msm-timer";
 402                         interrupts = <1 1 0x301>,
 403                                      <1 2 0x301>,
 404                                      <1 3 0x301>,
 405                                      <1 4 0x301>,
 406                                      <1 5 0x301>;
 407                         reg = <0x0200a000 0x100>;
 408                         clock-frequency = <25000000>,
 409                                           <32768>;
 410                         clocks = <&sleep_clk>;
 411                         clock-names = "sleep";
 412                         cpu-offset = <0x80000>;
 413                 };
 414
 415                 acc0: clock-controller@2088000 {
 416                         compatible = "qcom,kpss-acc-v1";
 417                         reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
 418                         clock-output-names = "acpu0_aux";
 419                 };
 420
 421                 acc1: clock-controller@2098000 {
 422                         compatible = "qcom,kpss-acc-v1";
 423                         reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
 424                         clock-output-names = "acpu1_aux";
 425                 };
 426
 427                 l2cc: clock-controller@2011000 {
 428                         compatible = "qcom,kpss-gcc", "syscon";
 429                         reg = <0x2011000 0x1000>;
 430                         clock-output-names = "acpu_l2_aux";
 431                 };
 432
 433                 saw0: regulator@2089000 {
 434                         compatible = "qcom,saw2", "syscon";
 435                         reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
 436                         regulator;
 437                 };
 438
 439                 saw1: regulator@2099000 {
 440                         compatible = "qcom,saw2", "syscon";
 441                         reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
 442                         regulator;
 443                 };
 444
 445                 saw_l2: regulator@02012000 {
 446                         compatible = "qcom,saw2", "syscon";
 447                         reg = <0x02012000 0x1000>;
 448                         regulator;
 449                 };
 450
 451                 sic_non_secure: sic-non-secure@12100000 {
 452                         compatible = "syscon";
 453                         reg = <0x12100000 0x10000>;
 454                 };
 455
 456                 gsbi2: gsbi@12480000 {
 457                         compatible = "qcom,gsbi-v1.0.0";
 458                         cell-index = <2>;
 459                         reg = <0x12480000 0x100>;
 460                         clocks = <&gcc GSBI2_H_CLK>;
 461                         clock-names = "iface";
 462                         #address-cells = <1>;
 463                         #size-cells = <1>;
 464                         ranges;
 465                         status = "disabled";
 466
 467                         syscon-tcsr = <&tcsr>;
 468
 469                         uart2: serial@12490000 {
 470                                 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
 471                                 reg = <0x12490000 0x1000>,
 472                                       <0x12480000 0x1000>;
 473                                 interrupts = <0 195 0x0>;
 474                                 clocks = <&gcc GSBI2_UART_CLK>, <&gcc GSBI2_H_CLK>;
 475                                 clock-names = "core", "iface";
 476                                 status = "disabled";
 477                         };
 478
 479                         i2c@124a0000 {
 480                                 compatible = "qcom,i2c-qup-v1.1.1";
 481                                 reg = <0x124a0000 0x1000>;
 482                                 interrupts = <0 196 0>;
 483
 484                                 clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
 485                                 clock-names = "core", "iface";
 486                                 status = "disabled";
 487
 488                                 #address-cells = <1>;
 489                                 #size-cells = <0>;
 490                         };
 491
 492                 };
 493
 494                 gsbi4: gsbi@16300000 {
 495                         compatible = "qcom,gsbi-v1.0.0";
 496                         cell-index = <4>;
 497                         reg = <0x16300000 0x100>;
 498                         clocks = <&gcc GSBI4_H_CLK>;
 499                         clock-names = "iface";
 500                         #address-cells = <1>;
 501                         #size-cells = <1>;
 502                         ranges;
 503                         status = "disabled";
 504
 505                         syscon-tcsr = <&tcsr>;
 506
 507                         gsbi4_serial: serial@16340000 {
 508                                 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
 509                                 reg = <0x16340000 0x1000>,
 510                                       <0x16300000 0x1000>;
 511                                 interrupts = <0 152 0x0>;
 512                                 clocks = <&gcc GSBI4_UART_CLK>, <&gcc GSBI4_H_CLK>;
 513                                 clock-names = "core", "iface";
 514                                 status = "disabled";
 515                         };
 516
 517                         i2c@16380000 {
 518                                 compatible = "qcom,i2c-qup-v1.1.1";
 519                                 reg = <0x16380000 0x1000>;
 520                                 interrupts = <0 153 0>;
 521
 522                                 clocks = <&gcc GSBI4_QUP_CLK>, <&gcc GSBI4_H_CLK>;
 523                                 clock-names = "core", "iface";
 524                                 status = "disabled";
 525
 526                                 #address-cells = <1>;
 527                                 #size-cells = <0>;
 528                         };
 529                 };
 530
 531                 gsbi5: gsbi@1a200000 {
 532                         compatible = "qcom,gsbi-v1.0.0";
 533                         cell-index = <5>;
 534                         reg = <0x1a200000 0x100>;
 535                         clocks = <&gcc GSBI5_H_CLK>;
 536                         clock-names = "iface";
 537                         #address-cells = <1>;
 538                         #size-cells = <1>;
 539                         ranges;
 540                         status = "disabled";
 541
 542                         syscon-tcsr = <&tcsr>;
 543
 544                         uart5: serial@1a240000 {
 545                                 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
 546                                 reg = <0x1a240000 0x1000>,
 547                                       <0x1a200000 0x1000>;
 548                                 interrupts = <0 154 0x0>;
 549                                 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
 550                                 clock-names = "core", "iface";
 551                                 status = "disabled";
 552                         };
 553
 554                         i2c@1a280000 {
 555                                 compatible = "qcom,i2c-qup-v1.1.1";
 556                                 reg = <0x1a280000 0x1000>;
 557                                 interrupts = <0 155 0>;
 558
 559                                 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
 560                                 clock-names = "core", "iface";
 561                                 status = "disabled";
 562
 563                                 #address-cells = <1>;
 564                                 #size-cells = <0>;
 565                         };
 566
 567                         spi@1a280000 {
 568                                 compatible = "qcom,spi-qup-v1.1.1";
 569                                 reg = <0x1a280000 0x1000>;
 570                                 interrupts = <0 155 0>;
 571
 572                                 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
 573                                 clock-names = "core", "iface";
 574                                 status = "disabled";
 575
 576                                 #address-cells = <1>;
 577                                 #size-cells = <0>;
 578                         };
 579                 };
 580
 581                 sata_phy: sata-phy@1b400000 {
 582                         compatible = "qcom,ipq806x-sata-phy";
 583                         reg = <0x1b400000 0x200>;
 584
 585                         clocks = <&gcc SATA_PHY_CFG_CLK>;
 586                         clock-names = "cfg";
 587
 588                         #phy-cells = <0>;
 589                         status = "disabled";
 590                 };
 591
 592                 sata@29000000 {
 593                         compatible = "qcom,ipq806x-ahci", "generic-ahci";
 594                         reg = <0x29000000 0x180>;
 595
 596                         interrupts = <0 209 0x0>;
 597
 598                         clocks = <&gcc SFAB_SATA_S_H_CLK>,
 599                                  <&gcc SATA_H_CLK>,
 600                                  <&gcc SATA_A_CLK>,
 601                                  <&gcc SATA_RXOOB_CLK>,
 602                                  <&gcc SATA_PMALIVE_CLK>;
 603                         clock-names = "slave_face", "iface", "core",
 604                                         "rxoob", "pmalive";
 605
 606                         assigned-clocks = <&gcc SATA_RXOOB_CLK>, <&gcc SATA_PMALIVE_CLK>;
 607                         assigned-clock-rates = <100000000>, <100000000>;
 608
 609                         phys = <&sata_phy>;
 610                         phy-names = "sata-phy";
 611                         status = "disabled";
 612                 };
 613
 614                 qcom,ssbi@500000 {
 615                         compatible = "qcom,ssbi";
 616                         reg = <0x00500000 0x1000>;
 617                         qcom,controller-type = "pmic-arbiter";
 618                 };
 619
 620                 gcc: clock-controller@900000 {
 621                         compatible = "qcom,gcc-ipq8064";
 622                         reg = <0x00900000 0x4000>;
 623                         nvmem-cells = <&tsens_calib>, <&tsens_backup>;
 624                         nvmem-cell-names = "calib", "calib_backup";
 625                         #clock-cells = <1>;
 626                         #reset-cells = <1>;
 627                         #power-domain-cells = <1>;
 628                         #thermal-sensor-cells = <1>;
 629                 };
 630
 631                 tcsr: syscon@1a400000 {
 632                         compatible = "qcom,tcsr-ipq8064", "syscon";
 633                         reg = <0x1a400000 0x100>;
 634                 };
 635
 636                 lcc: clock-controller@28000000 {
 637                         compatible = "qcom,lcc-ipq8064";
 638                         reg = <0x28000000 0x1000>;
 639                         #clock-cells = <1>;
 640                         #reset-cells = <1>;
 641                 };
 642
 643                 sfpb_mutex_block: syscon@1200600 {
 644                         compatible = "syscon";
 645                         reg = <0x01200600 0x100>;
 646                 };
 647
 648                 hs_phy_1: phy@100f8800 {
 649                         compatible = "qcom,dwc3-hs-usb-phy";
 650                         reg = <0x100f8800 0x30>;
 651                         clocks = <&gcc USB30_1_UTMI_CLK>;
 652                         clock-names = "ref";
 653                         #phy-cells = <0>;
 654
 655                         status = "disabled";
 656                 };
 657
 658                 ss_phy_1: phy@100f8830 {
 659                         compatible = "qcom,dwc3-ss-usb-phy";
 660                         reg = <0x100f8830 0x30>;
 661                         clocks = <&gcc USB30_1_MASTER_CLK>;
 662                         clock-names = "ref";
 663                         #phy-cells = <0>;
 664
 665                         status = "disabled";
 666                 };
 667
 668                 hs_phy_0: phy@110f8800 {
 669                         compatible = "qcom,dwc3-hs-usb-phy";
 670                         reg = <0x110f8800 0x30>;
 671                         clocks = <&gcc USB30_0_UTMI_CLK>;
 672                         clock-names = "ref";
 673                         #phy-cells = <0>;
 674
 675                         status = "disabled";
 676                 };
 677
 678                 ss_phy_0: phy@110f8830 {
 679                         compatible = "qcom,dwc3-ss-usb-phy";
 680                         reg = <0x110f8830 0x30>;
 681                         clocks = <&gcc USB30_0_MASTER_CLK>;
 682                         clock-names = "ref";
 683                         #phy-cells = <0>;
 684
 685                         status = "disabled";
 686                 };
 687
 688                 usb3_0: usb30@0 {
 689                         compatible = "qcom,dwc3";
 690                         #address-cells = <1>;
 691                         #size-cells = <1>;
 692                         clocks = <&gcc USB30_0_MASTER_CLK>;
 693                         clock-names = "core";
 694
 695                         syscon-tcsr = <&tcsr 0xb0 1>;
 696
 697                         ranges;
 698
 699                         status = "disabled";
 700
 701                         dwc3@11000000 {
 702                                 compatible = "snps,dwc3";
 703                                 reg = <0x11000000 0xcd00>;
 704                                 interrupts = <0 110 0x4>;
 705                                 phys = <&hs_phy_0>, <&ss_phy_0>;
 706                                 phy-names = "usb2-phy", "usb3-phy";
 707                                 dr_mode = "host";
 708                                 snps,dis_u3_susphy_quirk;
 709                         };
 710                 };
 711
 712                 usb3_1: usb30@1 {
 713                         compatible = "qcom,dwc3";
 714                         #address-cells = <1>;
 715                         #size-cells = <1>;
 716                         clocks = <&gcc USB30_1_MASTER_CLK>;
 717                         clock-names = "core";
 718
 719                         syscon-tcsr = <&tcsr 0xb0 0>;
 720
 721                         ranges;
 722
 723                         status = "disabled";
 724
 725                         dwc3@10000000 {
 726                                 compatible = "snps,dwc3";
 727                                 reg = <0x10000000 0xcd00>;
 728                                 interrupts = <0 205 0x4>;
 729                                 phys = <&hs_phy_1>, <&ss_phy_1>;
 730                                 phy-names = "usb2-phy", "usb3-phy";
 731                                 dr_mode = "host";
 732                                 snps,dis_u3_susphy_quirk;
 733                         };
 734                 };
 735
 736                 pcie0: pci@1b500000 {
 737                         compatible = "qcom,pcie-ipq8064";
 738                         reg = <0x1b500000 0x1000
 739                                0x1b502000 0x80
 740                                0x1b600000 0x100
 741                                0x0ff00000 0x100000>;
 742                         reg-names = "dbi", "elbi", "parf", "config";
 743                         device_type = "pci";
 744                         linux,pci-domain = <0>;
 745                         bus-range = <0x00 0xff>;
 746                         num-lanes = <1>;
 747                         #address-cells = <3>;
 748                         #size-cells = <2>;
 749
 750                         ranges = <0x81000000 0 0x0fe00000 0x0fe00000 0 0x00100000   /* downstream I/O */
 751                                   0x82000000 0 0x08000000 0x08000000 0 0x07e00000>; /* non-prefetchable memory */
 752
 753                         interrupts = <GIC_SPI 35 IRQ_TYPE_NONE>;
 754                         interrupt-names = "msi";
 755                         #interrupt-cells = <1>;
 756                         interrupt-map-mask = <0 0 0 0x7>;
 757                         interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
 758                                         <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
 759                                         <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
 760                                         <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
 761
 762                         clocks = <&gcc PCIE_A_CLK>,
 763                                  <&gcc PCIE_H_CLK>,
 764                                  <&gcc PCIE_PHY_CLK>,
 765                                  <&gcc PCIE_AUX_CLK>,
 766                                  <&gcc PCIE_ALT_REF_CLK>;
 767                         clock-names = "core", "iface", "phy", "aux", "ref";
 768
 769                         assigned-clocks = <&gcc PCIE_ALT_REF_CLK>;
 770                         assigned-clock-rates = <100000000>;
 771
 772                         resets = <&gcc PCIE_ACLK_RESET>,
 773                                  <&gcc PCIE_HCLK_RESET>,
 774                                  <&gcc PCIE_POR_RESET>,
 775                                  <&gcc PCIE_PCI_RESET>,
 776                                  <&gcc PCIE_PHY_RESET>,
 777                                  <&gcc PCIE_EXT_RESET>;
 778                         reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
 779
 780                         pinctrl-0 = <&pcie0_pins>;
 781                         pinctrl-names = "default";
 782
 783                         perst-gpios = <&qcom_pinmux 3 GPIO_ACTIVE_LOW>;
 784
 785                         status = "disabled";
 786                 };
 787
 788                 pcie1: pci@1b700000 {
 789                         compatible = "qcom,pcie-ipq8064";
 790                         reg = <0x1b700000 0x1000
 791                                0x1b702000 0x80
 792                                0x1b800000 0x100
 793                                0x31f00000 0x100000>;
 794                         reg-names = "dbi", "elbi", "parf", "config";
 795                         device_type = "pci";
 796                         linux,pci-domain = <1>;
 797                         bus-range = <0x00 0xff>;
 798                         num-lanes = <1>;
 799                         #address-cells = <3>;
 800                         #size-cells = <2>;
 801
 802                         ranges = <0x81000000 0 0x31e00000 0x31e00000 0 0x00100000   /* downstream I/O */
 803                                   0x82000000 0 0x2e000000 0x2e000000 0 0x03e00000>; /* non-prefetchable memory */
 804
 805                         interrupts = <GIC_SPI 57 IRQ_TYPE_NONE>;
 806                         interrupt-names = "msi";
 807                         #interrupt-cells = <1>;
 808                         interrupt-map-mask = <0 0 0 0x7>;
 809                         interrupt-map = <0 0 0 1 &intc 0 58 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
 810                                         <0 0 0 2 &intc 0 59 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
 811                                         <0 0 0 3 &intc 0 60 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
 812                                         <0 0 0 4 &intc 0 61 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
 813
 814                         clocks = <&gcc PCIE_1_A_CLK>,
 815                                  <&gcc PCIE_1_H_CLK>,
 816                                  <&gcc PCIE_1_PHY_CLK>,
 817                                  <&gcc PCIE_1_AUX_CLK>,
 818                                  <&gcc PCIE_1_ALT_REF_CLK>;
 819                         clock-names = "core", "iface", "phy", "aux", "ref";
 820
 821                         assigned-clocks = <&gcc PCIE_1_ALT_REF_CLK>;
 822                         assigned-clock-rates = <100000000>;
 823
 824                         resets = <&gcc PCIE_1_ACLK_RESET>,
 825                                  <&gcc PCIE_1_HCLK_RESET>,
 826                                  <&gcc PCIE_1_POR_RESET>,
 827                                  <&gcc PCIE_1_PCI_RESET>,
 828                                  <&gcc PCIE_1_PHY_RESET>,
 829                                  <&gcc PCIE_1_EXT_RESET>;
 830                         reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
 831
 832                         pinctrl-0 = <&pcie1_pins>;
 833                         pinctrl-names = "default";
 834
 835                         perst-gpios = <&qcom_pinmux 48 GPIO_ACTIVE_LOW>;
 836
 837                         status = "disabled";
 838                 };
 839
 840                 pcie2: pci@1b900000 {
 841                         compatible = "qcom,pcie-ipq8064";
 842                         reg = <0x1b900000 0x1000
 843                                0x1b902000 0x80
 844                                0x1ba00000 0x100
 845                                0x35f00000 0x100000>;
 846                         reg-names = "dbi", "elbi", "parf", "config";
 847                         device_type = "pci";
 848                         linux,pci-domain = <2>;
 849                         bus-range = <0x00 0xff>;
 850                         num-lanes = <1>;
 851                         #address-cells = <3>;
 852                         #size-cells = <2>;
 853
 854                         ranges = <0x81000000 0 0x35e00000 0x35e00000 0 0x00100000   /* downstream I/O */
 855                                   0x82000000 0 0x32000000 0x32000000 0 0x03e00000>; /* non-prefetchable memory */
 856
 857                         interrupts = <GIC_SPI 71 IRQ_TYPE_NONE>;
 858                         interrupt-names = "msi";
 859                         #interrupt-cells = <1>;
 860                         interrupt-map-mask = <0 0 0 0x7>;
 861                         interrupt-map = <0 0 0 1 &intc 0 72 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
 862                                         <0 0 0 2 &intc 0 73 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
 863                                         <0 0 0 3 &intc 0 74 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
 864                                         <0 0 0 4 &intc 0 75 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
 865
 866                         clocks = <&gcc PCIE_2_A_CLK>,
 867                                  <&gcc PCIE_2_H_CLK>,
 868                                  <&gcc PCIE_2_PHY_CLK>,
 869                                  <&gcc PCIE_2_AUX_CLK>,
 870                                  <&gcc PCIE_2_ALT_REF_CLK>;
 871                         clock-names = "core", "iface", "phy", "aux", "ref";
 872
 873                         assigned-clocks = <&gcc PCIE_2_ALT_REF_CLK>;
 874                         assigned-clock-rates = <100000000>;
 875
 876                         resets = <&gcc PCIE_2_ACLK_RESET>,
 877                                  <&gcc PCIE_2_HCLK_RESET>,
 878                                  <&gcc PCIE_2_POR_RESET>,
 879                                  <&gcc PCIE_2_PCI_RESET>,
 880                                  <&gcc PCIE_2_PHY_RESET>,
 881                                  <&gcc PCIE_2_EXT_RESET>;
 882                         reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
 883
 884                         pinctrl-0 = <&pcie2_pins>;
 885                         pinctrl-names = "default";
 886
 887                         perst-gpios = <&qcom_pinmux 63 GPIO_ACTIVE_LOW>;
 888
 889                         status = "disabled";
 890                 };
 891
 892                 adm_dma: dma@18300000 {
 893                         compatible = "qcom,adm";
 894                         reg = <0x18300000 0x100000>;
 895                         interrupts = <0 170 0>;
 896                         #dma-cells = <1>;
 897
 898                         clocks = <&gcc ADM0_CLK>, <&gcc ADM0_PBUS_CLK>;
 899                         clock-names = "core", "iface";
 900
 901                         resets = <&gcc ADM0_RESET>,
 902                                  <&gcc ADM0_PBUS_RESET>,
 903                                  <&gcc ADM0_C0_RESET>,
 904                                  <&gcc ADM0_C1_RESET>,
 905                                  <&gcc ADM0_C2_RESET>;
 906                         reset-names = "clk", "pbus", "c0", "c1", "c2";
 907                         qcom,ee = <0>;
 908
 909                         status = "disabled";
 910                 };
 911
 912                 nand@1ac00000 {
 913                         compatible = "qcom,ipq806x-nand";
 914                         reg = <0x1ac00000 0x800>;
 915
 916                         clocks = <&gcc EBI2_CLK>,
 917                                  <&gcc EBI2_AON_CLK>;
 918                         clock-names = "core", "aon";
 919
 920                         dmas = <&adm_dma 3>;
 921                         dma-names = "rxtx";
 922                         qcom,cmd-crci = <15>;
 923                         qcom,data-crci = <3>;
 924
 925                         status = "disabled";
 926
 927                         #address-cells = <1>;
 928                         #size-cells = <0>;
 929                 };
 930
 931                 nss_common: syscon@03000000 {
 932                         compatible = "syscon";
 933                         reg = <0x03000000 0x0000FFFF>;
 934                 };
 935
 936                 qsgmii_csr: syscon@1bb00000 {
 937                         compatible = "syscon";
 938                         reg = <0x1bb00000 0x000001FF>;
 939                 };
 940
 941                 stmmac_axi_setup: stmmac-axi-config {
 942                         snps,wr_osr_lmt = <7>;
 943                         snps,rd_osr_lmt = <7>;
 944                         snps,blen = <16 0 0 0 0 0 0>;
 945                 };
 946
 947                 gmac0: ethernet@37000000 {
 948                         device_type = "network";
 949                         compatible = "qcom,ipq806x-gmac";
 950                         reg = <0x37000000 0x200000>;
 951                         interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
 952                         interrupt-names = "macirq";
 953
 954                         snps,axi-config = <&stmmac_axi_setup>;
 955                         snps,pbl = <32>;
 956                         snps,aal = <1>;
 957
 958                         qcom,nss-common = <&nss_common>;
 959                         qcom,qsgmii-csr = <&qsgmii_csr>;
 960
 961                         clocks = <&gcc GMAC_CORE1_CLK>;
 962                         clock-names = "stmmaceth";
 963
 964                         resets = <&gcc GMAC_CORE1_RESET>;
 965                         reset-names = "stmmaceth";
 966
 967                         status = "disabled";
 968                 };
 969
 970                 gmac1: ethernet@37200000 {
 971                         device_type = "network";
 972                         compatible = "qcom,ipq806x-gmac";
 973                         reg = <0x37200000 0x200000>;
 974                         interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
 975                         interrupt-names = "macirq";
 976
 977                         snps,axi-config = <&stmmac_axi_setup>;
 978                         snps,pbl = <32>;
 979                         snps,aal = <1>;
 980
 981                         qcom,nss-common = <&nss_common>;
 982                         qcom,qsgmii-csr = <&qsgmii_csr>;
 983
 984                         clocks = <&gcc GMAC_CORE2_CLK>;
 985                         clock-names = "stmmaceth";
 986
 987                         resets = <&gcc GMAC_CORE2_RESET>;
 988                         reset-names = "stmmaceth";
 989
 990                         status = "disabled";
 991                 };
 992
 993                 gmac2: ethernet@37400000 {
 994                         device_type = "network";
 995                         compatible = "qcom,ipq806x-gmac";
 996                         reg = <0x37400000 0x200000>;
 997                         interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
 998                         interrupt-names = "macirq";
 999
1000                         snps,axi-config = <&stmmac_axi_setup>;
1001                         snps,pbl = <32>;
1002                         snps,aal = <1>;
1003
1004                         qcom,nss-common = <&nss_common>;
1005                         qcom,qsgmii-csr = <&qsgmii_csr>;
1006
1007                         clocks = <&gcc GMAC_CORE3_CLK>;
1008                         clock-names = "stmmaceth";
1009
1010                         resets = <&gcc GMAC_CORE3_RESET>;
1011                         reset-names = "stmmaceth";
1012
1013                         status = "disabled";
1014                 };
1015
1016                 gmac3: ethernet@37600000 {
1017                         device_type = "network";
1018                         compatible = "qcom,ipq806x-gmac";
1019                         reg = <0x37600000 0x200000>;
1020                         interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
1021                         interrupt-names = "macirq";
1022
1023                         snps,axi-config = <&stmmac_axi_setup>;
1024                         snps,pbl = <32>;
1025                         snps,aal = <1>;
1026
1027                         qcom,nss-common = <&nss_common>;
1028                         qcom,qsgmii-csr = <&qsgmii_csr>;
1029
1030                         clocks = <&gcc GMAC_CORE4_CLK>;
1031                         clock-names = "stmmaceth";
1032
1033                         resets = <&gcc GMAC_CORE4_RESET>;
1034                         reset-names = "stmmaceth";
1035
1036                         status = "disabled";
1037                 };
1038         };
1039
1040         sfpb_mutex: sfpb-mutex {
1041                 compatible = "qcom,sfpb-mutex";
1042                 syscon = <&sfpb_mutex_block 4 4>;
1043
1044                 #hwlock-cells = <1>;
1045         };
1046
1047         smem {
1048                 compatible = "qcom,smem";
1049                 memory-region = <&smem>;
1050                 hwlocks = <&sfpb_mutex 3>;
1051         };
1052 };