3 #include "skeleton.dtsi"
4 #include <dt-bindings/clock/qcom,gcc-ipq806x.h>
5 #include <dt-bindings/mfd/qcom-rpm.h>
6 #include <dt-bindings/clock/qcom,rpmcc.h>
7 #include <dt-bindings/clock/qcom,lcc-ipq806x.h>
8 #include <dt-bindings/soc/qcom,gsbi.h>
9 #include <dt-bindings/reset/qcom,gcc-ipq806x.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/gpio/gpio.h>
14 model = "Qualcomm IPQ8064";
15 compatible = "qcom,ipq8064";
16 interrupt-parent = <&intc>;
23 compatible = "qcom,krait";
24 enable-method = "qcom,kpss-acc-v1";
27 next-level-cache = <&L2>;
30 clocks = <&kraitcc 0>, <&kraitcc 4>;
31 clock-names = "cpu", "l2";
32 clock-latency = <100000>;
33 cpu-supply = <&smb208_s2a>;
34 voltage-tolerance = <5>;
35 cooling-min-state = <0>;
36 cooling-max-state = <10>;
38 cpu-idle-states = <&CPU_SPC>;
42 compatible = "qcom,krait";
43 enable-method = "qcom,kpss-acc-v1";
46 next-level-cache = <&L2>;
49 clocks = <&kraitcc 1>, <&kraitcc 4>;
50 clock-names = "cpu", "l2";
51 clock-latency = <100000>;
52 cpu-supply = <&smb208_s2b>;
53 cooling-min-state = <0>;
54 cooling-max-state = <10>;
56 cpu-idle-states = <&CPU_SPC>;
66 qcom,l2-rates = <384000000 1000000000 1200000000>;
71 compatible = "qcom,idle-state-spc",
73 entry-latency-us = <400>;
74 exit-latency-us = <900>;
75 min-residency-us = <3000>;
82 polling-delay-passive = <0>;
84 thermal-sensors = <&tsens 0>;
88 temperature = <125000>;
90 type = "critical_high";
94 temperature = <105000>;
96 type = "configurable_hi";
100 temperature = <95000>;
102 type = "configurable_lo";
108 type = "critical_low";
114 polling-delay-passive = <0>;
116 thermal-sensors = <&tsens 1>;
120 temperature = <125000>;
122 type = "critical_high";
126 temperature = <105000>;
128 type = "configurable_hi";
132 temperature = <95000>;
134 type = "configurable_lo";
140 type = "critical_low";
146 polling-delay-passive = <0>;
148 thermal-sensors = <&tsens 2>;
152 temperature = <125000>;
154 type = "critical_high";
158 temperature = <105000>;
160 type = "configurable_hi";
164 temperature = <95000>;
166 type = "configurable_lo";
172 type = "critical_low";
178 polling-delay-passive = <0>;
180 thermal-sensors = <&tsens 3>;
184 temperature = <125000>;
186 type = "critical_high";
190 temperature = <105000>;
192 type = "configurable_hi";
196 temperature = <95000>;
198 type = "configurable_lo";
204 type = "critical_low";
210 polling-delay-passive = <0>;
212 thermal-sensors = <&tsens 4>;
216 temperature = <125000>;
218 type = "critical_high";
222 temperature = <105000>;
224 type = "configurable_hi";
228 temperature = <95000>;
230 type = "configurable_lo";
236 type = "critical_low";
242 polling-delay-passive = <0>;
244 thermal-sensors = <&tsens 5>;
248 temperature = <125000>;
250 type = "critical_high";
254 temperature = <105000>;
256 type = "configurable_hi";
260 temperature = <95000>;
262 type = "configurable_lo";
268 type = "critical_low";
274 polling-delay-passive = <0>;
276 thermal-sensors = <&tsens 6>;
280 temperature = <125000>;
282 type = "critical_high";
286 temperature = <105000>;
288 type = "configurable_hi";
292 temperature = <95000>;
294 type = "configurable_lo";
300 type = "critical_low";
306 polling-delay-passive = <0>;
308 thermal-sensors = <&tsens 7>;
312 temperature = <125000>;
314 type = "critical_high";
318 temperature = <105000>;
320 type = "configurable_hi";
324 temperature = <95000>;
326 type = "configurable_lo";
332 type = "critical_low";
338 polling-delay-passive = <0>;
340 thermal-sensors = <&tsens 8>;
344 temperature = <125000>;
346 type = "critical_high";
350 temperature = <105000>;
352 type = "configurable_hi";
356 temperature = <95000>;
358 type = "configurable_lo";
364 type = "critical_low";
370 polling-delay-passive = <0>;
372 thermal-sensors = <&tsens 9>;
376 temperature = <125000>;
378 type = "critical_high";
382 temperature = <105000>;
384 type = "configurable_hi";
388 temperature = <95000>;
390 type = "configurable_lo";
396 type = "critical_low";
402 polling-delay-passive = <0>;
404 thermal-sensors = <&tsens 10>;
408 temperature = <125000>;
410 type = "critical_high";
414 temperature = <105000>;
416 type = "configurable_hi";
420 temperature = <95000>;
422 type = "configurable_lo";
428 type = "critical_low";
435 compatible = "qcom,krait-pmu";
436 interrupts = <1 10 0x304>;
440 #address-cells = <1>;
445 reg = <0x40000000 0x1000000>;
449 smem: smem@41000000 {
450 reg = <0x41000000 0x200000>;
457 compatible = "fixed-clock";
459 clock-frequency = <25000000>;
463 compatible = "fixed-clock";
465 clock-frequency = <25000000>;
468 sleep_clk: sleep_clk {
469 compatible = "fixed-clock";
470 clock-frequency = <32768>;
477 compatible = "qcom,scm-ipq806x";
481 kraitcc: clock-controller {
482 compatible = "qcom,krait-cc-v1";
488 qcom,speed0-pvs0-bin-v0 =
489 < 1400000000 1250000 >,
490 < 1200000000 1200000 >,
491 < 1000000000 1150000 >,
492 < 800000000 1100000 >,
493 < 600000000 1050000 >,
494 < 384000000 1000000 >;
496 qcom,speed0-pvs1-bin-v0 =
497 < 1400000000 1175000 >,
498 < 1200000000 1125000 >,
499 < 1000000000 1075000 >,
500 < 800000000 1025000 >,
501 < 600000000 975000 >,
502 < 384000000 925000 >;
504 qcom,speed0-pvs2-bin-v0 =
505 < 1400000000 1125000 >,
506 < 1200000000 1075000 >,
507 < 1000000000 1025000 >,
508 < 800000000 995000 >,
509 < 600000000 925000 >,
510 < 384000000 875000 >;
512 qcom,speed0-pvs3-bin-v0 =
513 < 1400000000 1050000 >,
514 < 1200000000 1000000 >,
515 < 1000000000 950000 >,
516 < 800000000 900000 >,
517 < 600000000 850000 >,
518 < 384000000 800000 >;
522 #address-cells = <1>;
525 compatible = "simple-bus";
528 compatible = "qcom,lpass-cpu";
530 clocks = <&lcc AHBIX_CLK>,
533 clock-names = "ahbix-clk",
536 interrupts = <0 85 1>;
537 interrupt-names = "lpass-irq-lpaif";
538 reg = <0x28100000 0x10000>;
539 reg-names = "lpass-lpaif";
542 qfprom: qfprom@700000 {
543 compatible = "qcom,qfprom", "syscon";
544 reg = <0x700000 0x1000>;
545 #address-cells = <1>;
548 tsens_calib: calib@400 {
551 tsens_backup: backup@410 {
557 compatible = "qcom,rpm-ipq8064";
558 reg = <0x108000 0x1000>;
559 qcom,ipc = <&l2cc 0x8 2>;
561 interrupts = <0 19 0>,
564 interrupt-names = "ack",
568 clocks = <&gcc RPM_MSG_RAM_H_CLK>;
571 #address-cells = <1>;
574 rpmcc: clock-controller {
575 compatible = "qcom,rpmcc-ipq806x", "qcom,rpmcc";
580 compatible = "qcom,rpm-smb208-regulators";
583 regulator-min-microvolt = <1050000>;
584 regulator-max-microvolt = <1150000>;
586 qcom,switch-mode-frequency = <1200000>;
591 regulator-min-microvolt = <1050000>;
592 regulator-max-microvolt = <1150000>;
594 qcom,switch-mode-frequency = <1200000>;
598 regulator-min-microvolt = < 800000>;
599 regulator-max-microvolt = <1250000>;
601 qcom,switch-mode-frequency = <1200000>;
605 regulator-min-microvolt = < 800000>;
606 regulator-max-microvolt = <1250000>;
608 qcom,switch-mode-frequency = <1200000>;
614 compatible = "qcom,prng";
615 reg = <0x1a500000 0x200>;
616 clocks = <&gcc PRNG_CLK>;
617 clock-names = "core";
620 qcom_pinmux: pinmux@800000 {
621 compatible = "qcom,ipq8064-pinctrl";
622 reg = <0x800000 0x4000>;
626 interrupt-controller;
627 #interrupt-cells = <2>;
628 interrupts = <0 16 0x4>;
630 pcie0_pins: pcie0_pinmux {
633 function = "pcie1_rst";
634 drive-strength = <2>;
639 pcie1_pins: pcie1_pinmux {
642 function = "pcie2_rst";
643 drive-strength = <2>;
648 pcie2_pins: pcie2_pinmux {
651 function = "pcie3_rst";
652 drive-strength = <2>;
659 intc: interrupt-controller@2000000 {
660 compatible = "qcom,msm-qgic2";
661 interrupt-controller;
662 #interrupt-cells = <3>;
663 reg = <0x02000000 0x1000>,
668 compatible = "qcom,kpss-timer", "qcom,msm-timer";
669 interrupts = <1 1 0x301>,
674 reg = <0x0200a000 0x100>;
675 clock-frequency = <25000000>,
677 clocks = <&sleep_clk>;
678 clock-names = "sleep";
679 cpu-offset = <0x80000>;
682 acc0: clock-controller@2088000 {
683 compatible = "qcom,kpss-acc-v1";
684 reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
685 clock-output-names = "acpu0_aux";
688 acc1: clock-controller@2098000 {
689 compatible = "qcom,kpss-acc-v1";
690 reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
691 clock-output-names = "acpu1_aux";
694 l2cc: clock-controller@2011000 {
695 compatible = "qcom,kpss-gcc", "syscon";
696 reg = <0x2011000 0x1000>;
697 clock-output-names = "acpu_l2_aux";
700 saw0: regulator@2089000 {
701 compatible = "qcom,saw2", "syscon";
702 reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
706 saw1: regulator@2099000 {
707 compatible = "qcom,saw2", "syscon";
708 reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
712 saw_l2: regulator@02012000 {
713 compatible = "qcom,saw2", "syscon";
714 reg = <0x02012000 0x1000>;
718 sic_non_secure: sic-non-secure@12100000 {
719 compatible = "syscon";
720 reg = <0x12100000 0x10000>;
723 gsbi2: gsbi@12480000 {
724 compatible = "qcom,gsbi-v1.0.0";
726 reg = <0x12480000 0x100>;
727 clocks = <&gcc GSBI2_H_CLK>;
728 clock-names = "iface";
729 #address-cells = <1>;
734 syscon-tcsr = <&tcsr>;
736 uart2: serial@12490000 {
737 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
738 reg = <0x12490000 0x1000>,
740 interrupts = <0 195 0x0>;
741 clocks = <&gcc GSBI2_UART_CLK>, <&gcc GSBI2_H_CLK>;
742 clock-names = "core", "iface";
747 compatible = "qcom,i2c-qup-v1.1.1";
748 reg = <0x124a0000 0x1000>;
749 interrupts = <0 196 0>;
751 clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
752 clock-names = "core", "iface";
755 #address-cells = <1>;
761 gsbi4: gsbi@16300000 {
762 compatible = "qcom,gsbi-v1.0.0";
764 reg = <0x16300000 0x100>;
765 clocks = <&gcc GSBI4_H_CLK>;
766 clock-names = "iface";
767 #address-cells = <1>;
772 syscon-tcsr = <&tcsr>;
774 gsbi4_serial: serial@16340000 {
775 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
776 reg = <0x16340000 0x1000>,
778 interrupts = <0 152 0x0>;
779 clocks = <&gcc GSBI4_UART_CLK>, <&gcc GSBI4_H_CLK>;
780 clock-names = "core", "iface";
785 compatible = "qcom,i2c-qup-v1.1.1";
786 reg = <0x16380000 0x1000>;
787 interrupts = <0 153 0>;
789 clocks = <&gcc GSBI4_QUP_CLK>, <&gcc GSBI4_H_CLK>;
790 clock-names = "core", "iface";
793 #address-cells = <1>;
798 gsbi5: gsbi@1a200000 {
799 compatible = "qcom,gsbi-v1.0.0";
801 reg = <0x1a200000 0x100>;
802 clocks = <&gcc GSBI5_H_CLK>;
803 clock-names = "iface";
804 #address-cells = <1>;
809 syscon-tcsr = <&tcsr>;
811 uart5: serial@1a240000 {
812 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
813 reg = <0x1a240000 0x1000>,
815 interrupts = <0 154 0x0>;
816 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
817 clock-names = "core", "iface";
822 compatible = "qcom,i2c-qup-v1.1.1";
823 reg = <0x1a280000 0x1000>;
824 interrupts = <0 155 0>;
826 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
827 clock-names = "core", "iface";
830 #address-cells = <1>;
835 compatible = "qcom,spi-qup-v1.1.1";
836 reg = <0x1a280000 0x1000>;
837 interrupts = <0 155 0>;
839 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
840 clock-names = "core", "iface";
843 #address-cells = <1>;
848 sata_phy: sata-phy@1b400000 {
849 compatible = "qcom,ipq806x-sata-phy";
850 reg = <0x1b400000 0x200>;
852 clocks = <&gcc SATA_PHY_CFG_CLK>;
860 compatible = "qcom,ipq806x-ahci", "generic-ahci";
861 reg = <0x29000000 0x180>;
863 ports-implemented = <0x1>;
865 interrupts = <0 209 0x0>;
867 clocks = <&gcc SFAB_SATA_S_H_CLK>,
870 <&gcc SATA_RXOOB_CLK>,
871 <&gcc SATA_PMALIVE_CLK>;
872 clock-names = "slave_face", "iface", "core",
875 assigned-clocks = <&gcc SATA_RXOOB_CLK>, <&gcc SATA_PMALIVE_CLK>;
876 assigned-clock-rates = <100000000>, <100000000>;
879 phy-names = "sata-phy";
884 compatible = "qcom,ssbi";
885 reg = <0x00500000 0x1000>;
886 qcom,controller-type = "pmic-arbiter";
889 gcc: clock-controller@900000 {
890 compatible = "qcom,gcc-ipq8064";
891 reg = <0x00900000 0x4000>;
894 #power-domain-cells = <1>;
897 tsens: thermal-sensor@900000 {
898 compatible = "qcom,ipq8064-tsens";
899 reg = <0x900000 0x3680>;
900 nvmem-cells = <&tsens_calib>, <&tsens_backup>;
901 nvmem-cell-names = "calib", "calib_backup";
902 interrupts = <0 178 0>;
903 #thermal-sensor-cells = <1>;
906 tcsr: syscon@1a400000 {
907 compatible = "qcom,tcsr-ipq8064", "syscon";
908 reg = <0x1a400000 0x100>;
911 lcc: clock-controller@28000000 {
912 compatible = "qcom,lcc-ipq8064";
913 reg = <0x28000000 0x1000>;
918 sfpb_mutex_block: syscon@1200600 {
919 compatible = "syscon";
920 reg = <0x01200600 0x100>;
923 hs_phy_1: phy@100f8800 {
924 compatible = "qcom,dwc3-hs-usb-phy";
925 reg = <0x100f8800 0x30>;
926 clocks = <&gcc USB30_1_UTMI_CLK>;
933 ss_phy_1: phy@100f8830 {
934 compatible = "qcom,dwc3-ss-usb-phy";
935 reg = <0x100f8830 0x30>;
936 clocks = <&gcc USB30_1_MASTER_CLK>;
943 hs_phy_0: phy@110f8800 {
944 compatible = "qcom,dwc3-hs-usb-phy";
945 reg = <0x110f8800 0x30>;
946 clocks = <&gcc USB30_0_UTMI_CLK>;
953 ss_phy_0: phy@110f8830 {
954 compatible = "qcom,dwc3-ss-usb-phy";
955 reg = <0x110f8830 0x30>;
956 clocks = <&gcc USB30_0_MASTER_CLK>;
964 compatible = "qcom,dwc3";
965 #address-cells = <1>;
967 clocks = <&gcc USB30_0_MASTER_CLK>;
968 clock-names = "core";
972 resets = <&gcc USB30_0_MASTER_RESET>;
973 reset-names = "usb30_0_mstr_rst";
977 dwc3_0: dwc3@11000000 {
978 compatible = "snps,dwc3";
979 reg = <0x11000000 0xcd00>;
980 interrupts = <0 110 0x4>;
981 phys = <&hs_phy_0>, <&ss_phy_0>;
982 phy-names = "usb2-phy", "usb3-phy";
984 snps,dis_u3_susphy_quirk;
989 compatible = "qcom,dwc3";
990 #address-cells = <1>;
992 clocks = <&gcc USB30_1_MASTER_CLK>;
993 clock-names = "core";
997 resets = <&gcc USB30_1_MASTER_RESET>;
998 reset-names = "usb30_1_mstr_rst";
1000 status = "disabled";
1002 dwc3_1: dwc3@10000000 {
1003 compatible = "snps,dwc3";
1004 reg = <0x10000000 0xcd00>;
1005 interrupts = <0 205 0x4>;
1006 phys = <&hs_phy_1>, <&ss_phy_1>;
1007 phy-names = "usb2-phy", "usb3-phy";
1009 snps,dis_u3_susphy_quirk;
1013 pcie0: pci@1b500000 {
1014 compatible = "qcom,pcie-ipq8064";
1015 reg = <0x1b500000 0x1000
1018 0x0ff00000 0x100000>;
1019 reg-names = "dbi", "elbi", "parf", "config";
1020 device_type = "pci";
1021 linux,pci-domain = <0>;
1022 bus-range = <0x00 0xff>;
1024 #address-cells = <3>;
1027 ranges = <0x81000000 0 0x0fe00000 0x0fe00000 0 0x00100000 /* downstream I/O */
1028 0x82000000 0 0x08000000 0x08000000 0 0x07e00000>; /* non-prefetchable memory */
1030 interrupts = <GIC_SPI 35 IRQ_TYPE_NONE>;
1031 interrupt-names = "msi";
1032 #interrupt-cells = <1>;
1033 interrupt-map-mask = <0 0 0 0x7>;
1034 interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1035 <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1036 <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1037 <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1039 clocks = <&gcc PCIE_A_CLK>,
1041 <&gcc PCIE_PHY_CLK>,
1042 <&gcc PCIE_AUX_CLK>,
1043 <&gcc PCIE_ALT_REF_CLK>;
1044 clock-names = "core", "iface", "phy", "aux", "ref";
1046 assigned-clocks = <&gcc PCIE_ALT_REF_CLK>;
1047 assigned-clock-rates = <100000000>;
1049 resets = <&gcc PCIE_ACLK_RESET>,
1050 <&gcc PCIE_HCLK_RESET>,
1051 <&gcc PCIE_POR_RESET>,
1052 <&gcc PCIE_PCI_RESET>,
1053 <&gcc PCIE_PHY_RESET>,
1054 <&gcc PCIE_EXT_RESET>;
1055 reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
1057 pinctrl-0 = <&pcie0_pins>;
1058 pinctrl-names = "default";
1060 perst-gpios = <&qcom_pinmux 3 GPIO_ACTIVE_LOW>;
1062 phy-tx0-term-offset = <7>;
1064 status = "disabled";
1067 pcie1: pci@1b700000 {
1068 compatible = "qcom,pcie-ipq8064";
1069 reg = <0x1b700000 0x1000
1072 0x31f00000 0x100000>;
1073 reg-names = "dbi", "elbi", "parf", "config";
1074 device_type = "pci";
1075 linux,pci-domain = <1>;
1076 bus-range = <0x00 0xff>;
1078 #address-cells = <3>;
1081 ranges = <0x81000000 0 0x31e00000 0x31e00000 0 0x00100000 /* downstream I/O */
1082 0x82000000 0 0x2e000000 0x2e000000 0 0x03e00000>; /* non-prefetchable memory */
1084 interrupts = <GIC_SPI 57 IRQ_TYPE_NONE>;
1085 interrupt-names = "msi";
1086 #interrupt-cells = <1>;
1087 interrupt-map-mask = <0 0 0 0x7>;
1088 interrupt-map = <0 0 0 1 &intc 0 58 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1089 <0 0 0 2 &intc 0 59 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1090 <0 0 0 3 &intc 0 60 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1091 <0 0 0 4 &intc 0 61 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1093 clocks = <&gcc PCIE_1_A_CLK>,
1094 <&gcc PCIE_1_H_CLK>,
1095 <&gcc PCIE_1_PHY_CLK>,
1096 <&gcc PCIE_1_AUX_CLK>,
1097 <&gcc PCIE_1_ALT_REF_CLK>;
1098 clock-names = "core", "iface", "phy", "aux", "ref";
1100 assigned-clocks = <&gcc PCIE_1_ALT_REF_CLK>;
1101 assigned-clock-rates = <100000000>;
1103 resets = <&gcc PCIE_1_ACLK_RESET>,
1104 <&gcc PCIE_1_HCLK_RESET>,
1105 <&gcc PCIE_1_POR_RESET>,
1106 <&gcc PCIE_1_PCI_RESET>,
1107 <&gcc PCIE_1_PHY_RESET>,
1108 <&gcc PCIE_1_EXT_RESET>;
1109 reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
1111 pinctrl-0 = <&pcie1_pins>;
1112 pinctrl-names = "default";
1114 perst-gpios = <&qcom_pinmux 48 GPIO_ACTIVE_LOW>;
1116 phy-tx0-term-offset = <7>;
1118 status = "disabled";
1121 pcie2: pci@1b900000 {
1122 compatible = "qcom,pcie-ipq8064";
1123 reg = <0x1b900000 0x1000
1126 0x35f00000 0x100000>;
1127 reg-names = "dbi", "elbi", "parf", "config";
1128 device_type = "pci";
1129 linux,pci-domain = <2>;
1130 bus-range = <0x00 0xff>;
1132 #address-cells = <3>;
1135 ranges = <0x81000000 0 0x35e00000 0x35e00000 0 0x00100000 /* downstream I/O */
1136 0x82000000 0 0x32000000 0x32000000 0 0x03e00000>; /* non-prefetchable memory */
1138 interrupts = <GIC_SPI 71 IRQ_TYPE_NONE>;
1139 interrupt-names = "msi";
1140 #interrupt-cells = <1>;
1141 interrupt-map-mask = <0 0 0 0x7>;
1142 interrupt-map = <0 0 0 1 &intc 0 72 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1143 <0 0 0 2 &intc 0 73 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1144 <0 0 0 3 &intc 0 74 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1145 <0 0 0 4 &intc 0 75 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1147 clocks = <&gcc PCIE_2_A_CLK>,
1148 <&gcc PCIE_2_H_CLK>,
1149 <&gcc PCIE_2_PHY_CLK>,
1150 <&gcc PCIE_2_AUX_CLK>,
1151 <&gcc PCIE_2_ALT_REF_CLK>;
1152 clock-names = "core", "iface", "phy", "aux", "ref";
1154 assigned-clocks = <&gcc PCIE_2_ALT_REF_CLK>;
1155 assigned-clock-rates = <100000000>;
1157 resets = <&gcc PCIE_2_ACLK_RESET>,
1158 <&gcc PCIE_2_HCLK_RESET>,
1159 <&gcc PCIE_2_POR_RESET>,
1160 <&gcc PCIE_2_PCI_RESET>,
1161 <&gcc PCIE_2_PHY_RESET>,
1162 <&gcc PCIE_2_EXT_RESET>;
1163 reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
1165 pinctrl-0 = <&pcie2_pins>;
1166 pinctrl-names = "default";
1168 perst-gpios = <&qcom_pinmux 63 GPIO_ACTIVE_LOW>;
1170 phy-tx0-term-offset = <7>;
1172 status = "disabled";
1175 adm_dma: dma@18300000 {
1176 compatible = "qcom,adm";
1177 reg = <0x18300000 0x100000>;
1178 interrupts = <0 170 0>;
1181 clocks = <&gcc ADM0_CLK>, <&gcc ADM0_PBUS_CLK>;
1182 clock-names = "core", "iface";
1184 resets = <&gcc ADM0_RESET>,
1185 <&gcc ADM0_PBUS_RESET>,
1186 <&gcc ADM0_C0_RESET>,
1187 <&gcc ADM0_C1_RESET>,
1188 <&gcc ADM0_C2_RESET>;
1189 reset-names = "clk", "pbus", "c0", "c1", "c2";
1192 status = "disabled";
1196 compatible = "qcom,ipq806x-nand";
1197 reg = <0x1ac00000 0x800>;
1199 clocks = <&gcc EBI2_CLK>,
1200 <&gcc EBI2_AON_CLK>;
1201 clock-names = "core", "aon";
1203 dmas = <&adm_dma 3>;
1205 qcom,cmd-crci = <15>;
1206 qcom,data-crci = <3>;
1208 status = "disabled";
1210 #address-cells = <1>;
1214 nss_common: syscon@03000000 {
1215 compatible = "syscon";
1216 reg = <0x03000000 0x0000FFFF>;
1219 qsgmii_csr: syscon@1bb00000 {
1220 compatible = "syscon";
1221 reg = <0x1bb00000 0x000001FF>;
1224 stmmac_axi_setup: stmmac-axi-config {
1225 snps,wr_osr_lmt = <7>;
1226 snps,rd_osr_lmt = <7>;
1227 snps,blen = <16 0 0 0 0 0 0>;
1230 gmac0: ethernet@37000000 {
1231 device_type = "network";
1232 compatible = "qcom,ipq806x-gmac";
1233 reg = <0x37000000 0x200000>;
1234 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
1235 interrupt-names = "macirq";
1237 snps,axi-config = <&stmmac_axi_setup>;
1241 qcom,nss-common = <&nss_common>;
1242 qcom,qsgmii-csr = <&qsgmii_csr>;
1244 clocks = <&gcc GMAC_CORE1_CLK>;
1245 clock-names = "stmmaceth";
1247 resets = <&gcc GMAC_CORE1_RESET>;
1248 reset-names = "stmmaceth";
1250 status = "disabled";
1253 gmac1: ethernet@37200000 {
1254 device_type = "network";
1255 compatible = "qcom,ipq806x-gmac";
1256 reg = <0x37200000 0x200000>;
1257 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
1258 interrupt-names = "macirq";
1260 snps,axi-config = <&stmmac_axi_setup>;
1264 qcom,nss-common = <&nss_common>;
1265 qcom,qsgmii-csr = <&qsgmii_csr>;
1267 clocks = <&gcc GMAC_CORE2_CLK>;
1268 clock-names = "stmmaceth";
1270 resets = <&gcc GMAC_CORE2_RESET>;
1271 reset-names = "stmmaceth";
1273 status = "disabled";
1276 gmac2: ethernet@37400000 {
1277 device_type = "network";
1278 compatible = "qcom,ipq806x-gmac";
1279 reg = <0x37400000 0x200000>;
1280 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
1281 interrupt-names = "macirq";
1283 snps,axi-config = <&stmmac_axi_setup>;
1287 qcom,nss-common = <&nss_common>;
1288 qcom,qsgmii-csr = <&qsgmii_csr>;
1290 clocks = <&gcc GMAC_CORE3_CLK>;
1291 clock-names = "stmmaceth";
1293 resets = <&gcc GMAC_CORE3_RESET>;
1294 reset-names = "stmmaceth";
1296 status = "disabled";
1299 gmac3: ethernet@37600000 {
1300 device_type = "network";
1301 compatible = "qcom,ipq806x-gmac";
1302 reg = <0x37600000 0x200000>;
1303 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
1304 interrupt-names = "macirq";
1306 snps,axi-config = <&stmmac_axi_setup>;
1310 qcom,nss-common = <&nss_common>;
1311 qcom,qsgmii-csr = <&qsgmii_csr>;
1313 clocks = <&gcc GMAC_CORE4_CLK>;
1314 clock-names = "stmmaceth";
1316 resets = <&gcc GMAC_CORE4_RESET>;
1317 reset-names = "stmmaceth";
1319 status = "disabled";
1322 /* Temporary fixed regulator */
1323 vsdcc_fixed: vsdcc-regulator {
1324 compatible = "regulator-fixed";
1325 regulator-name = "SDCC Power";
1326 regulator-min-microvolt = <3300000>;
1327 regulator-max-microvolt = <3300000>;
1328 regulator-always-on;
1331 sdcc1bam:dma@12402000 {
1332 compatible = "qcom,bam-v1.3.0";
1333 reg = <0x12402000 0x8000>;
1334 interrupts = <0 98 0>;
1335 clocks = <&gcc SDC1_H_CLK>;
1336 clock-names = "bam_clk";
1341 sdcc3bam:dma@12182000 {
1342 compatible = "qcom,bam-v1.3.0";
1343 reg = <0x12182000 0x8000>;
1344 interrupts = <0 96 0>;
1345 clocks = <&gcc SDC3_H_CLK>;
1346 clock-names = "bam_clk";
1352 compatible = "arm,amba-bus";
1353 #address-cells = <1>;
1356 sdcc1: sdcc@12400000 {
1357 status = "disabled";
1358 compatible = "arm,pl18x", "arm,primecell";
1359 arm,primecell-periphid = <0x00051180>;
1360 reg = <0x12400000 0x2000>;
1361 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
1362 interrupt-names = "cmd_irq";
1363 clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
1364 clock-names = "mclk", "apb_pclk";
1366 max-frequency = <96000000>;
1370 vmmc-supply = <&vsdcc_fixed>;
1371 dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
1372 dma-names = "tx", "rx";
1375 sdcc3: sdcc@12180000 {
1376 compatible = "arm,pl18x", "arm,primecell";
1377 arm,primecell-periphid = <0x00051180>;
1378 status = "disabled";
1379 reg = <0x12180000 0x2000>;
1380 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
1381 interrupt-names = "cmd_irq";
1382 clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
1383 clock-names = "mclk", "apb_pclk";
1387 max-frequency = <192000000>;
1391 vqmmc-supply = <&vsdcc_fixed>;
1392 dmas = <&sdcc3bam 2>, <&sdcc3bam 1>;
1393 dma-names = "tx", "rx";
1398 sfpb_mutex: sfpb-mutex {
1399 compatible = "qcom,sfpb-mutex";
1400 syscon = <&sfpb_mutex_block 4 4>;
1402 #hwlock-cells = <1>;
1406 compatible = "qcom,smem";
1407 memory-region = <&smem>;
1408 hwlocks = <&sfpb_mutex 3>;