target/linux/ipq806x/files-4.19/arch/arm/boot/dts/qcom-ipq8064.dtsi

   1 /dts-v1/;
   2
   3 #include "skeleton.dtsi"
   4 #include <dt-bindings/clock/qcom,gcc-ipq806x.h>
   5 #include <dt-bindings/mfd/qcom-rpm.h>
   6 #include <dt-bindings/clock/qcom,rpmcc.h>
   7 #include <dt-bindings/clock/qcom,lcc-ipq806x.h>
   8 #include <dt-bindings/soc/qcom,gsbi.h>
   9 #include <dt-bindings/reset/qcom,gcc-ipq806x.h>
  10 #include <dt-bindings/interrupt-controller/arm-gic.h>
  11 #include <dt-bindings/gpio/gpio.h>
  12
  13 / {
  14         model = "Qualcomm IPQ8064";
  15         compatible = "qcom,ipq8064";
  16         interrupt-parent = <&intc>;
  17
  18         cpus {
  19                 #address-cells = <1>;
  20                 #size-cells = <0>;
  21
  22                 cpu0: cpu@0 {
  23                         compatible = "qcom,krait";
  24                         enable-method = "qcom,kpss-acc-v1";
  25                         device_type = "cpu";
  26                         reg = <0>;
  27                         next-level-cache = <&L2>;
  28                         qcom,acc = <&acc0>;
  29                         qcom,saw = <&saw0>;
  30                         clocks = <&kraitcc 0>, <&kraitcc 4>;
  31                         clock-names = "cpu", "l2";
  32                         clock-latency = <100000>;
  33                         cpu-supply = <&smb208_s2a>;
  34                         voltage-tolerance = <5>;
  35                         cooling-min-state = <0>;
  36                         cooling-max-state = <10>;
  37                         #cooling-cells = <2>;
  38                         cpu-idle-states = <&CPU_SPC>;
  39                 };
  40
  41                 cpu1: cpu@1 {
  42                         compatible = "qcom,krait";
  43                         enable-method = "qcom,kpss-acc-v1";
  44                         device_type = "cpu";
  45                         reg = <1>;
  46                         next-level-cache = <&L2>;
  47                         qcom,acc = <&acc1>;
  48                         qcom,saw = <&saw1>;
  49                         clocks = <&kraitcc 1>, <&kraitcc 4>;
  50                         clock-names = "cpu", "l2";
  51                         clock-latency = <100000>;
  52                         cpu-supply = <&smb208_s2b>;
  53                         cooling-min-state = <0>;
  54                         cooling-max-state = <10>;
  55                         #cooling-cells = <2>;
  56                         cpu-idle-states = <&CPU_SPC>;
  57                 };
  58
  59                 L2: l2-cache {
  60                         compatible = "cache";
  61                         cache-level = <2>;
  62                         qcom,saw = <&saw_l2>;
  63                 };
  64
  65                 qcom,l2 {
  66                         qcom,l2-rates = <384000000 1000000000 1200000000>;
  67                 };
  68
  69                 idle-states {
  70                         CPU_SPC: spc {
  71                                 compatible = "qcom,idle-state-spc",
  72                                                 "arm,idle-state";
  73                                 entry-latency-us = <400>;
  74                                 exit-latency-us = <900>;
  75                                 min-residency-us = <3000>;
  76                         };
  77                 };
  78         };
  79
  80         thermal-zones {
  81                 tsens_tz_sensor0 {
  82                         polling-delay-passive = <0>;
  83                         polling-delay = <0>;
  84                         thermal-sensors = <&tsens 0>;
  85
  86                         trips {
  87                                 cpu-critical-hi {
  88                                         temperature = <125000>;
  89                                         hysteresis = <2000>;
  90                                         type = "critical_high";
  91                                 };
  92
  93                                 cpu-config-hi {
  94                                         temperature = <105000>;
  95                                         hysteresis = <2000>;
  96                                         type = "configurable_hi";
  97                                 };
  98
  99                                 cpu-config-lo {
 100                                         temperature = <95000>;
 101                                         hysteresis = <2000>;
 102                                         type = "configurable_lo";
 103                                 };
 104
 105                                 cpu-critical-low {
 106                                         temperature = <0>;
 107                                         hysteresis = <2000>;
 108                                         type = "critical_low";
 109                                 };
 110                         };
 111                 };
 112
 113                 tsens_tz_sensor1 {
 114                         polling-delay-passive = <0>;
 115                         polling-delay = <0>;
 116                         thermal-sensors = <&tsens 1>;
 117
 118                         trips {
 119                                 cpu-critical-hi {
 120                                         temperature = <125000>;
 121                                         hysteresis = <2000>;
 122                                         type = "critical_high";
 123                                 };
 124
 125                                 cpu-config-hi {
 126                                         temperature = <105000>;
 127                                         hysteresis = <2000>;
 128                                         type = "configurable_hi";
 129                                 };
 130
 131                                 cpu-config-lo {
 132                                         temperature = <95000>;
 133                                         hysteresis = <2000>;
 134                                         type = "configurable_lo";
 135                                 };
 136
 137                                 cpu-critical-low {
 138                                         temperature = <0>;
 139                                         hysteresis = <2000>;
 140                                         type = "critical_low";
 141                                 };
 142                         };
 143                 };
 144
 145                 tsens_tz_sensor2 {
 146                         polling-delay-passive = <0>;
 147                         polling-delay = <0>;
 148                         thermal-sensors = <&tsens 2>;
 149
 150                         trips {
 151                                 cpu-critical-hi {
 152                                         temperature = <125000>;
 153                                         hysteresis = <2000>;
 154                                         type = "critical_high";
 155                                 };
 156
 157                                 cpu-config-hi {
 158                                         temperature = <105000>;
 159                                         hysteresis = <2000>;
 160                                         type = "configurable_hi";
 161                                 };
 162
 163                                 cpu-config-lo {
 164                                         temperature = <95000>;
 165                                         hysteresis = <2000>;
 166                                         type = "configurable_lo";
 167                                 };
 168
 169                                 cpu-critical-low {
 170                                         temperature = <0>;
 171                                         hysteresis = <2000>;
 172                                         type = "critical_low";
 173                                 };
 174                         };
 175                 };
 176
 177                 tsens_tz_sensor3 {
 178                         polling-delay-passive = <0>;
 179                         polling-delay = <0>;
 180                         thermal-sensors = <&tsens 3>;
 181
 182                         trips {
 183                                 cpu-critical-hi {
 184                                         temperature = <125000>;
 185                                         hysteresis = <2000>;
 186                                         type = "critical_high";
 187                                 };
 188
 189                                 cpu-config-hi {
 190                                         temperature = <105000>;
 191                                         hysteresis = <2000>;
 192                                         type = "configurable_hi";
 193                                 };
 194
 195                                 cpu-config-lo {
 196                                         temperature = <95000>;
 197                                         hysteresis = <2000>;
 198                                         type = "configurable_lo";
 199                                 };
 200
 201                                 cpu-critical-low {
 202                                         temperature = <0>;
 203                                         hysteresis = <2000>;
 204                                         type = "critical_low";
 205                                 };
 206                         };
 207                 };
 208
 209                 tsens_tz_sensor4 {
 210                         polling-delay-passive = <0>;
 211                         polling-delay = <0>;
 212                         thermal-sensors = <&tsens 4>;
 213
 214                         trips {
 215                                 cpu-critical-hi {
 216                                         temperature = <125000>;
 217                                         hysteresis = <2000>;
 218                                         type = "critical_high";
 219                                 };
 220
 221                                 cpu-config-hi {
 222                                         temperature = <105000>;
 223                                         hysteresis = <2000>;
 224                                         type = "configurable_hi";
 225                                 };
 226
 227                                 cpu-config-lo {
 228                                         temperature = <95000>;
 229                                         hysteresis = <2000>;
 230                                         type = "configurable_lo";
 231                                 };
 232
 233                                 cpu-critical-low {
 234                                         temperature = <0>;
 235                                         hysteresis = <2000>;
 236                                         type = "critical_low";
 237                                 };
 238                         };
 239                 };
 240
 241                 tsens_tz_sensor5 {
 242                         polling-delay-passive = <0>;
 243                         polling-delay = <0>;
 244                         thermal-sensors = <&tsens 5>;
 245
 246                         trips {
 247                                 cpu-critical-hi {
 248                                         temperature = <125000>;
 249                                         hysteresis = <2000>;
 250                                         type = "critical_high";
 251                                 };
 252
 253                                 cpu-config-hi {
 254                                         temperature = <105000>;
 255                                         hysteresis = <2000>;
 256                                         type = "configurable_hi";
 257                                 };
 258
 259                                 cpu-config-lo {
 260                                         temperature = <95000>;
 261                                         hysteresis = <2000>;
 262                                         type = "configurable_lo";
 263                                 };
 264
 265                                 cpu-critical-low {
 266                                         temperature = <0>;
 267                                         hysteresis = <2000>;
 268                                         type = "critical_low";
 269                                 };
 270                         };
 271                 };
 272
 273                 tsens_tz_sensor6 {
 274                         polling-delay-passive = <0>;
 275                         polling-delay = <0>;
 276                         thermal-sensors = <&tsens 6>;
 277
 278                         trips {
 279                                 cpu-critical-hi {
 280                                         temperature = <125000>;
 281                                         hysteresis = <2000>;
 282                                         type = "critical_high";
 283                                 };
 284
 285                                 cpu-config-hi {
 286                                         temperature = <105000>;
 287                                         hysteresis = <2000>;
 288                                         type = "configurable_hi";
 289                                 };
 290
 291                                 cpu-config-lo {
 292                                         temperature = <95000>;
 293                                         hysteresis = <2000>;
 294                                         type = "configurable_lo";
 295                                 };
 296
 297                                 cpu-critical-low {
 298                                         temperature = <0>;
 299                                         hysteresis = <2000>;
 300                                         type = "critical_low";
 301                                 };
 302                         };
 303                 };
 304
 305                 tsens_tz_sensor7 {
 306                         polling-delay-passive = <0>;
 307                         polling-delay = <0>;
 308                         thermal-sensors = <&tsens 7>;
 309
 310                         trips {
 311                                 cpu-critical-hi {
 312                                         temperature = <125000>;
 313                                         hysteresis = <2000>;
 314                                         type = "critical_high";
 315                                 };
 316
 317                                 cpu-config-hi {
 318                                         temperature = <105000>;
 319                                         hysteresis = <2000>;
 320                                         type = "configurable_hi";
 321                                 };
 322
 323                                 cpu-config-lo {
 324                                         temperature = <95000>;
 325                                         hysteresis = <2000>;
 326                                         type = "configurable_lo";
 327                                 };
 328
 329                                 cpu-critical-low {
 330                                         temperature = <0>;
 331                                         hysteresis = <2000>;
 332                                         type = "critical_low";
 333                                 };
 334                         };
 335                 };
 336
 337                 tsens_tz_sensor8 {
 338                         polling-delay-passive = <0>;
 339                         polling-delay = <0>;
 340                         thermal-sensors = <&tsens 8>;
 341
 342                         trips {
 343                                 cpu-critical-hi {
 344                                         temperature = <125000>;
 345                                         hysteresis = <2000>;
 346                                         type = "critical_high";
 347                                 };
 348
 349                                 cpu-config-hi {
 350                                         temperature = <105000>;
 351                                         hysteresis = <2000>;
 352                                         type = "configurable_hi";
 353                                 };
 354
 355                                 cpu-config-lo {
 356                                         temperature = <95000>;
 357                                         hysteresis = <2000>;
 358                                         type = "configurable_lo";
 359                                 };
 360
 361                                 cpu-critical-low {
 362                                         temperature = <0>;
 363                                         hysteresis = <2000>;
 364                                         type = "critical_low";
 365                                 };
 366                         };
 367                 };
 368
 369                 tsens_tz_sensor9 {
 370                         polling-delay-passive = <0>;
 371                         polling-delay = <0>;
 372                         thermal-sensors = <&tsens 9>;
 373
 374                         trips {
 375                                 cpu-critical-hi {
 376                                         temperature = <125000>;
 377                                         hysteresis = <2000>;
 378                                         type = "critical_high";
 379                                 };
 380
 381                                 cpu-config-hi {
 382                                         temperature = <105000>;
 383                                         hysteresis = <2000>;
 384                                         type = "configurable_hi";
 385                                 };
 386
 387                                 cpu-config-lo {
 388                                         temperature = <95000>;
 389                                         hysteresis = <2000>;
 390                                         type = "configurable_lo";
 391                                 };
 392
 393                                 cpu-critical-low {
 394                                         temperature = <0>;
 395                                         hysteresis = <2000>;
 396                                         type = "critical_low";
 397                                 };
 398                         };
 399                 };
 400
 401                 tsens_tz_sensor10 {
 402                         polling-delay-passive = <0>;
 403                         polling-delay = <0>;
 404                         thermal-sensors = <&tsens 10>;
 405
 406                         trips {
 407                                 cpu-critical-hi {
 408                                         temperature = <125000>;
 409                                         hysteresis = <2000>;
 410                                         type = "critical_high";
 411                                 };
 412
 413                                 cpu-config-hi {
 414                                         temperature = <105000>;
 415                                         hysteresis = <2000>;
 416                                         type = "configurable_hi";
 417                                 };
 418
 419                                 cpu-config-lo {
 420                                         temperature = <95000>;
 421                                         hysteresis = <2000>;
 422                                         type = "configurable_lo";
 423                                 };
 424
 425                                 cpu-critical-low {
 426                                         temperature = <0>;
 427                                         hysteresis = <2000>;
 428                                         type = "critical_low";
 429                                 };
 430                         };
 431                 };
 432         };
 433
 434         cpu-pmu {
 435                 compatible = "qcom,krait-pmu";
 436                 interrupts = <1 10 0x304>;
 437         };
 438
 439         reserved-memory {
 440                 #address-cells = <1>;
 441                 #size-cells = <1>;
 442                 ranges;
 443
 444                 nss@40000000 {
 445                         reg = <0x40000000 0x1000000>;
 446                         no-map;
 447                 };
 448
 449                 smem: smem@41000000 {
 450                         reg = <0x41000000 0x200000>;
 451                         no-map;
 452                 };
 453         };
 454
 455         clocks {
 456                 cxo_board {
 457                         compatible = "fixed-clock";
 458                         #clock-cells = <0>;
 459                         clock-frequency = <25000000>;
 460                 };
 461
 462                 pxo_board {
 463                         compatible = "fixed-clock";
 464                         #clock-cells = <0>;
 465                         clock-frequency = <25000000>;
 466                 };
 467
 468                 sleep_clk: sleep_clk {
 469                         compatible = "fixed-clock";
 470                         clock-frequency = <32768>;
 471                         #clock-cells = <0>;
 472                 };
 473         };
 474
 475         firmware {
 476                 scm {
 477                         compatible = "qcom,scm-ipq806x";
 478                 };
 479         };
 480
 481         kraitcc: clock-controller {
 482                 compatible = "qcom,krait-cc-v1";
 483                 #clock-cells = <1>;
 484         };
 485
 486         qcom,pvs {
 487                 qcom,pvs-format-a;
 488                 qcom,speed0-pvs0-bin-v0 =
 489                         < 1400000000 1250000 >,
 490                         < 1200000000 1200000 >,
 491                         < 1000000000 1150000 >,
 492                          < 800000000 1100000 >,
 493                          < 600000000 1050000 >,
 494                          < 384000000 1000000 >;
 495
 496                 qcom,speed0-pvs1-bin-v0 =
 497                         < 1400000000 1175000 >,
 498                         < 1200000000 1125000 >,
 499                         < 1000000000 1075000 >,
 500                          < 800000000 1025000 >,
 501                          < 600000000  975000 >,
 502                          < 384000000  925000 >;
 503
 504                 qcom,speed0-pvs2-bin-v0 =
 505                         < 1400000000 1125000 >,
 506                         < 1200000000 1075000 >,
 507                         < 1000000000 1025000 >,
 508                          < 800000000  995000 >,
 509                          < 600000000  925000 >,
 510                          < 384000000  875000 >;
 511
 512                 qcom,speed0-pvs3-bin-v0 =
 513                         < 1400000000 1050000 >,
 514                         < 1200000000 1000000 >,
 515                         < 1000000000  950000 >,
 516                          < 800000000  900000 >,
 517                          < 600000000  850000 >,
 518                          < 384000000  800000 >;
 519         };
 520
 521         soc: soc {
 522                 #address-cells = <1>;
 523                 #size-cells = <1>;
 524                 ranges;
 525                 compatible = "simple-bus";
 526
 527                 lpass@28100000 {
 528                         compatible = "qcom,lpass-cpu";
 529                         status = "disabled";
 530                         clocks = <&lcc AHBIX_CLK>,
 531                                         <&lcc MI2S_OSR_CLK>,
 532                                         <&lcc MI2S_BIT_CLK>;
 533                         clock-names = "ahbix-clk",
 534                                         "mi2s-osr-clk",
 535                                         "mi2s-bit-clk";
 536                         interrupts = <0 85 1>;
 537                         interrupt-names = "lpass-irq-lpaif";
 538                         reg = <0x28100000 0x10000>;
 539                         reg-names = "lpass-lpaif";
 540                 };
 541
 542                 qfprom: qfprom@700000 {
 543                         compatible = "qcom,qfprom", "syscon";
 544                         reg = <0x700000 0x1000>;
 545                         #address-cells = <1>;
 546                         #size-cells = <1>;
 547                         status = "okay";
 548                         tsens_calib: calib@400 {
 549                                 reg = <0x400 0x10>;
 550                         };
 551                         tsens_backup: backup@410 {
 552                                 reg = <0x410 0x10>;
 553                         };
 554                 };
 555
 556                 rpm@108000 {
 557                         compatible = "qcom,rpm-ipq8064";
 558                         reg = <0x108000 0x1000>;
 559                         qcom,ipc = <&l2cc 0x8 2>;
 560
 561                         interrupts = <0 19 0>,
 562                                      <0 21 0>,
 563                                      <0 22 0>;
 564                         interrupt-names = "ack",
 565                                           "err",
 566                                           "wakeup";
 567
 568                         clocks = <&gcc RPM_MSG_RAM_H_CLK>;
 569                         clock-names = "ram";
 570
 571                         #address-cells = <1>;
 572                         #size-cells = <0>;
 573
 574                         rpmcc: clock-controller {
 575                                 compatible      = "qcom,rpmcc-ipq806x", "qcom,rpmcc";
 576                                 #clock-cells = <1>;
 577                         };
 578
 579                         regulators {
 580                                 compatible = "qcom,rpm-smb208-regulators";
 581
 582                                 smb208_s1a: s1a {
 583                                         regulator-min-microvolt = <1050000>;
 584                                         regulator-max-microvolt = <1150000>;
 585
 586                                         qcom,switch-mode-frequency = <1200000>;
 587
 588                                 };
 589
 590                                 smb208_s1b: s1b {
 591                                         regulator-min-microvolt = <1050000>;
 592                                         regulator-max-microvolt = <1150000>;
 593
 594                                         qcom,switch-mode-frequency = <1200000>;
 595                                 };
 596
 597                                 smb208_s2a: s2a {
 598                                         regulator-min-microvolt = < 800000>;
 599                                         regulator-max-microvolt = <1250000>;
 600
 601                                         qcom,switch-mode-frequency = <1200000>;
 602                                 };
 603
 604                                 smb208_s2b: s2b {
 605                                         regulator-min-microvolt = < 800000>;
 606                                         regulator-max-microvolt = <1250000>;
 607
 608                                         qcom,switch-mode-frequency = <1200000>;
 609                                 };
 610                         };
 611                 };
 612
 613                 rng@1a500000 {
 614                         compatible = "qcom,prng";
 615                         reg = <0x1a500000 0x200>;
 616                         clocks = <&gcc PRNG_CLK>;
 617                         clock-names = "core";
 618                 };
 619
 620                 qcom_pinmux: pinmux@800000 {
 621                         compatible = "qcom,ipq8064-pinctrl";
 622                         reg = <0x800000 0x4000>;
 623
 624                         gpio-controller;
 625                         #gpio-cells = <2>;
 626                         interrupt-controller;
 627                         #interrupt-cells = <2>;
 628                         interrupts = <0 16 0x4>;
 629
 630                         pcie0_pins: pcie0_pinmux {
 631                                 mux {
 632                                         pins = "gpio3";
 633                                         function = "pcie1_rst";
 634                                         drive-strength = <2>;
 635                                         bias-disable;
 636                                 };
 637                         };
 638
 639                         pcie1_pins: pcie1_pinmux {
 640                                 mux {
 641                                         pins = "gpio48";
 642                                         function = "pcie2_rst";
 643                                         drive-strength = <2>;
 644                                         bias-disable;
 645                                 };
 646                         };
 647
 648                         pcie2_pins: pcie2_pinmux {
 649                                 mux {
 650                                         pins = "gpio63";
 651                                         function = "pcie3_rst";
 652                                         drive-strength = <2>;
 653                                         bias-disable;
 654                                         output-low;
 655                                 };
 656                         };
 657                 };
 658
 659                 intc: interrupt-controller@2000000 {
 660                         compatible = "qcom,msm-qgic2";
 661                         interrupt-controller;
 662                         #interrupt-cells = <3>;
 663                         reg = <0x02000000 0x1000>,
 664                               <0x02002000 0x1000>;
 665                 };
 666
 667                 timer@200a000 {
 668                         compatible = "qcom,kpss-timer", "qcom,msm-timer";
 669                         interrupts = <1 1 0x301>,
 670                                      <1 2 0x301>,
 671                                      <1 3 0x301>,
 672                                      <1 4 0x301>,
 673                                      <1 5 0x301>;
 674                         reg = <0x0200a000 0x100>;
 675                         clock-frequency = <25000000>,
 676                                           <32768>;
 677                         clocks = <&sleep_clk>;
 678                         clock-names = "sleep";
 679                         cpu-offset = <0x80000>;
 680                 };
 681
 682                 acc0: clock-controller@2088000 {
 683                         compatible = "qcom,kpss-acc-v1";
 684                         reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
 685                         clock-output-names = "acpu0_aux";
 686                 };
 687
 688                 acc1: clock-controller@2098000 {
 689                         compatible = "qcom,kpss-acc-v1";
 690                         reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
 691                         clock-output-names = "acpu1_aux";
 692                 };
 693
 694                 l2cc: clock-controller@2011000 {
 695                         compatible = "qcom,kpss-gcc", "syscon";
 696                         reg = <0x2011000 0x1000>;
 697                         clock-output-names = "acpu_l2_aux";
 698                 };
 699
 700                 saw0: regulator@2089000 {
 701                         compatible = "qcom,saw2", "syscon";
 702                         reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
 703                         regulator;
 704                 };
 705
 706                 saw1: regulator@2099000 {
 707                         compatible = "qcom,saw2", "syscon";
 708                         reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
 709                         regulator;
 710                 };
 711
 712                 saw_l2: regulator@02012000 {
 713                         compatible = "qcom,saw2", "syscon";
 714                         reg = <0x02012000 0x1000>;
 715                         regulator;
 716                 };
 717
 718                 sic_non_secure: sic-non-secure@12100000 {
 719                         compatible = "syscon";
 720                         reg = <0x12100000 0x10000>;
 721                 };
 722
 723                 gsbi2: gsbi@12480000 {
 724                         compatible = "qcom,gsbi-v1.0.0";
 725                         cell-index = <2>;
 726                         reg = <0x12480000 0x100>;
 727                         clocks = <&gcc GSBI2_H_CLK>;
 728                         clock-names = "iface";
 729                         #address-cells = <1>;
 730                         #size-cells = <1>;
 731                         ranges;
 732                         status = "disabled";
 733
 734                         syscon-tcsr = <&tcsr>;
 735
 736                         uart2: serial@12490000 {
 737                                 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
 738                                 reg = <0x12490000 0x1000>,
 739                                       <0x12480000 0x1000>;
 740                                 interrupts = <0 195 0x0>;
 741                                 clocks = <&gcc GSBI2_UART_CLK>, <&gcc GSBI2_H_CLK>;
 742                                 clock-names = "core", "iface";
 743                                 status = "disabled";
 744                         };
 745
 746                         i2c@124a0000 {
 747                                 compatible = "qcom,i2c-qup-v1.1.1";
 748                                 reg = <0x124a0000 0x1000>;
 749                                 interrupts = <0 196 0>;
 750
 751                                 clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
 752                                 clock-names = "core", "iface";
 753                                 status = "disabled";
 754
 755                                 #address-cells = <1>;
 756                                 #size-cells = <0>;
 757                         };
 758
 759                 };
 760
 761                 gsbi4: gsbi@16300000 {
 762                         compatible = "qcom,gsbi-v1.0.0";
 763                         cell-index = <4>;
 764                         reg = <0x16300000 0x100>;
 765                         clocks = <&gcc GSBI4_H_CLK>;
 766                         clock-names = "iface";
 767                         #address-cells = <1>;
 768                         #size-cells = <1>;
 769                         ranges;
 770                         status = "disabled";
 771
 772                         syscon-tcsr = <&tcsr>;
 773
 774                         gsbi4_serial: serial@16340000 {
 775                                 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
 776                                 reg = <0x16340000 0x1000>,
 777                                       <0x16300000 0x1000>;
 778                                 interrupts = <0 152 0x0>;
 779                                 clocks = <&gcc GSBI4_UART_CLK>, <&gcc GSBI4_H_CLK>;
 780                                 clock-names = "core", "iface";
 781                                 status = "disabled";
 782                         };
 783
 784                         i2c@16380000 {
 785                                 compatible = "qcom,i2c-qup-v1.1.1";
 786                                 reg = <0x16380000 0x1000>;
 787                                 interrupts = <0 153 0>;
 788
 789                                 clocks = <&gcc GSBI4_QUP_CLK>, <&gcc GSBI4_H_CLK>;
 790                                 clock-names = "core", "iface";
 791                                 status = "disabled";
 792
 793                                 #address-cells = <1>;
 794                                 #size-cells = <0>;
 795                         };
 796                 };
 797
 798                 gsbi5: gsbi@1a200000 {
 799                         compatible = "qcom,gsbi-v1.0.0";
 800                         cell-index = <5>;
 801                         reg = <0x1a200000 0x100>;
 802                         clocks = <&gcc GSBI5_H_CLK>;
 803                         clock-names = "iface";
 804                         #address-cells = <1>;
 805                         #size-cells = <1>;
 806                         ranges;
 807                         status = "disabled";
 808
 809                         syscon-tcsr = <&tcsr>;
 810
 811                         uart5: serial@1a240000 {
 812                                 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
 813                                 reg = <0x1a240000 0x1000>,
 814                                       <0x1a200000 0x1000>;
 815                                 interrupts = <0 154 0x0>;
 816                                 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
 817                                 clock-names = "core", "iface";
 818                                 status = "disabled";
 819                         };
 820
 821                         i2c@1a280000 {
 822                                 compatible = "qcom,i2c-qup-v1.1.1";
 823                                 reg = <0x1a280000 0x1000>;
 824                                 interrupts = <0 155 0>;
 825
 826                                 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
 827                                 clock-names = "core", "iface";
 828                                 status = "disabled";
 829
 830                                 #address-cells = <1>;
 831                                 #size-cells = <0>;
 832                         };
 833
 834                         spi@1a280000 {
 835                                 compatible = "qcom,spi-qup-v1.1.1";
 836                                 reg = <0x1a280000 0x1000>;
 837                                 interrupts = <0 155 0>;
 838
 839                                 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
 840                                 clock-names = "core", "iface";
 841                                 status = "disabled";
 842
 843                                 #address-cells = <1>;
 844                                 #size-cells = <0>;
 845                         };
 846                 };
 847
 848                 sata_phy: sata-phy@1b400000 {
 849                         compatible = "qcom,ipq806x-sata-phy";
 850                         reg = <0x1b400000 0x200>;
 851
 852                         clocks = <&gcc SATA_PHY_CFG_CLK>;
 853                         clock-names = "cfg";
 854
 855                         #phy-cells = <0>;
 856                         status = "disabled";
 857                 };
 858
 859                 sata@29000000 {
 860                         compatible = "qcom,ipq806x-ahci", "generic-ahci";
 861                         reg = <0x29000000 0x180>;
 862
 863                         ports-implemented = <0x1>;
 864
 865                         interrupts = <0 209 0x0>;
 866
 867                         clocks = <&gcc SFAB_SATA_S_H_CLK>,
 868                                  <&gcc SATA_H_CLK>,
 869                                  <&gcc SATA_A_CLK>,
 870                                  <&gcc SATA_RXOOB_CLK>,
 871                                  <&gcc SATA_PMALIVE_CLK>;
 872                         clock-names = "slave_face", "iface", "core",
 873                                         "rxoob", "pmalive";
 874
 875                         assigned-clocks = <&gcc SATA_RXOOB_CLK>, <&gcc SATA_PMALIVE_CLK>;
 876                         assigned-clock-rates = <100000000>, <100000000>;
 877
 878                         phys = <&sata_phy>;
 879                         phy-names = "sata-phy";
 880                         status = "disabled";
 881                 };
 882
 883                 qcom,ssbi@500000 {
 884                         compatible = "qcom,ssbi";
 885                         reg = <0x00500000 0x1000>;
 886                         qcom,controller-type = "pmic-arbiter";
 887                 };
 888
 889                 gcc: clock-controller@900000 {
 890                         compatible = "qcom,gcc-ipq8064";
 891                         reg = <0x00900000 0x4000>;
 892                         #clock-cells = <1>;
 893                         #reset-cells = <1>;
 894                         #power-domain-cells = <1>;
 895                 };
 896
 897                 tsens: thermal-sensor@900000 {
 898                         compatible = "qcom,ipq8064-tsens";
 899                         reg = <0x900000 0x3680>;
 900                         nvmem-cells = <&tsens_calib>, <&tsens_backup>;
 901                         nvmem-cell-names = "calib", "calib_backup";
 902                         interrupts = <0 178 0>;
 903                         #thermal-sensor-cells = <1>;
 904                 };
 905
 906                 tcsr: syscon@1a400000 {
 907                         compatible = "qcom,tcsr-ipq8064", "syscon";
 908                         reg = <0x1a400000 0x100>;
 909                 };
 910
 911                 lcc: clock-controller@28000000 {
 912                         compatible = "qcom,lcc-ipq8064";
 913                         reg = <0x28000000 0x1000>;
 914                         #clock-cells = <1>;
 915                         #reset-cells = <1>;
 916                 };
 917
 918                 sfpb_mutex_block: syscon@1200600 {
 919                         compatible = "syscon";
 920                         reg = <0x01200600 0x100>;
 921                 };
 922
 923                 hs_phy_0: hs_phy_0 {
 924                         compatible = "qcom,dwc3-hs-usb-phy";
 925                         regmap = <&usb3_0>;
 926                         clocks = <&gcc USB30_0_UTMI_CLK>;
 927                         clock-names = "ref";
 928                         #phy-cells = <0>;
 929                 };
 930
 931                 ss_phy_0: ss_phy_0 {
 932                         compatible = "qcom,dwc3-ss-usb-phy";
 933                         regmap = <&usb3_0>;
 934                         clocks = <&gcc USB30_0_MASTER_CLK>;
 935                         clock-names = "ref";
 936                         #phy-cells = <0>;
 937                 };
 938
 939                 usb3_0: usb3@110f8800 {
 940                         compatible = "qcom,dwc3", "syscon";
 941                         #address-cells = <1>;
 942                         #size-cells = <1>;
 943                         reg = <0x110f8800 0x8000>;
 944                         clocks = <&gcc USB30_0_MASTER_CLK>;
 945                         clock-names = "core";
 946
 947                         ranges;
 948
 949                         resets = <&gcc USB30_0_MASTER_RESET>;
 950                         reset-names = "master";
 951
 952                         status = "disabled";
 953
 954                         dwc3_0: dwc3@11000000 {
 955                                 compatible = "snps,dwc3";
 956                                 reg = <0x11000000 0xcd00>;
 957                                 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 958                                 phys = <&hs_phy_0>, <&ss_phy_0>;
 959                                 phy-names = "usb2-phy", "usb3-phy";
 960                                 dr_mode = "host";
 961                                 snps,dis_u3_susphy_quirk;
 962                         };
 963                 };
 964
 965                 hs_phy_1: hs_phy_1 {
 966                         compatible = "qcom,dwc3-hs-usb-phy";
 967                         regmap = <&usb3_1>;
 968                         clocks = <&gcc USB30_1_UTMI_CLK>;
 969                         clock-names = "ref";
 970                         #phy-cells = <0>;
 971                 };
 972
 973                 ss_phy_1: ss_phy_1 {
 974                         compatible = "qcom,dwc3-ss-usb-phy";
 975                         regmap = <&usb3_1>;
 976                         clocks = <&gcc USB30_1_MASTER_CLK>;
 977                         clock-names = "ref";
 978                         #phy-cells = <0>;
 979                 };
 980
 981                 usb3_1: usb3@100f8800 {
 982                         compatible = "qcom,dwc3", "syscon";
 983                         #address-cells = <1>;
 984                         #size-cells = <1>;
 985                         reg = <0x100f8800 0x8000>;
 986                         clocks = <&gcc USB30_1_MASTER_CLK>;
 987                         clock-names = "core";
 988
 989                         ranges;
 990
 991                         resets = <&gcc USB30_1_MASTER_RESET>;
 992                         reset-names = "master";
 993
 994                         status = "disabled";
 995
 996                         dwc3_1: dwc3@10000000 {
 997                                 compatible = "snps,dwc3";
 998                                 reg = <0x10000000 0xcd00>;
 999                                 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
1000                                 phys = <&hs_phy_1>, <&ss_phy_1>;
1001                                 phy-names = "usb2-phy", "usb3-phy";
1002                                 dr_mode = "host";
1003                                 snps,dis_u3_susphy_quirk;
1004                         };
1005                 };
1006
1007                 pcie0: pci@1b500000 {
1008                         compatible = "qcom,pcie-ipq8064";
1009                         reg = <0x1b500000 0x1000
1010                                0x1b502000 0x80
1011                                0x1b600000 0x100
1012                                0x0ff00000 0x100000>;
1013                         reg-names = "dbi", "elbi", "parf", "config";
1014                         device_type = "pci";
1015                         linux,pci-domain = <0>;
1016                         bus-range = <0x00 0xff>;
1017                         num-lanes = <1>;
1018                         #address-cells = <3>;
1019                         #size-cells = <2>;
1020
1021                         ranges = <0x81000000 0 0x0fe00000 0x0fe00000 0 0x00100000   /* downstream I/O */
1022                                   0x82000000 0 0x08000000 0x08000000 0 0x07e00000>; /* non-prefetchable memory */
1023
1024                         interrupts = <GIC_SPI 35 IRQ_TYPE_NONE>;
1025                         interrupt-names = "msi";
1026                         #interrupt-cells = <1>;
1027                         interrupt-map-mask = <0 0 0 0x7>;
1028                         interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1029                                         <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1030                                         <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1031                                         <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1032
1033                         clocks = <&gcc PCIE_A_CLK>,
1034                                  <&gcc PCIE_H_CLK>,
1035                                  <&gcc PCIE_PHY_CLK>,
1036                                  <&gcc PCIE_AUX_CLK>,
1037                                  <&gcc PCIE_ALT_REF_CLK>;
1038                         clock-names = "core", "iface", "phy", "aux", "ref";
1039
1040                         assigned-clocks = <&gcc PCIE_ALT_REF_CLK>;
1041                         assigned-clock-rates = <100000000>;
1042
1043                         resets = <&gcc PCIE_ACLK_RESET>,
1044                                  <&gcc PCIE_HCLK_RESET>,
1045                                  <&gcc PCIE_POR_RESET>,
1046                                  <&gcc PCIE_PCI_RESET>,
1047                                  <&gcc PCIE_PHY_RESET>,
1048                                  <&gcc PCIE_EXT_RESET>;
1049                         reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
1050
1051                         pinctrl-0 = <&pcie0_pins>;
1052                         pinctrl-names = "default";
1053
1054                         perst-gpios = <&qcom_pinmux 3 GPIO_ACTIVE_LOW>;
1055
1056                         phy-tx0-term-offset = <7>;
1057
1058                         status = "disabled";
1059                 };
1060
1061                 pcie1: pci@1b700000 {
1062                         compatible = "qcom,pcie-ipq8064";
1063                         reg = <0x1b700000 0x1000
1064                                0x1b702000 0x80
1065                                0x1b800000 0x100
1066                                0x31f00000 0x100000>;
1067                         reg-names = "dbi", "elbi", "parf", "config";
1068                         device_type = "pci";
1069                         linux,pci-domain = <1>;
1070                         bus-range = <0x00 0xff>;
1071                         num-lanes = <1>;
1072                         #address-cells = <3>;
1073                         #size-cells = <2>;
1074
1075                         ranges = <0x81000000 0 0x31e00000 0x31e00000 0 0x00100000   /* downstream I/O */
1076                                   0x82000000 0 0x2e000000 0x2e000000 0 0x03e00000>; /* non-prefetchable memory */
1077
1078                         interrupts = <GIC_SPI 57 IRQ_TYPE_NONE>;
1079                         interrupt-names = "msi";
1080                         #interrupt-cells = <1>;
1081                         interrupt-map-mask = <0 0 0 0x7>;
1082                         interrupt-map = <0 0 0 1 &intc 0 58 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1083                                         <0 0 0 2 &intc 0 59 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1084                                         <0 0 0 3 &intc 0 60 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1085                                         <0 0 0 4 &intc 0 61 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1086
1087                         clocks = <&gcc PCIE_1_A_CLK>,
1088                                  <&gcc PCIE_1_H_CLK>,
1089                                  <&gcc PCIE_1_PHY_CLK>,
1090                                  <&gcc PCIE_1_AUX_CLK>,
1091                                  <&gcc PCIE_1_ALT_REF_CLK>;
1092                         clock-names = "core", "iface", "phy", "aux", "ref";
1093
1094                         assigned-clocks = <&gcc PCIE_1_ALT_REF_CLK>;
1095                         assigned-clock-rates = <100000000>;
1096
1097                         resets = <&gcc PCIE_1_ACLK_RESET>,
1098                                  <&gcc PCIE_1_HCLK_RESET>,
1099                                  <&gcc PCIE_1_POR_RESET>,
1100                                  <&gcc PCIE_1_PCI_RESET>,
1101                                  <&gcc PCIE_1_PHY_RESET>,
1102                                  <&gcc PCIE_1_EXT_RESET>;
1103                         reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
1104
1105                         pinctrl-0 = <&pcie1_pins>;
1106                         pinctrl-names = "default";
1107
1108                         perst-gpios = <&qcom_pinmux 48 GPIO_ACTIVE_LOW>;
1109
1110                         phy-tx0-term-offset = <7>;
1111
1112                         status = "disabled";
1113                 };
1114
1115                 pcie2: pci@1b900000 {
1116                         compatible = "qcom,pcie-ipq8064";
1117                         reg = <0x1b900000 0x1000
1118                                0x1b902000 0x80
1119                                0x1ba00000 0x100
1120                                0x35f00000 0x100000>;
1121                         reg-names = "dbi", "elbi", "parf", "config";
1122                         device_type = "pci";
1123                         linux,pci-domain = <2>;
1124                         bus-range = <0x00 0xff>;
1125                         num-lanes = <1>;
1126                         #address-cells = <3>;
1127                         #size-cells = <2>;
1128
1129                         ranges = <0x81000000 0 0x35e00000 0x35e00000 0 0x00100000   /* downstream I/O */
1130                                   0x82000000 0 0x32000000 0x32000000 0 0x03e00000>; /* non-prefetchable memory */
1131
1132                         interrupts = <GIC_SPI 71 IRQ_TYPE_NONE>;
1133                         interrupt-names = "msi";
1134                         #interrupt-cells = <1>;
1135                         interrupt-map-mask = <0 0 0 0x7>;
1136                         interrupt-map = <0 0 0 1 &intc 0 72 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1137                                         <0 0 0 2 &intc 0 73 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1138                                         <0 0 0 3 &intc 0 74 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1139                                         <0 0 0 4 &intc 0 75 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1140
1141                         clocks = <&gcc PCIE_2_A_CLK>,
1142                                  <&gcc PCIE_2_H_CLK>,
1143                                  <&gcc PCIE_2_PHY_CLK>,
1144                                  <&gcc PCIE_2_AUX_CLK>,
1145                                  <&gcc PCIE_2_ALT_REF_CLK>;
1146                         clock-names = "core", "iface", "phy", "aux", "ref";
1147
1148                         assigned-clocks = <&gcc PCIE_2_ALT_REF_CLK>;
1149                         assigned-clock-rates = <100000000>;
1150
1151                         resets = <&gcc PCIE_2_ACLK_RESET>,
1152                                  <&gcc PCIE_2_HCLK_RESET>,
1153                                  <&gcc PCIE_2_POR_RESET>,
1154                                  <&gcc PCIE_2_PCI_RESET>,
1155                                  <&gcc PCIE_2_PHY_RESET>,
1156                                  <&gcc PCIE_2_EXT_RESET>;
1157                         reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
1158
1159                         pinctrl-0 = <&pcie2_pins>;
1160                         pinctrl-names = "default";
1161
1162                         perst-gpios = <&qcom_pinmux 63 GPIO_ACTIVE_LOW>;
1163
1164                         phy-tx0-term-offset = <7>;
1165
1166                         status = "disabled";
1167                 };
1168
1169                 adm_dma: dma@18300000 {
1170                         compatible = "qcom,adm";
1171                         reg = <0x18300000 0x100000>;
1172                         interrupts = <0 170 0>;
1173                         #dma-cells = <1>;
1174
1175                         clocks = <&gcc ADM0_CLK>, <&gcc ADM0_PBUS_CLK>;
1176                         clock-names = "core", "iface";
1177
1178                         resets = <&gcc ADM0_RESET>,
1179                                  <&gcc ADM0_PBUS_RESET>,
1180                                  <&gcc ADM0_C0_RESET>,
1181                                  <&gcc ADM0_C1_RESET>,
1182                                  <&gcc ADM0_C2_RESET>;
1183                         reset-names = "clk", "pbus", "c0", "c1", "c2";
1184                         qcom,ee = <0>;
1185
1186                         status = "disabled";
1187                 };
1188
1189                 nand@1ac00000 {
1190                         compatible = "qcom,ipq806x-nand";
1191                         reg = <0x1ac00000 0x800>;
1192
1193                         clocks = <&gcc EBI2_CLK>,
1194                                  <&gcc EBI2_AON_CLK>;
1195                         clock-names = "core", "aon";
1196
1197                         dmas = <&adm_dma 3>;
1198                         dma-names = "rxtx";
1199                         qcom,cmd-crci = <15>;
1200                         qcom,data-crci = <3>;
1201
1202                         status = "disabled";
1203
1204                         #address-cells = <1>;
1205                         #size-cells = <0>;
1206                 };
1207
1208                 nss_common: syscon@03000000 {
1209                         compatible = "syscon";
1210                         reg = <0x03000000 0x0000FFFF>;
1211                 };
1212
1213                 qsgmii_csr: syscon@1bb00000 {
1214                         compatible = "syscon";
1215                         reg = <0x1bb00000 0x000001FF>;
1216                 };
1217
1218                 stmmac_axi_setup: stmmac-axi-config {
1219                         snps,wr_osr_lmt = <7>;
1220                         snps,rd_osr_lmt = <7>;
1221                         snps,blen = <16 0 0 0 0 0 0>;
1222                 };
1223
1224                 gmac0: ethernet@37000000 {
1225                         device_type = "network";
1226                         compatible = "qcom,ipq806x-gmac";
1227                         reg = <0x37000000 0x200000>;
1228                         interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
1229                         interrupt-names = "macirq";
1230
1231                         snps,axi-config = <&stmmac_axi_setup>;
1232                         snps,pbl = <32>;
1233                         snps,aal = <1>;
1234
1235                         qcom,nss-common = <&nss_common>;
1236                         qcom,qsgmii-csr = <&qsgmii_csr>;
1237
1238                         clocks = <&gcc GMAC_CORE1_CLK>;
1239                         clock-names = "stmmaceth";
1240
1241                         resets = <&gcc GMAC_CORE1_RESET>;
1242                         reset-names = "stmmaceth";
1243
1244                         status = "disabled";
1245                 };
1246
1247                 gmac1: ethernet@37200000 {
1248                         device_type = "network";
1249                         compatible = "qcom,ipq806x-gmac";
1250                         reg = <0x37200000 0x200000>;
1251                         interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
1252                         interrupt-names = "macirq";
1253
1254                         snps,axi-config = <&stmmac_axi_setup>;
1255                         snps,pbl = <32>;
1256                         snps,aal = <1>;
1257
1258                         qcom,nss-common = <&nss_common>;
1259                         qcom,qsgmii-csr = <&qsgmii_csr>;
1260
1261                         clocks = <&gcc GMAC_CORE2_CLK>;
1262                         clock-names = "stmmaceth";
1263
1264                         resets = <&gcc GMAC_CORE2_RESET>;
1265                         reset-names = "stmmaceth";
1266
1267                         status = "disabled";
1268                 };
1269
1270                 gmac2: ethernet@37400000 {
1271                         device_type = "network";
1272                         compatible = "qcom,ipq806x-gmac";
1273                         reg = <0x37400000 0x200000>;
1274                         interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
1275                         interrupt-names = "macirq";
1276
1277                         snps,axi-config = <&stmmac_axi_setup>;
1278                         snps,pbl = <32>;
1279                         snps,aal = <1>;
1280
1281                         qcom,nss-common = <&nss_common>;
1282                         qcom,qsgmii-csr = <&qsgmii_csr>;
1283
1284                         clocks = <&gcc GMAC_CORE3_CLK>;
1285                         clock-names = "stmmaceth";
1286
1287                         resets = <&gcc GMAC_CORE3_RESET>;
1288                         reset-names = "stmmaceth";
1289
1290                         status = "disabled";
1291                 };
1292
1293                 gmac3: ethernet@37600000 {
1294                         device_type = "network";
1295                         compatible = "qcom,ipq806x-gmac";
1296                         reg = <0x37600000 0x200000>;
1297                         interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
1298                         interrupt-names = "macirq";
1299
1300                         snps,axi-config = <&stmmac_axi_setup>;
1301                         snps,pbl = <32>;
1302                         snps,aal = <1>;
1303
1304                         qcom,nss-common = <&nss_common>;
1305                         qcom,qsgmii-csr = <&qsgmii_csr>;
1306
1307                         clocks = <&gcc GMAC_CORE4_CLK>;
1308                         clock-names = "stmmaceth";
1309
1310                         resets = <&gcc GMAC_CORE4_RESET>;
1311                         reset-names = "stmmaceth";
1312
1313                         status = "disabled";
1314                 };
1315
1316                 /* Temporary fixed regulator */
1317                 vsdcc_fixed: vsdcc-regulator {
1318                         compatible = "regulator-fixed";
1319                         regulator-name = "SDCC Power";
1320                         regulator-min-microvolt = <3300000>;
1321                         regulator-max-microvolt = <3300000>;
1322                         regulator-always-on;
1323                 };
1324
1325                 sdcc1bam:dma@12402000 {
1326                         compatible = "qcom,bam-v1.3.0";
1327                         reg = <0x12402000 0x8000>;
1328                         interrupts = <0 98 0>;
1329                         clocks = <&gcc SDC1_H_CLK>;
1330                         clock-names = "bam_clk";
1331                         #dma-cells = <1>;
1332                         qcom,ee = <0>;
1333                 };
1334
1335                 sdcc3bam:dma@12182000 {
1336                         compatible = "qcom,bam-v1.3.0";
1337                         reg = <0x12182000 0x8000>;
1338                         interrupts = <0 96 0>;
1339                         clocks = <&gcc SDC3_H_CLK>;
1340                         clock-names = "bam_clk";
1341                         #dma-cells = <1>;
1342                         qcom,ee = <0>;
1343                 };
1344
1345                 amba {
1346                         compatible = "arm,amba-bus";
1347                         #address-cells = <1>;
1348                         #size-cells = <1>;
1349                         ranges;
1350                         sdcc1: sdcc@12400000 {
1351                                 status          = "disabled";
1352                                 compatible      = "arm,pl18x", "arm,primecell";
1353                                 arm,primecell-periphid = <0x00051180>;
1354                                 reg             = <0x12400000 0x2000>;
1355                                 interrupts      = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
1356                                 interrupt-names = "cmd_irq";
1357                                 clocks          = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
1358                                 clock-names     = "mclk", "apb_pclk";
1359                                 bus-width       = <8>;
1360                                 max-frequency   = <96000000>;
1361                                 non-removable;
1362                                 cap-sd-highspeed;
1363                                 cap-mmc-highspeed;
1364                                 vmmc-supply = <&vsdcc_fixed>;
1365                                 dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
1366                                 dma-names = "tx", "rx";
1367                         };
1368
1369                         sdcc3: sdcc@12180000 {
1370                                 compatible      = "arm,pl18x", "arm,primecell";
1371                                 arm,primecell-periphid = <0x00051180>;
1372                                 status          = "disabled";
1373                                 reg             = <0x12180000 0x2000>;
1374                                 interrupts      = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
1375                                 interrupt-names = "cmd_irq";
1376                                 clocks          = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
1377                                 clock-names     = "mclk", "apb_pclk";
1378                                 bus-width       = <8>;
1379                                 cap-sd-highspeed;
1380                                 cap-mmc-highspeed;
1381                                 max-frequency   = <192000000>;
1382                                 #mmc-ddr-1_8v;
1383                                 sd-uhs-sdr104;
1384                                 sd-uhs-ddr50;
1385                                 vqmmc-supply = <&vsdcc_fixed>;
1386                                 dmas = <&sdcc3bam 2>, <&sdcc3bam 1>;
1387                                 dma-names = "tx", "rx";
1388                         };
1389                 };
1390         };
1391
1392         sfpb_mutex: sfpb-mutex {
1393                 compatible = "qcom,sfpb-mutex";
1394                 syscon = <&sfpb_mutex_block 4 4>;
1395
1396                 #hwlock-cells = <1>;
1397         };
1398
1399         smem {
1400                 compatible = "qcom,smem";
1401                 memory-region = <&smem>;
1402                 hwlocks = <&sfpb_mutex 3>;
1403         };
1404 };