target/linux/ipq806x/files-4.19/arch/arm/boot/dts/qcom-ipq8064.dtsi

   1 /dts-v1/;
   2
   3 #include "skeleton.dtsi"
   4 #include <dt-bindings/clock/qcom,gcc-ipq806x.h>
   5 #include <dt-bindings/mfd/qcom-rpm.h>
   6 #include <dt-bindings/clock/qcom,rpmcc.h>
   7 #include <dt-bindings/clock/qcom,lcc-ipq806x.h>
   8 #include <dt-bindings/soc/qcom,gsbi.h>
   9 #include <dt-bindings/reset/qcom,gcc-ipq806x.h>
  10 #include <dt-bindings/interrupt-controller/arm-gic.h>
  11 #include <dt-bindings/gpio/gpio.h>
  12
  13 / {
  14         model = "Qualcomm IPQ8064";
  15         compatible = "qcom,ipq8064";
  16         interrupt-parent = <&intc>;
  17
  18         cpus {
  19                 #address-cells = <1>;
  20                 #size-cells = <0>;
  21
  22                 cpu0: cpu@0 {
  23                         compatible = "qcom,krait";
  24                         enable-method = "qcom,kpss-acc-v1";
  25                         device_type = "cpu";
  26                         reg = <0>;
  27                         next-level-cache = <&L2>;
  28                         qcom,acc = <&acc0>;
  29                         qcom,saw = <&saw0>;
  30                         clocks = <&kraitcc 0>, <&kraitcc 4>;
  31                         clock-names = "cpu", "l2";
  32                         clock-latency = <100000>;
  33                         cpu-supply = <&smb208_s2a>;
  34                         voltage-tolerance = <5>;
  35                         cooling-min-state = <0>;
  36                         cooling-max-state = <10>;
  37                         #cooling-cells = <2>;
  38                         cpu-idle-states = <&CPU_SPC>;
  39                 };
  40
  41                 cpu1: cpu@1 {
  42                         compatible = "qcom,krait";
  43                         enable-method = "qcom,kpss-acc-v1";
  44                         device_type = "cpu";
  45                         reg = <1>;
  46                         next-level-cache = <&L2>;
  47                         qcom,acc = <&acc1>;
  48                         qcom,saw = <&saw1>;
  49                         clocks = <&kraitcc 1>, <&kraitcc 4>;
  50                         clock-names = "cpu", "l2";
  51                         clock-latency = <100000>;
  52                         cpu-supply = <&smb208_s2b>;
  53                         cooling-min-state = <0>;
  54                         cooling-max-state = <10>;
  55                         #cooling-cells = <2>;
  56                         cpu-idle-states = <&CPU_SPC>;
  57                 };
  58
  59                 L2: l2-cache {
  60                         compatible = "cache";
  61                         cache-level = <2>;
  62                         qcom,saw = <&saw_l2>;
  63                 };
  64
  65                 qcom,l2 {
  66                         qcom,l2-rates = <384000000 1000000000 1200000000>;
  67                 };
  68
  69                 idle-states {
  70                         CPU_SPC: spc {
  71                                 compatible = "qcom,idle-state-spc",
  72                                                 "arm,idle-state";
  73                                 status = "okay";
  74                                 entry-latency-us = <400>;
  75                                 exit-latency-us = <900>;
  76                                 min-residency-us = <3000>;
  77                         };
  78                 };
  79         };
  80
  81         thermal-zones {
  82                 tsens_tz_sensor0 {
  83                         polling-delay-passive = <0>;
  84                         polling-delay = <0>;
  85                         thermal-sensors = <&tsens 0>;
  86
  87                         trips {
  88                                 cpu-critical-hi {
  89                                         temperature = <125000>;
  90                                         hysteresis = <2000>;
  91                                         type = "critical_high";
  92                                 };
  93
  94                                 cpu-config-hi {
  95                                         temperature = <105000>;
  96                                         hysteresis = <2000>;
  97                                         type = "configurable_hi";
  98                                 };
  99
 100                                 cpu-config-lo {
 101                                         temperature = <95000>;
 102                                         hysteresis = <2000>;
 103                                         type = "configurable_lo";
 104                                 };
 105
 106                                 cpu-critical-low {
 107                                         temperature = <0>;
 108                                         hysteresis = <2000>;
 109                                         type = "critical_low";
 110                                 };
 111                         };
 112                 };
 113
 114                 tsens_tz_sensor1 {
 115                         polling-delay-passive = <0>;
 116                         polling-delay = <0>;
 117                         thermal-sensors = <&tsens 1>;
 118
 119                         trips {
 120                                 cpu-critical-hi {
 121                                         temperature = <125000>;
 122                                         hysteresis = <2000>;
 123                                         type = "critical_high";
 124                                 };
 125
 126                                 cpu-config-hi {
 127                                         temperature = <105000>;
 128                                         hysteresis = <2000>;
 129                                         type = "configurable_hi";
 130                                 };
 131
 132                                 cpu-config-lo {
 133                                         temperature = <95000>;
 134                                         hysteresis = <2000>;
 135                                         type = "configurable_lo";
 136                                 };
 137
 138                                 cpu-critical-low {
 139                                         temperature = <0>;
 140                                         hysteresis = <2000>;
 141                                         type = "critical_low";
 142                                 };
 143                         };
 144                 };
 145
 146                 tsens_tz_sensor2 {
 147                         polling-delay-passive = <0>;
 148                         polling-delay = <0>;
 149                         thermal-sensors = <&tsens 2>;
 150
 151                         trips {
 152                                 cpu-critical-hi {
 153                                         temperature = <125000>;
 154                                         hysteresis = <2000>;
 155                                         type = "critical_high";
 156                                 };
 157
 158                                 cpu-config-hi {
 159                                         temperature = <105000>;
 160                                         hysteresis = <2000>;
 161                                         type = "configurable_hi";
 162                                 };
 163
 164                                 cpu-config-lo {
 165                                         temperature = <95000>;
 166                                         hysteresis = <2000>;
 167                                         type = "configurable_lo";
 168                                 };
 169
 170                                 cpu-critical-low {
 171                                         temperature = <0>;
 172                                         hysteresis = <2000>;
 173                                         type = "critical_low";
 174                                 };
 175                         };
 176                 };
 177
 178                 tsens_tz_sensor3 {
 179                         polling-delay-passive = <0>;
 180                         polling-delay = <0>;
 181                         thermal-sensors = <&tsens 3>;
 182
 183                         trips {
 184                                 cpu-critical-hi {
 185                                         temperature = <125000>;
 186                                         hysteresis = <2000>;
 187                                         type = "critical_high";
 188                                 };
 189
 190                                 cpu-config-hi {
 191                                         temperature = <105000>;
 192                                         hysteresis = <2000>;
 193                                         type = "configurable_hi";
 194                                 };
 195
 196                                 cpu-config-lo {
 197                                         temperature = <95000>;
 198                                         hysteresis = <2000>;
 199                                         type = "configurable_lo";
 200                                 };
 201
 202                                 cpu-critical-low {
 203                                         temperature = <0>;
 204                                         hysteresis = <2000>;
 205                                         type = "critical_low";
 206                                 };
 207                         };
 208                 };
 209
 210                 tsens_tz_sensor4 {
 211                         polling-delay-passive = <0>;
 212                         polling-delay = <0>;
 213                         thermal-sensors = <&tsens 4>;
 214
 215                         trips {
 216                                 cpu-critical-hi {
 217                                         temperature = <125000>;
 218                                         hysteresis = <2000>;
 219                                         type = "critical_high";
 220                                 };
 221
 222                                 cpu-config-hi {
 223                                         temperature = <105000>;
 224                                         hysteresis = <2000>;
 225                                         type = "configurable_hi";
 226                                 };
 227
 228                                 cpu-config-lo {
 229                                         temperature = <95000>;
 230                                         hysteresis = <2000>;
 231                                         type = "configurable_lo";
 232                                 };
 233
 234                                 cpu-critical-low {
 235                                         temperature = <0>;
 236                                         hysteresis = <2000>;
 237                                         type = "critical_low";
 238                                 };
 239                         };
 240                 };
 241
 242                 tsens_tz_sensor5 {
 243                         polling-delay-passive = <0>;
 244                         polling-delay = <0>;
 245                         thermal-sensors = <&tsens 5>;
 246
 247                         trips {
 248                                 cpu-critical-hi {
 249                                         temperature = <125000>;
 250                                         hysteresis = <2000>;
 251                                         type = "critical_high";
 252                                 };
 253
 254                                 cpu-config-hi {
 255                                         temperature = <105000>;
 256                                         hysteresis = <2000>;
 257                                         type = "configurable_hi";
 258                                 };
 259
 260                                 cpu-config-lo {
 261                                         temperature = <95000>;
 262                                         hysteresis = <2000>;
 263                                         type = "configurable_lo";
 264                                 };
 265
 266                                 cpu-critical-low {
 267                                         temperature = <0>;
 268                                         hysteresis = <2000>;
 269                                         type = "critical_low";
 270                                 };
 271                         };
 272                 };
 273
 274                 tsens_tz_sensor6 {
 275                         polling-delay-passive = <0>;
 276                         polling-delay = <0>;
 277                         thermal-sensors = <&tsens 6>;
 278
 279                         trips {
 280                                 cpu-critical-hi {
 281                                         temperature = <125000>;
 282                                         hysteresis = <2000>;
 283                                         type = "critical_high";
 284                                 };
 285
 286                                 cpu-config-hi {
 287                                         temperature = <105000>;
 288                                         hysteresis = <2000>;
 289                                         type = "configurable_hi";
 290                                 };
 291
 292                                 cpu-config-lo {
 293                                         temperature = <95000>;
 294                                         hysteresis = <2000>;
 295                                         type = "configurable_lo";
 296                                 };
 297
 298                                 cpu-critical-low {
 299                                         temperature = <0>;
 300                                         hysteresis = <2000>;
 301                                         type = "critical_low";
 302                                 };
 303                         };
 304                 };
 305
 306                 tsens_tz_sensor7 {
 307                         polling-delay-passive = <0>;
 308                         polling-delay = <0>;
 309                         thermal-sensors = <&tsens 7>;
 310
 311                         trips {
 312                                 cpu-critical-hi {
 313                                         temperature = <125000>;
 314                                         hysteresis = <2000>;
 315                                         type = "critical_high";
 316                                 };
 317
 318                                 cpu-config-hi {
 319                                         temperature = <105000>;
 320                                         hysteresis = <2000>;
 321                                         type = "configurable_hi";
 322                                 };
 323
 324                                 cpu-config-lo {
 325                                         temperature = <95000>;
 326                                         hysteresis = <2000>;
 327                                         type = "configurable_lo";
 328                                 };
 329
 330                                 cpu-critical-low {
 331                                         temperature = <0>;
 332                                         hysteresis = <2000>;
 333                                         type = "critical_low";
 334                                 };
 335                         };
 336                 };
 337
 338                 tsens_tz_sensor8 {
 339                         polling-delay-passive = <0>;
 340                         polling-delay = <0>;
 341                         thermal-sensors = <&tsens 8>;
 342
 343                         trips {
 344                                 cpu-critical-hi {
 345                                         temperature = <125000>;
 346                                         hysteresis = <2000>;
 347                                         type = "critical_high";
 348                                 };
 349
 350                                 cpu-config-hi {
 351                                         temperature = <105000>;
 352                                         hysteresis = <2000>;
 353                                         type = "configurable_hi";
 354                                 };
 355
 356                                 cpu-config-lo {
 357                                         temperature = <95000>;
 358                                         hysteresis = <2000>;
 359                                         type = "configurable_lo";
 360                                 };
 361
 362                                 cpu-critical-low {
 363                                         temperature = <0>;
 364                                         hysteresis = <2000>;
 365                                         type = "critical_low";
 366                                 };
 367                         };
 368                 };
 369
 370                 tsens_tz_sensor9 {
 371                         polling-delay-passive = <0>;
 372                         polling-delay = <0>;
 373                         thermal-sensors = <&tsens 9>;
 374
 375                         trips {
 376                                 cpu-critical-hi {
 377                                         temperature = <125000>;
 378                                         hysteresis = <2000>;
 379                                         type = "critical_high";
 380                                 };
 381
 382                                 cpu-config-hi {
 383                                         temperature = <105000>;
 384                                         hysteresis = <2000>;
 385                                         type = "configurable_hi";
 386                                 };
 387
 388                                 cpu-config-lo {
 389                                         temperature = <95000>;
 390                                         hysteresis = <2000>;
 391                                         type = "configurable_lo";
 392                                 };
 393
 394                                 cpu-critical-low {
 395                                         temperature = <0>;
 396                                         hysteresis = <2000>;
 397                                         type = "critical_low";
 398                                 };
 399                         };
 400                 };
 401
 402                 tsens_tz_sensor10 {
 403                         polling-delay-passive = <0>;
 404                         polling-delay = <0>;
 405                         thermal-sensors = <&tsens 10>;
 406
 407                         trips {
 408                                 cpu-critical-hi {
 409                                         temperature = <125000>;
 410                                         hysteresis = <2000>;
 411                                         type = "critical_high";
 412                                 };
 413
 414                                 cpu-config-hi {
 415                                         temperature = <105000>;
 416                                         hysteresis = <2000>;
 417                                         type = "configurable_hi";
 418                                 };
 419
 420                                 cpu-config-lo {
 421                                         temperature = <95000>;
 422                                         hysteresis = <2000>;
 423                                         type = "configurable_lo";
 424                                 };
 425
 426                                 cpu-critical-low {
 427                                         temperature = <0>;
 428                                         hysteresis = <2000>;
 429                                         type = "critical_low";
 430                                 };
 431                         };
 432                 };
 433         };
 434
 435         cpu-pmu {
 436                 compatible = "qcom,krait-pmu";
 437                 interrupts = <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |
 438                                           IRQ_TYPE_LEVEL_HIGH)>;
 439         };
 440
 441         reserved-memory {
 442                 #address-cells = <1>;
 443                 #size-cells = <1>;
 444                 ranges;
 445
 446                 nss@40000000 {
 447                         reg = <0x40000000 0x1000000>;
 448                         no-map;
 449                 };
 450
 451                 smem: smem@41000000 {
 452                         reg = <0x41000000 0x200000>;
 453                         no-map;
 454                 };
 455         };
 456
 457         clocks {
 458                 cxo_board {
 459                         compatible = "fixed-clock";
 460                         #clock-cells = <0>;
 461                         clock-frequency = <25000000>;
 462                 };
 463
 464                 pxo_board {
 465                         compatible = "fixed-clock";
 466                         #clock-cells = <0>;
 467                         clock-frequency = <25000000>;
 468                 };
 469
 470                 sleep_clk: sleep_clk {
 471                         compatible = "fixed-clock";
 472                         clock-frequency = <32768>;
 473                         #clock-cells = <0>;
 474                 };
 475         };
 476
 477         firmware {
 478                 scm {
 479                         compatible = "qcom,scm-ipq806x";
 480                 };
 481         };
 482
 483         kraitcc: clock-controller {
 484                 compatible = "qcom,krait-cc-v1";
 485                 #clock-cells = <1>;
 486         };
 487
 488         qcom,pvs {
 489                 qcom,pvs-format-a;
 490                 qcom,speed0-pvs0-bin-v0 =
 491                         < 1400000000 1250000 >,
 492                         < 1200000000 1200000 >,
 493                         < 1000000000 1150000 >,
 494                          < 800000000 1100000 >,
 495                          < 600000000 1050000 >,
 496                          < 384000000 1000000 >;
 497
 498                 qcom,speed0-pvs1-bin-v0 =
 499                         < 1400000000 1175000 >,
 500                         < 1200000000 1125000 >,
 501                         < 1000000000 1075000 >,
 502                          < 800000000 1025000 >,
 503                          < 600000000  975000 >,
 504                          < 384000000  925000 >;
 505
 506                 qcom,speed0-pvs2-bin-v0 =
 507                         < 1400000000 1125000 >,
 508                         < 1200000000 1075000 >,
 509                         < 1000000000 1025000 >,
 510                          < 800000000  995000 >,
 511                          < 600000000  925000 >,
 512                          < 384000000  875000 >;
 513
 514                 qcom,speed0-pvs3-bin-v0 =
 515                         < 1400000000 1050000 >,
 516                         < 1200000000 1000000 >,
 517                         < 1000000000  950000 >,
 518                          < 800000000  900000 >,
 519                          < 600000000  850000 >,
 520                          < 384000000  800000 >;
 521         };
 522
 523         soc: soc {
 524                 #address-cells = <1>;
 525                 #size-cells = <1>;
 526                 ranges;
 527                 compatible = "simple-bus";
 528
 529                 lpass@28100000 {
 530                         compatible = "qcom,lpass-cpu";
 531                         status = "disabled";
 532                         clocks = <&lcc AHBIX_CLK>,
 533                                         <&lcc MI2S_OSR_CLK>,
 534                                         <&lcc MI2S_BIT_CLK>;
 535                         clock-names = "ahbix-clk",
 536                                         "mi2s-osr-clk",
 537                                         "mi2s-bit-clk";
 538                         interrupts = <GIC_SPI 85 IRQ_TYPE_EDGE_RISING>;
 539                         interrupt-names = "lpass-irq-lpaif";
 540                         reg = <0x28100000 0x10000>;
 541                         reg-names = "lpass-lpaif";
 542                 };
 543
 544                 qfprom: qfprom@700000 {
 545                         compatible = "qcom,qfprom", "syscon";
 546                         reg = <0x700000 0x1000>;
 547                         #address-cells = <1>;
 548                         #size-cells = <1>;
 549                         status = "okay";
 550                         tsens_calib: calib@400 {
 551                                 reg = <0x400 0x10>;
 552                         };
 553                         tsens_backup: backup@410 {
 554                                 reg = <0x410 0x10>;
 555                         };
 556                 };
 557
 558                 rpm@108000 {
 559                         compatible = "qcom,rpm-ipq8064";
 560                         reg = <0x108000 0x1000>;
 561                         qcom,ipc = <&l2cc 0x8 2>;
 562
 563                         interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
 564                                      <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
 565                                      <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 566                         interrupt-names = "ack",
 567                                           "err",
 568                                           "wakeup";
 569
 570                         clocks = <&gcc RPM_MSG_RAM_H_CLK>;
 571                         clock-names = "ram";
 572
 573                         #address-cells = <1>;
 574                         #size-cells = <0>;
 575
 576                         rpmcc: clock-controller {
 577                                 compatible      = "qcom,rpmcc-ipq806x", "qcom,rpmcc";
 578                                 #clock-cells = <1>;
 579                         };
 580
 581                         regulators {
 582                                 compatible = "qcom,rpm-smb208-regulators";
 583
 584                                 smb208_s1a: s1a {
 585                                         regulator-min-microvolt = <1050000>;
 586                                         regulator-max-microvolt = <1150000>;
 587
 588                                         qcom,switch-mode-frequency = <1200000>;
 589
 590                                 };
 591
 592                                 smb208_s1b: s1b {
 593                                         regulator-min-microvolt = <1050000>;
 594                                         regulator-max-microvolt = <1150000>;
 595
 596                                         qcom,switch-mode-frequency = <1200000>;
 597                                 };
 598
 599                                 smb208_s2a: s2a {
 600                                         regulator-min-microvolt = < 800000>;
 601                                         regulator-max-microvolt = <1250000>;
 602
 603                                         qcom,switch-mode-frequency = <1200000>;
 604                                 };
 605
 606                                 smb208_s2b: s2b {
 607                                         regulator-min-microvolt = < 800000>;
 608                                         regulator-max-microvolt = <1250000>;
 609
 610                                         qcom,switch-mode-frequency = <1200000>;
 611                                 };
 612                         };
 613                 };
 614
 615                 rng@1a500000 {
 616                         compatible = "qcom,prng";
 617                         reg = <0x1a500000 0x200>;
 618                         clocks = <&gcc PRNG_CLK>;
 619                         clock-names = "core";
 620                 };
 621
 622                 qcom_pinmux: pinmux@800000 {
 623                         compatible = "qcom,ipq8064-pinctrl";
 624                         reg = <0x800000 0x4000>;
 625
 626                         gpio-controller;
 627                         #gpio-cells = <2>;
 628                         interrupt-controller;
 629                         #interrupt-cells = <2>;
 630                         interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 631
 632                         pcie0_pins: pcie0_pinmux {
 633                                 mux {
 634                                         pins = "gpio3";
 635                                         function = "pcie1_rst";
 636                                         drive-strength = <2>;
 637                                         bias-disable;
 638                                 };
 639                         };
 640
 641                         pcie1_pins: pcie1_pinmux {
 642                                 mux {
 643                                         pins = "gpio48";
 644                                         function = "pcie2_rst";
 645                                         drive-strength = <2>;
 646                                         bias-disable;
 647                                 };
 648                         };
 649
 650                         pcie2_pins: pcie2_pinmux {
 651                                 mux {
 652                                         pins = "gpio63";
 653                                         function = "pcie3_rst";
 654                                         drive-strength = <2>;
 655                                         bias-disable;
 656                                         output-low;
 657                                 };
 658                         };
 659                 };
 660
 661                 intc: interrupt-controller@2000000 {
 662                         compatible = "qcom,msm-qgic2";
 663                         interrupt-controller;
 664                         #interrupt-cells = <3>;
 665                         reg = <0x02000000 0x1000>,
 666                               <0x02002000 0x1000>;
 667                 };
 668
 669                 timer@200a000 {
 670                         compatible = "qcom,kpss-timer", "qcom,msm-timer";
 671                         interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(2) |
 672                                                  IRQ_TYPE_EDGE_RISING)>,
 673                                      <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(2) |
 674                                                  IRQ_TYPE_EDGE_RISING)>,
 675                                      <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(2) |
 676                                                  IRQ_TYPE_EDGE_RISING)>,
 677                                      <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(2) |
 678                                                  IRQ_TYPE_EDGE_RISING)>,
 679                                      <GIC_PPI 5 (GIC_CPU_MASK_SIMPLE(2) |
 680                                                  IRQ_TYPE_EDGE_RISING)>;
 681                         reg = <0x0200a000 0x100>;
 682                         clock-frequency = <25000000>,
 683                                           <32768>;
 684                         clocks = <&sleep_clk>;
 685                         clock-names = "sleep";
 686                         cpu-offset = <0x80000>;
 687                 };
 688
 689                 acc0: clock-controller@2088000 {
 690                         compatible = "qcom,kpss-acc-v1";
 691                         reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
 692                         clock-output-names = "acpu0_aux";
 693                 };
 694
 695                 acc1: clock-controller@2098000 {
 696                         compatible = "qcom,kpss-acc-v1";
 697                         reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
 698                         clock-output-names = "acpu1_aux";
 699                 };
 700
 701                 l2cc: clock-controller@2011000 {
 702                         compatible = "qcom,kpss-gcc", "syscon";
 703                         reg = <0x2011000 0x1000>;
 704                         clock-output-names = "acpu_l2_aux";
 705                 };
 706
 707                 saw0: regulator@2089000 {
 708                         compatible = "qcom,saw2", "qcom,apq8064-saw2-v1.1-cpu", "syscon";
 709                         reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
 710                         regulator;
 711                 };
 712
 713                 saw1: regulator@2099000 {
 714                         compatible = "qcom,saw2", "qcom,apq8064-saw2-v1.1-cpu", "syscon";
 715                         reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
 716                         regulator;
 717                 };
 718
 719                 saw_l2: regulator@02012000 {
 720                         compatible = "qcom,saw2", "syscon";
 721                         reg = <0x02012000 0x1000>;
 722                         regulator;
 723                 };
 724
 725                 sic_non_secure: sic-non-secure@12100000 {
 726                         compatible = "syscon";
 727                         reg = <0x12100000 0x10000>;
 728                 };
 729
 730                 gsbi2: gsbi@12480000 {
 731                         compatible = "qcom,gsbi-v1.0.0";
 732                         cell-index = <2>;
 733                         reg = <0x12480000 0x100>;
 734                         clocks = <&gcc GSBI2_H_CLK>;
 735                         clock-names = "iface";
 736                         #address-cells = <1>;
 737                         #size-cells = <1>;
 738                         ranges;
 739                         status = "disabled";
 740
 741                         syscon-tcsr = <&tcsr>;
 742
 743                         uart2: serial@12490000 {
 744                                 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
 745                                 reg = <0x12490000 0x1000>,
 746                                       <0x12480000 0x1000>;
 747                                 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
 748                                 clocks = <&gcc GSBI2_UART_CLK>, <&gcc GSBI2_H_CLK>;
 749                                 clock-names = "core", "iface";
 750                                 status = "disabled";
 751                         };
 752
 753                         i2c@124a0000 {
 754                                 compatible = "qcom,i2c-qup-v1.1.1";
 755                                 reg = <0x124a0000 0x1000>;
 756                                 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
 757
 758                                 clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
 759                                 clock-names = "core", "iface";
 760                                 status = "disabled";
 761
 762                                 #address-cells = <1>;
 763                                 #size-cells = <0>;
 764                         };
 765
 766                 };
 767
 768                 gsbi4: gsbi@16300000 {
 769                         compatible = "qcom,gsbi-v1.0.0";
 770                         cell-index = <4>;
 771                         reg = <0x16300000 0x100>;
 772                         clocks = <&gcc GSBI4_H_CLK>;
 773                         clock-names = "iface";
 774                         #address-cells = <1>;
 775                         #size-cells = <1>;
 776                         ranges;
 777                         status = "disabled";
 778
 779                         syscon-tcsr = <&tcsr>;
 780
 781                         gsbi4_serial: serial@16340000 {
 782                                 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
 783                                 reg = <0x16340000 0x1000>,
 784                                       <0x16300000 0x1000>;
 785                                 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
 786                                 clocks = <&gcc GSBI4_UART_CLK>, <&gcc GSBI4_H_CLK>;
 787                                 clock-names = "core", "iface";
 788                                 status = "disabled";
 789                         };
 790
 791                         i2c@16380000 {
 792                                 compatible = "qcom,i2c-qup-v1.1.1";
 793                                 reg = <0x16380000 0x1000>;
 794                                 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
 795
 796                                 clocks = <&gcc GSBI4_QUP_CLK>, <&gcc GSBI4_H_CLK>;
 797                                 clock-names = "core", "iface";
 798                                 status = "disabled";
 799
 800                                 #address-cells = <1>;
 801                                 #size-cells = <0>;
 802                         };
 803                 };
 804
 805                 gsbi5: gsbi@1a200000 {
 806                         compatible = "qcom,gsbi-v1.0.0";
 807                         cell-index = <5>;
 808                         reg = <0x1a200000 0x100>;
 809                         clocks = <&gcc GSBI5_H_CLK>;
 810                         clock-names = "iface";
 811                         #address-cells = <1>;
 812                         #size-cells = <1>;
 813                         ranges;
 814                         status = "disabled";
 815
 816                         syscon-tcsr = <&tcsr>;
 817
 818                         uart5: serial@1a240000 {
 819                                 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
 820                                 reg = <0x1a240000 0x1000>,
 821                                       <0x1a200000 0x1000>;
 822                                 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
 823                                 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
 824                                 clock-names = "core", "iface";
 825                                 status = "disabled";
 826                         };
 827
 828                         i2c@1a280000 {
 829                                 compatible = "qcom,i2c-qup-v1.1.1";
 830                                 reg = <0x1a280000 0x1000>;
 831                                 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
 832
 833                                 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
 834                                 clock-names = "core", "iface";
 835                                 status = "disabled";
 836
 837                                 #address-cells = <1>;
 838                                 #size-cells = <0>;
 839                         };
 840
 841                         spi@1a280000 {
 842                                 compatible = "qcom,spi-qup-v1.1.1";
 843                                 reg = <0x1a280000 0x1000>;
 844                                 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
 845
 846                                 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
 847                                 clock-names = "core", "iface";
 848                                 status = "disabled";
 849
 850                                 #address-cells = <1>;
 851                                 #size-cells = <0>;
 852                         };
 853                 };
 854
 855                 sata_phy: sata-phy@1b400000 {
 856                         compatible = "qcom,ipq806x-sata-phy";
 857                         reg = <0x1b400000 0x200>;
 858
 859                         clocks = <&gcc SATA_PHY_CFG_CLK>;
 860                         clock-names = "cfg";
 861
 862                         #phy-cells = <0>;
 863                         status = "disabled";
 864                 };
 865
 866                 sata@29000000 {
 867                         compatible = "qcom,ipq806x-ahci", "generic-ahci";
 868                         reg = <0x29000000 0x180>;
 869
 870                         ports-implemented = <0x1>;
 871
 872                         interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
 873
 874                         clocks = <&gcc SFAB_SATA_S_H_CLK>,
 875                                  <&gcc SATA_H_CLK>,
 876                                  <&gcc SATA_A_CLK>,
 877                                  <&gcc SATA_RXOOB_CLK>,
 878                                  <&gcc SATA_PMALIVE_CLK>;
 879                         clock-names = "slave_face", "iface", "core",
 880                                         "rxoob", "pmalive";
 881
 882                         assigned-clocks = <&gcc SATA_RXOOB_CLK>, <&gcc SATA_PMALIVE_CLK>;
 883                         assigned-clock-rates = <100000000>, <100000000>;
 884
 885                         phys = <&sata_phy>;
 886                         phy-names = "sata-phy";
 887                         status = "disabled";
 888                 };
 889
 890                 qcom,ssbi@500000 {
 891                         compatible = "qcom,ssbi";
 892                         reg = <0x00500000 0x1000>;
 893                         qcom,controller-type = "pmic-arbiter";
 894                 };
 895
 896                 gcc: clock-controller@900000 {
 897                         compatible = "qcom,gcc-ipq8064";
 898                         reg = <0x00900000 0x4000>;
 899                         #clock-cells = <1>;
 900                         #reset-cells = <1>;
 901                         #power-domain-cells = <1>;
 902                 };
 903
 904                 tsens: thermal-sensor@900000 {
 905                         compatible = "qcom,ipq8064-tsens";
 906                         reg = <0x900000 0x3680>;
 907                         nvmem-cells = <&tsens_calib>, <&tsens_backup>;
 908                         nvmem-cell-names = "calib", "calib_backup";
 909                         interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
 910                         #thermal-sensor-cells = <1>;
 911                 };
 912
 913                 tcsr: syscon@1a400000 {
 914                         compatible = "qcom,tcsr-ipq8064", "syscon";
 915                         reg = <0x1a400000 0x100>;
 916                 };
 917
 918                 lcc: clock-controller@28000000 {
 919                         compatible = "qcom,lcc-ipq8064";
 920                         reg = <0x28000000 0x1000>;
 921                         #clock-cells = <1>;
 922                         #reset-cells = <1>;
 923                 };
 924
 925                 sfpb_mutex_block: syscon@1200600 {
 926                         compatible = "syscon";
 927                         reg = <0x01200600 0x100>;
 928                 };
 929
 930                 hs_phy_0: hs_phy_0 {
 931                         compatible = "qcom,dwc3-hs-usb-phy";
 932                         regmap = <&usb3_0>;
 933                         clocks = <&gcc USB30_0_UTMI_CLK>;
 934                         clock-names = "ref";
 935                         #phy-cells = <0>;
 936                 };
 937
 938                 ss_phy_0: ss_phy_0 {
 939                         compatible = "qcom,dwc3-ss-usb-phy";
 940                         regmap = <&usb3_0>;
 941                         clocks = <&gcc USB30_0_MASTER_CLK>;
 942                         clock-names = "ref";
 943                         #phy-cells = <0>;
 944                 };
 945
 946                 usb3_0: usb3@110f8800 {
 947                         compatible = "qcom,dwc3", "syscon";
 948                         #address-cells = <1>;
 949                         #size-cells = <1>;
 950                         reg = <0x110f8800 0x8000>;
 951                         clocks = <&gcc USB30_0_MASTER_CLK>;
 952                         clock-names = "core";
 953
 954                         ranges;
 955
 956                         resets = <&gcc USB30_0_MASTER_RESET>;
 957                         reset-names = "master";
 958
 959                         status = "disabled";
 960
 961                         dwc3_0: dwc3@11000000 {
 962                                 compatible = "snps,dwc3";
 963                                 reg = <0x11000000 0xcd00>;
 964                                 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 965                                 phys = <&hs_phy_0>, <&ss_phy_0>;
 966                                 phy-names = "usb2-phy", "usb3-phy";
 967                                 dr_mode = "host";
 968                                 snps,dis_u3_susphy_quirk;
 969                         };
 970                 };
 971
 972                 hs_phy_1: hs_phy_1 {
 973                         compatible = "qcom,dwc3-hs-usb-phy";
 974                         regmap = <&usb3_1>;
 975                         clocks = <&gcc USB30_1_UTMI_CLK>;
 976                         clock-names = "ref";
 977                         #phy-cells = <0>;
 978                 };
 979
 980                 ss_phy_1: ss_phy_1 {
 981                         compatible = "qcom,dwc3-ss-usb-phy";
 982                         regmap = <&usb3_1>;
 983                         clocks = <&gcc USB30_1_MASTER_CLK>;
 984                         clock-names = "ref";
 985                         #phy-cells = <0>;
 986                 };
 987
 988                 usb3_1: usb3@100f8800 {
 989                         compatible = "qcom,dwc3", "syscon";
 990                         #address-cells = <1>;
 991                         #size-cells = <1>;
 992                         reg = <0x100f8800 0x8000>;
 993                         clocks = <&gcc USB30_1_MASTER_CLK>;
 994                         clock-names = "core";
 995
 996                         ranges;
 997
 998                         resets = <&gcc USB30_1_MASTER_RESET>;
 999                         reset-names = "master";
1000
1001                         status = "disabled";
1002
1003                         dwc3_1: dwc3@10000000 {
1004                                 compatible = "snps,dwc3";
1005                                 reg = <0x10000000 0xcd00>;
1006                                 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
1007                                 phys = <&hs_phy_1>, <&ss_phy_1>;
1008                                 phy-names = "usb2-phy", "usb3-phy";
1009                                 dr_mode = "host";
1010                                 snps,dis_u3_susphy_quirk;
1011                         };
1012                 };
1013
1014                 pcie0: pci@1b500000 {
1015                         compatible = "qcom,pcie-ipq8064";
1016                         reg = <0x1b500000 0x1000
1017                                0x1b502000 0x80
1018                                0x1b600000 0x100
1019                                0x0ff00000 0x100000>;
1020                         reg-names = "dbi", "elbi", "parf", "config";
1021                         device_type = "pci";
1022                         linux,pci-domain = <0>;
1023                         bus-range = <0x00 0xff>;
1024                         num-lanes = <1>;
1025                         #address-cells = <3>;
1026                         #size-cells = <2>;
1027
1028                         ranges = <0x81000000 0 0x0fe00000 0x0fe00000 0 0x00100000   /* downstream I/O */
1029                                   0x82000000 0 0x08000000 0x08000000 0 0x07e00000>; /* non-prefetchable memory */
1030
1031                         interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
1032                         interrupt-names = "msi";
1033                         #interrupt-cells = <1>;
1034                         interrupt-map-mask = <0 0 0 0x7>;
1035                         interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1036                                         <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1037                                         <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1038                                         <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1039
1040                         clocks = <&gcc PCIE_A_CLK>,
1041                                  <&gcc PCIE_H_CLK>,
1042                                  <&gcc PCIE_PHY_CLK>,
1043                                  <&gcc PCIE_AUX_CLK>,
1044                                  <&gcc PCIE_ALT_REF_CLK>;
1045                         clock-names = "core", "iface", "phy", "aux", "ref";
1046
1047                         assigned-clocks = <&gcc PCIE_ALT_REF_CLK>;
1048                         assigned-clock-rates = <100000000>;
1049
1050                         resets = <&gcc PCIE_ACLK_RESET>,
1051                                  <&gcc PCIE_HCLK_RESET>,
1052                                  <&gcc PCIE_POR_RESET>,
1053                                  <&gcc PCIE_PCI_RESET>,
1054                                  <&gcc PCIE_PHY_RESET>,
1055                                  <&gcc PCIE_EXT_RESET>;
1056                         reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
1057
1058                         pinctrl-0 = <&pcie0_pins>;
1059                         pinctrl-names = "default";
1060
1061                         perst-gpios = <&qcom_pinmux 3 GPIO_ACTIVE_LOW>;
1062
1063                         phy-tx0-term-offset = <7>;
1064
1065                         status = "disabled";
1066                 };
1067
1068                 pcie1: pci@1b700000 {
1069                         compatible = "qcom,pcie-ipq8064";
1070                         reg = <0x1b700000 0x1000
1071                                0x1b702000 0x80
1072                                0x1b800000 0x100
1073                                0x31f00000 0x100000>;
1074                         reg-names = "dbi", "elbi", "parf", "config";
1075                         device_type = "pci";
1076                         linux,pci-domain = <1>;
1077                         bus-range = <0x00 0xff>;
1078                         num-lanes = <1>;
1079                         #address-cells = <3>;
1080                         #size-cells = <2>;
1081
1082                         ranges = <0x81000000 0 0x31e00000 0x31e00000 0 0x00100000   /* downstream I/O */
1083                                   0x82000000 0 0x2e000000 0x2e000000 0 0x03e00000>; /* non-prefetchable memory */
1084
1085                         interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
1086                         interrupt-names = "msi";
1087                         #interrupt-cells = <1>;
1088                         interrupt-map-mask = <0 0 0 0x7>;
1089                         interrupt-map = <0 0 0 1 &intc 0 58 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1090                                         <0 0 0 2 &intc 0 59 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1091                                         <0 0 0 3 &intc 0 60 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1092                                         <0 0 0 4 &intc 0 61 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1093
1094                         clocks = <&gcc PCIE_1_A_CLK>,
1095                                  <&gcc PCIE_1_H_CLK>,
1096                                  <&gcc PCIE_1_PHY_CLK>,
1097                                  <&gcc PCIE_1_AUX_CLK>,
1098                                  <&gcc PCIE_1_ALT_REF_CLK>;
1099                         clock-names = "core", "iface", "phy", "aux", "ref";
1100
1101                         assigned-clocks = <&gcc PCIE_1_ALT_REF_CLK>;
1102                         assigned-clock-rates = <100000000>;
1103
1104                         resets = <&gcc PCIE_1_ACLK_RESET>,
1105                                  <&gcc PCIE_1_HCLK_RESET>,
1106                                  <&gcc PCIE_1_POR_RESET>,
1107                                  <&gcc PCIE_1_PCI_RESET>,
1108                                  <&gcc PCIE_1_PHY_RESET>,
1109                                  <&gcc PCIE_1_EXT_RESET>;
1110                         reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
1111
1112                         pinctrl-0 = <&pcie1_pins>;
1113                         pinctrl-names = "default";
1114
1115                         perst-gpios = <&qcom_pinmux 48 GPIO_ACTIVE_LOW>;
1116
1117                         phy-tx0-term-offset = <7>;
1118
1119                         status = "disabled";
1120                 };
1121
1122                 pcie2: pci@1b900000 {
1123                         compatible = "qcom,pcie-ipq8064";
1124                         reg = <0x1b900000 0x1000
1125                                0x1b902000 0x80
1126                                0x1ba00000 0x100
1127                                0x35f00000 0x100000>;
1128                         reg-names = "dbi", "elbi", "parf", "config";
1129                         device_type = "pci";
1130                         linux,pci-domain = <2>;
1131                         bus-range = <0x00 0xff>;
1132                         num-lanes = <1>;
1133                         #address-cells = <3>;
1134                         #size-cells = <2>;
1135
1136                         ranges = <0x81000000 0 0x35e00000 0x35e00000 0 0x00100000   /* downstream I/O */
1137                                   0x82000000 0 0x32000000 0x32000000 0 0x03e00000>; /* non-prefetchable memory */
1138
1139                         interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
1140                         interrupt-names = "msi";
1141                         #interrupt-cells = <1>;
1142                         interrupt-map-mask = <0 0 0 0x7>;
1143                         interrupt-map = <0 0 0 1 &intc 0 72 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1144                                         <0 0 0 2 &intc 0 73 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1145                                         <0 0 0 3 &intc 0 74 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1146                                         <0 0 0 4 &intc 0 75 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1147
1148                         clocks = <&gcc PCIE_2_A_CLK>,
1149                                  <&gcc PCIE_2_H_CLK>,
1150                                  <&gcc PCIE_2_PHY_CLK>,
1151                                  <&gcc PCIE_2_AUX_CLK>,
1152                                  <&gcc PCIE_2_ALT_REF_CLK>;
1153                         clock-names = "core", "iface", "phy", "aux", "ref";
1154
1155                         assigned-clocks = <&gcc PCIE_2_ALT_REF_CLK>;
1156                         assigned-clock-rates = <100000000>;
1157
1158                         resets = <&gcc PCIE_2_ACLK_RESET>,
1159                                  <&gcc PCIE_2_HCLK_RESET>,
1160                                  <&gcc PCIE_2_POR_RESET>,
1161                                  <&gcc PCIE_2_PCI_RESET>,
1162                                  <&gcc PCIE_2_PHY_RESET>,
1163                                  <&gcc PCIE_2_EXT_RESET>;
1164                         reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
1165
1166                         pinctrl-0 = <&pcie2_pins>;
1167                         pinctrl-names = "default";
1168
1169                         perst-gpios = <&qcom_pinmux 63 GPIO_ACTIVE_LOW>;
1170
1171                         phy-tx0-term-offset = <7>;
1172
1173                         status = "disabled";
1174                 };
1175
1176                 adm_dma: dma@18300000 {
1177                         compatible = "qcom,adm";
1178                         reg = <0x18300000 0x100000>;
1179                         interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
1180                         #dma-cells = <1>;
1181
1182                         clocks = <&gcc ADM0_CLK>, <&gcc ADM0_PBUS_CLK>;
1183                         clock-names = "core", "iface";
1184
1185                         resets = <&gcc ADM0_RESET>,
1186                                  <&gcc ADM0_PBUS_RESET>,
1187                                  <&gcc ADM0_C0_RESET>,
1188                                  <&gcc ADM0_C1_RESET>,
1189                                  <&gcc ADM0_C2_RESET>;
1190                         reset-names = "clk", "pbus", "c0", "c1", "c2";
1191                         qcom,ee = <0>;
1192
1193                         status = "disabled";
1194                 };
1195
1196                 nand@1ac00000 {
1197                         compatible = "qcom,ipq806x-nand";
1198                         reg = <0x1ac00000 0x800>;
1199
1200                         clocks = <&gcc EBI2_CLK>,
1201                                  <&gcc EBI2_AON_CLK>;
1202                         clock-names = "core", "aon";
1203
1204                         dmas = <&adm_dma 3>;
1205                         dma-names = "rxtx";
1206                         qcom,cmd-crci = <15>;
1207                         qcom,data-crci = <3>;
1208
1209                         status = "disabled";
1210
1211                         #address-cells = <1>;
1212                         #size-cells = <0>;
1213                 };
1214
1215                 nss_common: syscon@03000000 {
1216                         compatible = "syscon";
1217                         reg = <0x03000000 0x0000FFFF>;
1218                 };
1219
1220                 qsgmii_csr: syscon@1bb00000 {
1221                         compatible = "syscon";
1222                         reg = <0x1bb00000 0x000001FF>;
1223                 };
1224
1225                 stmmac_axi_setup: stmmac-axi-config {
1226                         snps,wr_osr_lmt = <7>;
1227                         snps,rd_osr_lmt = <7>;
1228                         snps,blen = <16 0 0 0 0 0 0>;
1229                 };
1230
1231                 gmac0: ethernet@37000000 {
1232                         device_type = "network";
1233                         compatible = "qcom,ipq806x-gmac";
1234                         reg = <0x37000000 0x200000>;
1235                         interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
1236                         interrupt-names = "macirq";
1237
1238                         snps,axi-config = <&stmmac_axi_setup>;
1239                         snps,pbl = <32>;
1240                         snps,aal = <1>;
1241
1242                         qcom,nss-common = <&nss_common>;
1243                         qcom,qsgmii-csr = <&qsgmii_csr>;
1244
1245                         clocks = <&gcc GMAC_CORE1_CLK>;
1246                         clock-names = "stmmaceth";
1247
1248                         resets = <&gcc GMAC_CORE1_RESET>;
1249                         reset-names = "stmmaceth";
1250
1251                         status = "disabled";
1252                 };
1253
1254                 gmac1: ethernet@37200000 {
1255                         device_type = "network";
1256                         compatible = "qcom,ipq806x-gmac";
1257                         reg = <0x37200000 0x200000>;
1258                         interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
1259                         interrupt-names = "macirq";
1260
1261                         snps,axi-config = <&stmmac_axi_setup>;
1262                         snps,pbl = <32>;
1263                         snps,aal = <1>;
1264
1265                         qcom,nss-common = <&nss_common>;
1266                         qcom,qsgmii-csr = <&qsgmii_csr>;
1267
1268                         clocks = <&gcc GMAC_CORE2_CLK>;
1269                         clock-names = "stmmaceth";
1270
1271                         resets = <&gcc GMAC_CORE2_RESET>;
1272                         reset-names = "stmmaceth";
1273
1274                         status = "disabled";
1275                 };
1276
1277                 gmac2: ethernet@37400000 {
1278                         device_type = "network";
1279                         compatible = "qcom,ipq806x-gmac";
1280                         reg = <0x37400000 0x200000>;
1281                         interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
1282                         interrupt-names = "macirq";
1283
1284                         snps,axi-config = <&stmmac_axi_setup>;
1285                         snps,pbl = <32>;
1286                         snps,aal = <1>;
1287
1288                         qcom,nss-common = <&nss_common>;
1289                         qcom,qsgmii-csr = <&qsgmii_csr>;
1290
1291                         clocks = <&gcc GMAC_CORE3_CLK>;
1292                         clock-names = "stmmaceth";
1293
1294                         resets = <&gcc GMAC_CORE3_RESET>;
1295                         reset-names = "stmmaceth";
1296
1297                         status = "disabled";
1298                 };
1299
1300                 gmac3: ethernet@37600000 {
1301                         device_type = "network";
1302                         compatible = "qcom,ipq806x-gmac";
1303                         reg = <0x37600000 0x200000>;
1304                         interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
1305                         interrupt-names = "macirq";
1306
1307                         snps,axi-config = <&stmmac_axi_setup>;
1308                         snps,pbl = <32>;
1309                         snps,aal = <1>;
1310
1311                         qcom,nss-common = <&nss_common>;
1312                         qcom,qsgmii-csr = <&qsgmii_csr>;
1313
1314                         clocks = <&gcc GMAC_CORE4_CLK>;
1315                         clock-names = "stmmaceth";
1316
1317                         resets = <&gcc GMAC_CORE4_RESET>;
1318                         reset-names = "stmmaceth";
1319
1320                         status = "disabled";
1321                 };
1322
1323                 /* Temporary fixed regulator */
1324                 vsdcc_fixed: vsdcc-regulator {
1325                         compatible = "regulator-fixed";
1326                         regulator-name = "SDCC Power";
1327                         regulator-min-microvolt = <3300000>;
1328                         regulator-max-microvolt = <3300000>;
1329                         regulator-always-on;
1330                 };
1331
1332                 sdcc1bam:dma@12402000 {
1333                         compatible = "qcom,bam-v1.3.0";
1334                         reg = <0x12402000 0x8000>;
1335                         interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1336                         clocks = <&gcc SDC1_H_CLK>;
1337                         clock-names = "bam_clk";
1338                         #dma-cells = <1>;
1339                         qcom,ee = <0>;
1340                 };
1341
1342                 sdcc3bam:dma@12182000 {
1343                         compatible = "qcom,bam-v1.3.0";
1344                         reg = <0x12182000 0x8000>;
1345                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1346                         clocks = <&gcc SDC3_H_CLK>;
1347                         clock-names = "bam_clk";
1348                         #dma-cells = <1>;
1349                         qcom,ee = <0>;
1350                 };
1351
1352                 amba {
1353                         compatible = "arm,amba-bus";
1354                         #address-cells = <1>;
1355                         #size-cells = <1>;
1356                         ranges;
1357                         sdcc1: sdcc@12400000 {
1358                                 status          = "disabled";
1359                                 compatible      = "arm,pl18x", "arm,primecell";
1360                                 arm,primecell-periphid = <0x00051180>;
1361                                 reg             = <0x12400000 0x2000>;
1362                                 interrupts      = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
1363                                 interrupt-names = "cmd_irq";
1364                                 clocks          = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
1365                                 clock-names     = "mclk", "apb_pclk";
1366                                 bus-width       = <8>;
1367                                 max-frequency   = <96000000>;
1368                                 non-removable;
1369                                 cap-sd-highspeed;
1370                                 cap-mmc-highspeed;
1371                                 vmmc-supply = <&vsdcc_fixed>;
1372                                 dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
1373                                 dma-names = "tx", "rx";
1374                         };
1375
1376                         sdcc3: sdcc@12180000 {
1377                                 compatible      = "arm,pl18x", "arm,primecell";
1378                                 arm,primecell-periphid = <0x00051180>;
1379                                 status          = "disabled";
1380                                 reg             = <0x12180000 0x2000>;
1381                                 interrupts      = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
1382                                 interrupt-names = "cmd_irq";
1383                                 clocks          = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
1384                                 clock-names     = "mclk", "apb_pclk";
1385                                 bus-width       = <8>;
1386                                 cap-sd-highspeed;
1387                                 cap-mmc-highspeed;
1388                                 max-frequency   = <192000000>;
1389                                 #mmc-ddr-1_8v;
1390                                 sd-uhs-sdr104;
1391                                 sd-uhs-ddr50;
1392                                 vqmmc-supply = <&vsdcc_fixed>;
1393                                 dmas = <&sdcc3bam 2>, <&sdcc3bam 1>;
1394                                 dma-names = "tx", "rx";
1395                         };
1396                 };
1397         };
1398
1399         sfpb_mutex: sfpb-mutex {
1400                 compatible = "qcom,sfpb-mutex";
1401                 syscon = <&sfpb_mutex_block 4 4>;
1402
1403                 #hwlock-cells = <1>;
1404         };
1405
1406         smem {
1407                 compatible = "qcom,smem";
1408                 memory-region = <&smem>;
1409                 hwlocks = <&sfpb_mutex 3>;
1410         };
1411 };