target/linux/ipq806x/files-4.19/arch/arm/boot/dts/qcom-ipq8064.dtsi

   1 /dts-v1/;
   2
   3 #include "skeleton.dtsi"
   4 #include <dt-bindings/clock/qcom,gcc-ipq806x.h>
   5 #include <dt-bindings/mfd/qcom-rpm.h>
   6 #include <dt-bindings/clock/qcom,rpmcc.h>
   7 #include <dt-bindings/clock/qcom,lcc-ipq806x.h>
   8 #include <dt-bindings/soc/qcom,gsbi.h>
   9 #include <dt-bindings/reset/qcom,gcc-ipq806x.h>
  10 #include <dt-bindings/interrupt-controller/arm-gic.h>
  11 #include <dt-bindings/gpio/gpio.h>
  12
  13 / {
  14         model = "Qualcomm IPQ8064";
  15         compatible = "qcom,ipq8064";
  16         interrupt-parent = <&intc>;
  17
  18         cpus {
  19                 #address-cells = <1>;
  20                 #size-cells = <0>;
  21
  22                 cpu0: cpu@0 {
  23                         compatible = "qcom,krait";
  24                         enable-method = "qcom,kpss-acc-v1";
  25                         device_type = "cpu";
  26                         reg = <0>;
  27                         next-level-cache = <&L2>;
  28                         qcom,acc = <&acc0>;
  29                         qcom,saw = <&saw0>;
  30                         clocks = <&kraitcc 0>, <&kraitcc 4>;
  31                         clock-names = "cpu", "l2";
  32                         clock-latency = <100000>;
  33                         cpu-supply = <&smb208_s2a>;
  34                         voltage-tolerance = <5>;
  35                         cooling-min-state = <0>;
  36                         cooling-max-state = <10>;
  37                         #cooling-cells = <2>;
  38                         cpu-idle-states = <&CPU_SPC>;
  39                 };
  40
  41                 cpu1: cpu@1 {
  42                         compatible = "qcom,krait";
  43                         enable-method = "qcom,kpss-acc-v1";
  44                         device_type = "cpu";
  45                         reg = <1>;
  46                         next-level-cache = <&L2>;
  47                         qcom,acc = <&acc1>;
  48                         qcom,saw = <&saw1>;
  49                         clocks = <&kraitcc 1>, <&kraitcc 4>;
  50                         clock-names = "cpu", "l2";
  51                         clock-latency = <100000>;
  52                         cpu-supply = <&smb208_s2b>;
  53                         cooling-min-state = <0>;
  54                         cooling-max-state = <10>;
  55                         #cooling-cells = <2>;
  56                         cpu-idle-states = <&CPU_SPC>;
  57                 };
  58
  59                 L2: l2-cache {
  60                         compatible = "cache";
  61                         cache-level = <2>;
  62                         qcom,saw = <&saw_l2>;
  63                 };
  64
  65                 qcom,l2 {
  66                         qcom,l2-rates = <384000000 1000000000 1200000000>;
  67                 };
  68
  69                 idle-states {
  70                         CPU_SPC: spc {
  71                                 compatible = "qcom,idle-state-spc",
  72                                                 "arm,idle-state";
  73                                 status = "okay";
  74                                 entry-latency-us = <400>;
  75                                 exit-latency-us = <900>;
  76                                 min-residency-us = <3000>;
  77                         };
  78                 };
  79         };
  80
  81         thermal-zones {
  82                 tsens_tz_sensor0 {
  83                         polling-delay-passive = <0>;
  84                         polling-delay = <0>;
  85                         thermal-sensors = <&tsens 0>;
  86
  87                         trips {
  88                                 cpu-critical-hi {
  89                                         temperature = <125000>;
  90                                         hysteresis = <2000>;
  91                                         type = "critical_high";
  92                                 };
  93
  94                                 cpu-config-hi {
  95                                         temperature = <105000>;
  96                                         hysteresis = <2000>;
  97                                         type = "configurable_hi";
  98                                 };
  99
 100                                 cpu-config-lo {
 101                                         temperature = <95000>;
 102                                         hysteresis = <2000>;
 103                                         type = "configurable_lo";
 104                                 };
 105
 106                                 cpu-critical-low {
 107                                         temperature = <0>;
 108                                         hysteresis = <2000>;
 109                                         type = "critical_low";
 110                                 };
 111                         };
 112                 };
 113
 114                 tsens_tz_sensor1 {
 115                         polling-delay-passive = <0>;
 116                         polling-delay = <0>;
 117                         thermal-sensors = <&tsens 1>;
 118
 119                         trips {
 120                                 cpu-critical-hi {
 121                                         temperature = <125000>;
 122                                         hysteresis = <2000>;
 123                                         type = "critical_high";
 124                                 };
 125
 126                                 cpu-config-hi {
 127                                         temperature = <105000>;
 128                                         hysteresis = <2000>;
 129                                         type = "configurable_hi";
 130                                 };
 131
 132                                 cpu-config-lo {
 133                                         temperature = <95000>;
 134                                         hysteresis = <2000>;
 135                                         type = "configurable_lo";
 136                                 };
 137
 138                                 cpu-critical-low {
 139                                         temperature = <0>;
 140                                         hysteresis = <2000>;
 141                                         type = "critical_low";
 142                                 };
 143                         };
 144                 };
 145
 146                 tsens_tz_sensor2 {
 147                         polling-delay-passive = <0>;
 148                         polling-delay = <0>;
 149                         thermal-sensors = <&tsens 2>;
 150
 151                         trips {
 152                                 cpu-critical-hi {
 153                                         temperature = <125000>;
 154                                         hysteresis = <2000>;
 155                                         type = "critical_high";
 156                                 };
 157
 158                                 cpu-config-hi {
 159                                         temperature = <105000>;
 160                                         hysteresis = <2000>;
 161                                         type = "configurable_hi";
 162                                 };
 163
 164                                 cpu-config-lo {
 165                                         temperature = <95000>;
 166                                         hysteresis = <2000>;
 167                                         type = "configurable_lo";
 168                                 };
 169
 170                                 cpu-critical-low {
 171                                         temperature = <0>;
 172                                         hysteresis = <2000>;
 173                                         type = "critical_low";
 174                                 };
 175                         };
 176                 };
 177
 178                 tsens_tz_sensor3 {
 179                         polling-delay-passive = <0>;
 180                         polling-delay = <0>;
 181                         thermal-sensors = <&tsens 3>;
 182
 183                         trips {
 184                                 cpu-critical-hi {
 185                                         temperature = <125000>;
 186                                         hysteresis = <2000>;
 187                                         type = "critical_high";
 188                                 };
 189
 190                                 cpu-config-hi {
 191                                         temperature = <105000>;
 192                                         hysteresis = <2000>;
 193                                         type = "configurable_hi";
 194                                 };
 195
 196                                 cpu-config-lo {
 197                                         temperature = <95000>;
 198                                         hysteresis = <2000>;
 199                                         type = "configurable_lo";
 200                                 };
 201
 202                                 cpu-critical-low {
 203                                         temperature = <0>;
 204                                         hysteresis = <2000>;
 205                                         type = "critical_low";
 206                                 };
 207                         };
 208                 };
 209
 210                 tsens_tz_sensor4 {
 211                         polling-delay-passive = <0>;
 212                         polling-delay = <0>;
 213                         thermal-sensors = <&tsens 4>;
 214
 215                         trips {
 216                                 cpu-critical-hi {
 217                                         temperature = <125000>;
 218                                         hysteresis = <2000>;
 219                                         type = "critical_high";
 220                                 };
 221
 222                                 cpu-config-hi {
 223                                         temperature = <105000>;
 224                                         hysteresis = <2000>;
 225                                         type = "configurable_hi";
 226                                 };
 227
 228                                 cpu-config-lo {
 229                                         temperature = <95000>;
 230                                         hysteresis = <2000>;
 231                                         type = "configurable_lo";
 232                                 };
 233
 234                                 cpu-critical-low {
 235                                         temperature = <0>;
 236                                         hysteresis = <2000>;
 237                                         type = "critical_low";
 238                                 };
 239                         };
 240                 };
 241
 242                 tsens_tz_sensor5 {
 243                         polling-delay-passive = <0>;
 244                         polling-delay = <0>;
 245                         thermal-sensors = <&tsens 5>;
 246
 247                         trips {
 248                                 cpu-critical-hi {
 249                                         temperature = <125000>;
 250                                         hysteresis = <2000>;
 251                                         type = "critical_high";
 252                                 };
 253
 254                                 cpu-config-hi {
 255                                         temperature = <105000>;
 256                                         hysteresis = <2000>;
 257                                         type = "configurable_hi";
 258                                 };
 259
 260                                 cpu-config-lo {
 261                                         temperature = <95000>;
 262                                         hysteresis = <2000>;
 263                                         type = "configurable_lo";
 264                                 };
 265
 266                                 cpu-critical-low {
 267                                         temperature = <0>;
 268                                         hysteresis = <2000>;
 269                                         type = "critical_low";
 270                                 };
 271                         };
 272                 };
 273
 274                 tsens_tz_sensor6 {
 275                         polling-delay-passive = <0>;
 276                         polling-delay = <0>;
 277                         thermal-sensors = <&tsens 6>;
 278
 279                         trips {
 280                                 cpu-critical-hi {
 281                                         temperature = <125000>;
 282                                         hysteresis = <2000>;
 283                                         type = "critical_high";
 284                                 };
 285
 286                                 cpu-config-hi {
 287                                         temperature = <105000>;
 288                                         hysteresis = <2000>;
 289                                         type = "configurable_hi";
 290                                 };
 291
 292                                 cpu-config-lo {
 293                                         temperature = <95000>;
 294                                         hysteresis = <2000>;
 295                                         type = "configurable_lo";
 296                                 };
 297
 298                                 cpu-critical-low {
 299                                         temperature = <0>;
 300                                         hysteresis = <2000>;
 301                                         type = "critical_low";
 302                                 };
 303                         };
 304                 };
 305
 306                 tsens_tz_sensor7 {
 307                         polling-delay-passive = <0>;
 308                         polling-delay = <0>;
 309                         thermal-sensors = <&tsens 7>;
 310
 311                         trips {
 312                                 cpu-critical-hi {
 313                                         temperature = <125000>;
 314                                         hysteresis = <2000>;
 315                                         type = "critical_high";
 316                                 };
 317
 318                                 cpu-config-hi {
 319                                         temperature = <105000>;
 320                                         hysteresis = <2000>;
 321                                         type = "configurable_hi";
 322                                 };
 323
 324                                 cpu-config-lo {
 325                                         temperature = <95000>;
 326                                         hysteresis = <2000>;
 327                                         type = "configurable_lo";
 328                                 };
 329
 330                                 cpu-critical-low {
 331                                         temperature = <0>;
 332                                         hysteresis = <2000>;
 333                                         type = "critical_low";
 334                                 };
 335                         };
 336                 };
 337
 338                 tsens_tz_sensor8 {
 339                         polling-delay-passive = <0>;
 340                         polling-delay = <0>;
 341                         thermal-sensors = <&tsens 8>;
 342
 343                         trips {
 344                                 cpu-critical-hi {
 345                                         temperature = <125000>;
 346                                         hysteresis = <2000>;
 347                                         type = "critical_high";
 348                                 };
 349
 350                                 cpu-config-hi {
 351                                         temperature = <105000>;
 352                                         hysteresis = <2000>;
 353                                         type = "configurable_hi";
 354                                 };
 355
 356                                 cpu-config-lo {
 357                                         temperature = <95000>;
 358                                         hysteresis = <2000>;
 359                                         type = "configurable_lo";
 360                                 };
 361
 362                                 cpu-critical-low {
 363                                         temperature = <0>;
 364                                         hysteresis = <2000>;
 365                                         type = "critical_low";
 366                                 };
 367                         };
 368                 };
 369
 370                 tsens_tz_sensor9 {
 371                         polling-delay-passive = <0>;
 372                         polling-delay = <0>;
 373                         thermal-sensors = <&tsens 9>;
 374
 375                         trips {
 376                                 cpu-critical-hi {
 377                                         temperature = <125000>;
 378                                         hysteresis = <2000>;
 379                                         type = "critical_high";
 380                                 };
 381
 382                                 cpu-config-hi {
 383                                         temperature = <105000>;
 384                                         hysteresis = <2000>;
 385                                         type = "configurable_hi";
 386                                 };
 387
 388                                 cpu-config-lo {
 389                                         temperature = <95000>;
 390                                         hysteresis = <2000>;
 391                                         type = "configurable_lo";
 392                                 };
 393
 394                                 cpu-critical-low {
 395                                         temperature = <0>;
 396                                         hysteresis = <2000>;
 397                                         type = "critical_low";
 398                                 };
 399                         };
 400                 };
 401
 402                 tsens_tz_sensor10 {
 403                         polling-delay-passive = <0>;
 404                         polling-delay = <0>;
 405                         thermal-sensors = <&tsens 10>;
 406
 407                         trips {
 408                                 cpu-critical-hi {
 409                                         temperature = <125000>;
 410                                         hysteresis = <2000>;
 411                                         type = "critical_high";
 412                                 };
 413
 414                                 cpu-config-hi {
 415                                         temperature = <105000>;
 416                                         hysteresis = <2000>;
 417                                         type = "configurable_hi";
 418                                 };
 419
 420                                 cpu-config-lo {
 421                                         temperature = <95000>;
 422                                         hysteresis = <2000>;
 423                                         type = "configurable_lo";
 424                                 };
 425
 426                                 cpu-critical-low {
 427                                         temperature = <0>;
 428                                         hysteresis = <2000>;
 429                                         type = "critical_low";
 430                                 };
 431                         };
 432                 };
 433         };
 434
 435         cpu-pmu {
 436                 compatible = "qcom,krait-pmu";
 437                 interrupts = <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |
 438                                           IRQ_TYPE_LEVEL_HIGH)>;
 439         };
 440
 441         reserved-memory {
 442                 #address-cells = <1>;
 443                 #size-cells = <1>;
 444                 ranges;
 445
 446                 nss@40000000 {
 447                         reg = <0x40000000 0x1000000>;
 448                         no-map;
 449                 };
 450
 451                 smem: smem@41000000 {
 452                         reg = <0x41000000 0x200000>;
 453                         no-map;
 454                 };
 455         };
 456
 457         clocks {
 458                 cxo_board {
 459                         compatible = "fixed-clock";
 460                         #clock-cells = <0>;
 461                         clock-frequency = <25000000>;
 462                 };
 463
 464                 pxo_board {
 465                         compatible = "fixed-clock";
 466                         #clock-cells = <0>;
 467                         clock-frequency = <25000000>;
 468                 };
 469
 470                 sleep_clk: sleep_clk {
 471                         compatible = "fixed-clock";
 472                         clock-frequency = <32768>;
 473                         #clock-cells = <0>;
 474                 };
 475         };
 476
 477         firmware {
 478                 scm {
 479                         compatible = "qcom,scm-ipq806x";
 480                 };
 481         };
 482
 483         kraitcc: clock-controller {
 484                 compatible = "qcom,krait-cc-v1";
 485                 #clock-cells = <1>;
 486         };
 487
 488         qcom,pvs {
 489                 qcom,pvs-format-a;
 490                 qcom,speed0-pvs0-bin-v0 =
 491                         < 1400000000 1250000 >,
 492                         < 1200000000 1200000 >,
 493                         < 1000000000 1150000 >,
 494                          < 800000000 1100000 >,
 495                          < 600000000 1050000 >,
 496                          < 384000000 1000000 >;
 497
 498                 qcom,speed0-pvs1-bin-v0 =
 499                         < 1400000000 1175000 >,
 500                         < 1200000000 1125000 >,
 501                         < 1000000000 1075000 >,
 502                          < 800000000 1025000 >,
 503                          < 600000000  975000 >,
 504                          < 384000000  925000 >;
 505
 506                 qcom,speed0-pvs2-bin-v0 =
 507                         < 1400000000 1125000 >,
 508                         < 1200000000 1075000 >,
 509                         < 1000000000 1025000 >,
 510                          < 800000000  995000 >,
 511                          < 600000000  925000 >,
 512                          < 384000000  875000 >;
 513
 514                 qcom,speed0-pvs3-bin-v0 =
 515                         < 1400000000 1050000 >,
 516                         < 1200000000 1000000 >,
 517                         < 1000000000  950000 >,
 518                          < 800000000  900000 >,
 519                          < 600000000  850000 >,
 520                          < 384000000  800000 >;
 521         };
 522
 523         soc: soc {
 524                 #address-cells = <1>;
 525                 #size-cells = <1>;
 526                 ranges;
 527                 compatible = "simple-bus";
 528
 529                 lpass@28100000 {
 530                         compatible = "qcom,lpass-cpu";
 531                         status = "disabled";
 532                         clocks = <&lcc AHBIX_CLK>,
 533                                         <&lcc MI2S_OSR_CLK>,
 534                                         <&lcc MI2S_BIT_CLK>;
 535                         clock-names = "ahbix-clk",
 536                                         "mi2s-osr-clk",
 537                                         "mi2s-bit-clk";
 538                         interrupts = <GIC_SPI 85 IRQ_TYPE_EDGE_RISING>;
 539                         interrupt-names = "lpass-irq-lpaif";
 540                         reg = <0x28100000 0x10000>;
 541                         reg-names = "lpass-lpaif";
 542                 };
 543
 544                 qfprom: qfprom@700000 {
 545                         compatible = "qcom,qfprom", "syscon";
 546                         reg = <0x700000 0x1000>;
 547                         #address-cells = <1>;
 548                         #size-cells = <1>;
 549                         status = "okay";
 550                         tsens_calib: calib@400 {
 551                                 reg = <0x400 0x10>;
 552                         };
 553                         tsens_backup: backup@410 {
 554                                 reg = <0x410 0x10>;
 555                         };
 556                 };
 557
 558                 rpm@108000 {
 559                         compatible = "qcom,rpm-ipq8064";
 560                         reg = <0x108000 0x1000>;
 561                         qcom,ipc = <&l2cc 0x8 2>;
 562
 563                         interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
 564                                      <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
 565                                      <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 566                         interrupt-names = "ack",
 567                                           "err",
 568                                           "wakeup";
 569
 570                         clocks = <&gcc RPM_MSG_RAM_H_CLK>;
 571                         clock-names = "ram";
 572
 573                         #address-cells = <1>;
 574                         #size-cells = <0>;
 575
 576                         rpmcc: clock-controller {
 577                                 compatible      = "qcom,rpmcc-ipq806x", "qcom,rpmcc";
 578                                 #clock-cells = <1>;
 579                         };
 580
 581                         regulators {
 582                                 compatible = "qcom,rpm-smb208-regulators";
 583
 584                                 smb208_s1a: s1a {
 585                                         regulator-min-microvolt = <1050000>;
 586                                         regulator-max-microvolt = <1150000>;
 587
 588                                         qcom,switch-mode-frequency = <1200000>;
 589
 590                                 };
 591
 592                                 smb208_s1b: s1b {
 593                                         regulator-min-microvolt = <1050000>;
 594                                         regulator-max-microvolt = <1150000>;
 595
 596                                         qcom,switch-mode-frequency = <1200000>;
 597                                 };
 598
 599                                 smb208_s2a: s2a {
 600                                         regulator-min-microvolt = < 800000>;
 601                                         regulator-max-microvolt = <1250000>;
 602
 603                                         qcom,switch-mode-frequency = <1200000>;
 604                                 };
 605
 606                                 smb208_s2b: s2b {
 607                                         regulator-min-microvolt = < 800000>;
 608                                         regulator-max-microvolt = <1250000>;
 609
 610                                         qcom,switch-mode-frequency = <1200000>;
 611                                 };
 612                         };
 613                 };
 614
 615                 rng@1a500000 {
 616                         compatible = "qcom,prng";
 617                         reg = <0x1a500000 0x200>;
 618                         clocks = <&gcc PRNG_CLK>;
 619                         clock-names = "core";
 620                 };
 621
 622                 qcom_pinmux: pinmux@800000 {
 623                         compatible = "qcom,ipq8064-pinctrl";
 624                         reg = <0x800000 0x4000>;
 625
 626                         gpio-controller;
 627                         #gpio-cells = <2>;
 628                         interrupt-controller;
 629                         #interrupt-cells = <2>;
 630                         interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 631
 632                         pcie0_pins: pcie0_pinmux {
 633                                 mux {
 634                                         pins = "gpio3";
 635                                         function = "pcie1_rst";
 636                                         drive-strength = <12>;
 637                                         bias-disable;
 638                                 };
 639                         };
 640
 641                         pcie1_pins: pcie1_pinmux {
 642                                 mux {
 643                                         pins = "gpio48";
 644                                         function = "pcie2_rst";
 645                                         drive-strength = <12>;
 646                                         bias-disable;
 647                                 };
 648                         };
 649
 650                         pcie2_pins: pcie2_pinmux {
 651                                 mux {
 652                                         pins = "gpio63";
 653                                         function = "pcie3_rst";
 654                                         drive-strength = <12>;
 655                                         bias-disable;
 656                                         output-low;
 657                                 };
 658                         };
 659
 660                         spi_pins: spi_pins {
 661                                 mux {
 662                                         pins = "gpio18", "gpio19", "gpio21";
 663                                         function = "gsbi5";
 664                                         drive-strength = <10>;
 665                                         bias-none;
 666                                 };
 667                         };
 668
 669                         leds_pins: leds_pins {
 670                                 mux {
 671                                         pins = "gpio7", "gpio8", "gpio9",
 672                                                "gpio26", "gpio53";
 673                                         function = "gpio";
 674                                         drive-strength = <2>;
 675                                         bias-pull-down;
 676                                         output-low;
 677                                 };
 678                         };
 679
 680                         buttons_pins: buttons_pins {
 681                                 mux {
 682                                         pins = "gpio54";
 683                                         drive-strength = <2>;
 684                                         bias-pull-up;
 685                                 };
 686                         };
 687                 };
 688
 689                 intc: interrupt-controller@2000000 {
 690                         compatible = "qcom,msm-qgic2";
 691                         interrupt-controller;
 692                         #interrupt-cells = <3>;
 693                         reg = <0x02000000 0x1000>,
 694                               <0x02002000 0x1000>;
 695                 };
 696
 697                 timer@200a000 {
 698                         compatible = "qcom,kpss-timer",
 699                                 "qcom,kpss-wdt-ipq8064", "qcom,msm-timer";
 700                         interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(2) |
 701                                                  IRQ_TYPE_EDGE_RISING)>,
 702                                      <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(2) |
 703                                                  IRQ_TYPE_EDGE_RISING)>,
 704                                      <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(2) |
 705                                                  IRQ_TYPE_EDGE_RISING)>,
 706                                      <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(2) |
 707                                                  IRQ_TYPE_EDGE_RISING)>,
 708                                      <GIC_PPI 5 (GIC_CPU_MASK_SIMPLE(2) |
 709                                                  IRQ_TYPE_EDGE_RISING)>;
 710                         reg = <0x0200a000 0x100>;
 711                         clock-frequency = <25000000>,
 712                                           <32768>;
 713                         clocks = <&sleep_clk>;
 714                         clock-names = "sleep";
 715                         cpu-offset = <0x80000>;
 716                 };
 717
 718                 acc0: clock-controller@2088000 {
 719                         compatible = "qcom,kpss-acc-v1";
 720                         reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
 721                         clock-output-names = "acpu0_aux";
 722                 };
 723
 724                 acc1: clock-controller@2098000 {
 725                         compatible = "qcom,kpss-acc-v1";
 726                         reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
 727                         clock-output-names = "acpu1_aux";
 728                 };
 729
 730                 l2cc: clock-controller@2011000 {
 731                         compatible = "qcom,kpss-gcc", "syscon";
 732                         reg = <0x2011000 0x1000>;
 733                         clock-output-names = "acpu_l2_aux";
 734                 };
 735
 736                 saw0: regulator@2089000 {
 737                         compatible = "qcom,saw2", "qcom,apq8064-saw2-v1.1-cpu", "syscon";
 738                         reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
 739                         regulator;
 740                 };
 741
 742                 saw1: regulator@2099000 {
 743                         compatible = "qcom,saw2", "qcom,apq8064-saw2-v1.1-cpu", "syscon";
 744                         reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
 745                         regulator;
 746                 };
 747
 748                 saw_l2: regulator@02012000 {
 749                         compatible = "qcom,saw2", "syscon";
 750                         reg = <0x02012000 0x1000>;
 751                         regulator;
 752                 };
 753
 754                 sic_non_secure: sic-non-secure@12100000 {
 755                         compatible = "syscon";
 756                         reg = <0x12100000 0x10000>;
 757                 };
 758
 759                 gsbi2: gsbi@12480000 {
 760                         compatible = "qcom,gsbi-v1.0.0";
 761                         cell-index = <2>;
 762                         reg = <0x12480000 0x100>;
 763                         clocks = <&gcc GSBI2_H_CLK>;
 764                         clock-names = "iface";
 765                         #address-cells = <1>;
 766                         #size-cells = <1>;
 767                         ranges;
 768                         status = "disabled";
 769
 770                         syscon-tcsr = <&tcsr>;
 771
 772                         uart2: serial@12490000 {
 773                                 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
 774                                 reg = <0x12490000 0x1000>,
 775                                       <0x12480000 0x1000>;
 776                                 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
 777                                 clocks = <&gcc GSBI2_UART_CLK>, <&gcc GSBI2_H_CLK>;
 778                                 clock-names = "core", "iface";
 779                                 status = "disabled";
 780                         };
 781
 782                         i2c@124a0000 {
 783                                 compatible = "qcom,i2c-qup-v1.1.1";
 784                                 reg = <0x124a0000 0x1000>;
 785                                 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
 786
 787                                 clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
 788                                 clock-names = "core", "iface";
 789                                 status = "disabled";
 790
 791                                 #address-cells = <1>;
 792                                 #size-cells = <0>;
 793                         };
 794
 795                 };
 796
 797                 gsbi4: gsbi@16300000 {
 798                         compatible = "qcom,gsbi-v1.0.0";
 799                         cell-index = <4>;
 800                         reg = <0x16300000 0x100>;
 801                         clocks = <&gcc GSBI4_H_CLK>;
 802                         clock-names = "iface";
 803                         #address-cells = <1>;
 804                         #size-cells = <1>;
 805                         ranges;
 806                         status = "disabled";
 807
 808                         syscon-tcsr = <&tcsr>;
 809
 810                         gsbi4_serial: serial@16340000 {
 811                                 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
 812                                 reg = <0x16340000 0x1000>,
 813                                       <0x16300000 0x1000>;
 814                                 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
 815                                 clocks = <&gcc GSBI4_UART_CLK>, <&gcc GSBI4_H_CLK>;
 816                                 clock-names = "core", "iface";
 817                                 status = "disabled";
 818                         };
 819
 820                         i2c@16380000 {
 821                                 compatible = "qcom,i2c-qup-v1.1.1";
 822                                 reg = <0x16380000 0x1000>;
 823                                 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
 824
 825                                 clocks = <&gcc GSBI4_QUP_CLK>, <&gcc GSBI4_H_CLK>;
 826                                 clock-names = "core", "iface";
 827                                 status = "disabled";
 828
 829                                 #address-cells = <1>;
 830                                 #size-cells = <0>;
 831                         };
 832                 };
 833
 834                 gsbi5: gsbi@1a200000 {
 835                         compatible = "qcom,gsbi-v1.0.0";
 836                         cell-index = <5>;
 837                         reg = <0x1a200000 0x100>;
 838                         clocks = <&gcc GSBI5_H_CLK>;
 839                         clock-names = "iface";
 840                         #address-cells = <1>;
 841                         #size-cells = <1>;
 842                         ranges;
 843                         status = "disabled";
 844
 845                         syscon-tcsr = <&tcsr>;
 846
 847                         uart5: serial@1a240000 {
 848                                 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
 849                                 reg = <0x1a240000 0x1000>,
 850                                       <0x1a200000 0x1000>;
 851                                 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
 852                                 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
 853                                 clock-names = "core", "iface";
 854                                 status = "disabled";
 855                         };
 856
 857                         i2c@1a280000 {
 858                                 compatible = "qcom,i2c-qup-v1.1.1";
 859                                 reg = <0x1a280000 0x1000>;
 860                                 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
 861
 862                                 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
 863                                 clock-names = "core", "iface";
 864                                 status = "disabled";
 865
 866                                 #address-cells = <1>;
 867                                 #size-cells = <0>;
 868                         };
 869
 870                         spi@1a280000 {
 871                                 compatible = "qcom,spi-qup-v1.1.1";
 872                                 reg = <0x1a280000 0x1000>;
 873                                 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
 874
 875                                 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
 876                                 clock-names = "core", "iface";
 877                                 status = "disabled";
 878
 879                                 #address-cells = <1>;
 880                                 #size-cells = <0>;
 881                         };
 882                 };
 883
 884                 gsbi7: gsbi@16600000 {
 885                         status = "disabled";
 886                         compatible = "qcom,gsbi-v1.0.0";
 887                         cell-index = <7>;
 888                         reg = <0x16600000 0x100>;
 889                         clocks = <&gcc GSBI7_H_CLK>;
 890                         clock-names = "iface";
 891                         #address-cells = <1>;
 892                         #size-cells = <1>;
 893                         ranges;
 894                         syscon-tcsr = <&tcsr>;
 895
 896                         gsbi7_serial: serial@16640000 {
 897                                 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
 898                                 reg = <0x16640000 0x1000>,
 899                                       <0x16600000 0x1000>;
 900                                 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
 901                                 clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
 902                                 clock-names = "core", "iface";
 903                                 status = "disabled";
 904                         };
 905                 };
 906
 907                 sata_phy: sata-phy@1b400000 {
 908                         compatible = "qcom,ipq806x-sata-phy";
 909                         reg = <0x1b400000 0x200>;
 910
 911                         clocks = <&gcc SATA_PHY_CFG_CLK>;
 912                         clock-names = "cfg";
 913
 914                         #phy-cells = <0>;
 915                         status = "disabled";
 916                 };
 917
 918                 sata: sata@29000000 {
 919                         compatible = "qcom,ipq806x-ahci", "generic-ahci";
 920                         reg = <0x29000000 0x180>;
 921
 922                         ports-implemented = <0x1>;
 923
 924                         interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
 925
 926                         clocks = <&gcc SFAB_SATA_S_H_CLK>,
 927                                  <&gcc SATA_H_CLK>,
 928                                  <&gcc SATA_A_CLK>,
 929                                  <&gcc SATA_RXOOB_CLK>,
 930                                  <&gcc SATA_PMALIVE_CLK>;
 931                         clock-names = "slave_face", "iface", "core",
 932                                         "rxoob", "pmalive";
 933
 934                         assigned-clocks = <&gcc SATA_RXOOB_CLK>, <&gcc SATA_PMALIVE_CLK>;
 935                         assigned-clock-rates = <100000000>, <100000000>;
 936
 937                         phys = <&sata_phy>;
 938                         phy-names = "sata-phy";
 939                         status = "disabled";
 940                 };
 941
 942                 qcom,ssbi@500000 {
 943                         compatible = "qcom,ssbi";
 944                         reg = <0x00500000 0x1000>;
 945                         qcom,controller-type = "pmic-arbiter";
 946                 };
 947
 948                 gcc: clock-controller@900000 {
 949                         compatible = "qcom,gcc-ipq8064";
 950                         reg = <0x00900000 0x4000>;
 951                         #clock-cells = <1>;
 952                         #reset-cells = <1>;
 953                         #power-domain-cells = <1>;
 954                 };
 955
 956                 tsens: thermal-sensor@900000 {
 957                         compatible = "qcom,ipq8064-tsens";
 958                         reg = <0x900000 0x3680>;
 959                         nvmem-cells = <&tsens_calib>, <&tsens_backup>;
 960                         nvmem-cell-names = "calib", "calib_backup";
 961                         interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
 962                         #thermal-sensor-cells = <1>;
 963                 };
 964
 965                 tcsr: syscon@1a400000 {
 966                         compatible = "qcom,tcsr-ipq8064", "syscon";
 967                         reg = <0x1a400000 0x100>;
 968                 };
 969
 970                 lcc: clock-controller@28000000 {
 971                         compatible = "qcom,lcc-ipq8064";
 972                         reg = <0x28000000 0x1000>;
 973                         #clock-cells = <1>;
 974                         #reset-cells = <1>;
 975                 };
 976
 977                 sfpb_mutex_block: syscon@1200600 {
 978                         compatible = "syscon";
 979                         reg = <0x01200600 0x100>;
 980                 };
 981
 982                 hs_phy_0: hs_phy_0 {
 983                         compatible = "qcom,dwc3-hs-usb-phy";
 984                         regmap = <&usb3_0>;
 985                         clocks = <&gcc USB30_0_UTMI_CLK>;
 986                         clock-names = "ref";
 987                         #phy-cells = <0>;
 988                 };
 989
 990                 ss_phy_0: ss_phy_0 {
 991                         compatible = "qcom,dwc3-ss-usb-phy";
 992                         regmap = <&usb3_0>;
 993                         clocks = <&gcc USB30_0_MASTER_CLK>;
 994                         clock-names = "ref";
 995                         #phy-cells = <0>;
 996                 };
 997
 998                 usb3_0: usb3@110f8800 {
 999                         compatible = "qcom,dwc3", "syscon";
1000                         #address-cells = <1>;
1001                         #size-cells = <1>;
1002                         reg = <0x110f8800 0x8000>;
1003                         clocks = <&gcc USB30_0_MASTER_CLK>;
1004                         clock-names = "core";
1005
1006                         ranges;
1007
1008                         resets = <&gcc USB30_0_MASTER_RESET>;
1009                         reset-names = "master";
1010
1011                         status = "disabled";
1012
1013                         dwc3_0: dwc3@11000000 {
1014                                 compatible = "snps,dwc3";
1015                                 reg = <0x11000000 0xcd00>;
1016                                 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
1017                                 phys = <&hs_phy_0>, <&ss_phy_0>;
1018                                 phy-names = "usb2-phy", "usb3-phy";
1019                                 dr_mode = "host";
1020                                 snps,dis_u3_susphy_quirk;
1021                         };
1022                 };
1023
1024                 hs_phy_1: hs_phy_1 {
1025                         compatible = "qcom,dwc3-hs-usb-phy";
1026                         regmap = <&usb3_1>;
1027                         clocks = <&gcc USB30_1_UTMI_CLK>;
1028                         clock-names = "ref";
1029                         #phy-cells = <0>;
1030                 };
1031
1032                 ss_phy_1: ss_phy_1 {
1033                         compatible = "qcom,dwc3-ss-usb-phy";
1034                         regmap = <&usb3_1>;
1035                         clocks = <&gcc USB30_1_MASTER_CLK>;
1036                         clock-names = "ref";
1037                         #phy-cells = <0>;
1038                 };
1039
1040                 usb3_1: usb3@100f8800 {
1041                         compatible = "qcom,dwc3", "syscon";
1042                         #address-cells = <1>;
1043                         #size-cells = <1>;
1044                         reg = <0x100f8800 0x8000>;
1045                         clocks = <&gcc USB30_1_MASTER_CLK>;
1046                         clock-names = "core";
1047
1048                         ranges;
1049
1050                         resets = <&gcc USB30_1_MASTER_RESET>;
1051                         reset-names = "master";
1052
1053                         status = "disabled";
1054
1055                         dwc3_1: dwc3@10000000 {
1056                                 compatible = "snps,dwc3";
1057                                 reg = <0x10000000 0xcd00>;
1058                                 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
1059                                 phys = <&hs_phy_1>, <&ss_phy_1>;
1060                                 phy-names = "usb2-phy", "usb3-phy";
1061                                 dr_mode = "host";
1062                                 snps,dis_u3_susphy_quirk;
1063                         };
1064                 };
1065
1066                 pcie0: pci@1b500000 {
1067                         compatible = "qcom,pcie-ipq8064";
1068                         reg = <0x1b500000 0x1000
1069                                0x1b502000 0x80
1070                                0x1b600000 0x100
1071                                0x0ff00000 0x100000>;
1072                         reg-names = "dbi", "elbi", "parf", "config";
1073                         device_type = "pci";
1074                         linux,pci-domain = <0>;
1075                         bus-range = <0x00 0xff>;
1076                         num-lanes = <1>;
1077                         #address-cells = <3>;
1078                         #size-cells = <2>;
1079
1080                         ranges = <0x81000000 0 0x0fe00000 0x0fe00000 0 0x00100000   /* downstream I/O */
1081                                   0x82000000 0 0x08000000 0x08000000 0 0x07e00000>; /* non-prefetchable memory */
1082
1083                         interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
1084                         interrupt-names = "msi";
1085                         #interrupt-cells = <1>;
1086                         interrupt-map-mask = <0 0 0 0x7>;
1087                         interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1088                                         <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1089                                         <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1090                                         <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1091
1092                         clocks = <&gcc PCIE_A_CLK>,
1093                                  <&gcc PCIE_H_CLK>,
1094                                  <&gcc PCIE_PHY_CLK>,
1095                                  <&gcc PCIE_AUX_CLK>,
1096                                  <&gcc PCIE_ALT_REF_CLK>;
1097                         clock-names = "core", "iface", "phy", "aux", "ref";
1098
1099                         assigned-clocks = <&gcc PCIE_ALT_REF_CLK>;
1100                         assigned-clock-rates = <100000000>;
1101
1102                         resets = <&gcc PCIE_ACLK_RESET>,
1103                                  <&gcc PCIE_HCLK_RESET>,
1104                                  <&gcc PCIE_POR_RESET>,
1105                                  <&gcc PCIE_PCI_RESET>,
1106                                  <&gcc PCIE_PHY_RESET>,
1107                                  <&gcc PCIE_EXT_RESET>;
1108                         reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
1109
1110                         pinctrl-0 = <&pcie0_pins>;
1111                         pinctrl-names = "default";
1112
1113                         perst-gpios = <&qcom_pinmux 3 GPIO_ACTIVE_LOW>;
1114
1115                         phy-tx0-term-offset = <7>;
1116
1117                         status = "disabled";
1118                 };
1119
1120                 pcie1: pci@1b700000 {
1121                         compatible = "qcom,pcie-ipq8064";
1122                         reg = <0x1b700000 0x1000
1123                                0x1b702000 0x80
1124                                0x1b800000 0x100
1125                                0x31f00000 0x100000>;
1126                         reg-names = "dbi", "elbi", "parf", "config";
1127                         device_type = "pci";
1128                         linux,pci-domain = <1>;
1129                         bus-range = <0x00 0xff>;
1130                         num-lanes = <1>;
1131                         #address-cells = <3>;
1132                         #size-cells = <2>;
1133
1134                         ranges = <0x81000000 0 0x31e00000 0x31e00000 0 0x00100000   /* downstream I/O */
1135                                   0x82000000 0 0x2e000000 0x2e000000 0 0x03e00000>; /* non-prefetchable memory */
1136
1137                         interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
1138                         interrupt-names = "msi";
1139                         #interrupt-cells = <1>;
1140                         interrupt-map-mask = <0 0 0 0x7>;
1141                         interrupt-map = <0 0 0 1 &intc 0 58 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1142                                         <0 0 0 2 &intc 0 59 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1143                                         <0 0 0 3 &intc 0 60 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1144                                         <0 0 0 4 &intc 0 61 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1145
1146                         clocks = <&gcc PCIE_1_A_CLK>,
1147                                  <&gcc PCIE_1_H_CLK>,
1148                                  <&gcc PCIE_1_PHY_CLK>,
1149                                  <&gcc PCIE_1_AUX_CLK>,
1150                                  <&gcc PCIE_1_ALT_REF_CLK>;
1151                         clock-names = "core", "iface", "phy", "aux", "ref";
1152
1153                         assigned-clocks = <&gcc PCIE_1_ALT_REF_CLK>;
1154                         assigned-clock-rates = <100000000>;
1155
1156                         resets = <&gcc PCIE_1_ACLK_RESET>,
1157                                  <&gcc PCIE_1_HCLK_RESET>,
1158                                  <&gcc PCIE_1_POR_RESET>,
1159                                  <&gcc PCIE_1_PCI_RESET>,
1160                                  <&gcc PCIE_1_PHY_RESET>,
1161                                  <&gcc PCIE_1_EXT_RESET>;
1162                         reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
1163
1164                         pinctrl-0 = <&pcie1_pins>;
1165                         pinctrl-names = "default";
1166
1167                         perst-gpios = <&qcom_pinmux 48 GPIO_ACTIVE_LOW>;
1168
1169                         phy-tx0-term-offset = <7>;
1170
1171                         status = "disabled";
1172                 };
1173
1174                 pcie2: pci@1b900000 {
1175                         compatible = "qcom,pcie-ipq8064";
1176                         reg = <0x1b900000 0x1000
1177                                0x1b902000 0x80
1178                                0x1ba00000 0x100
1179                                0x35f00000 0x100000>;
1180                         reg-names = "dbi", "elbi", "parf", "config";
1181                         device_type = "pci";
1182                         linux,pci-domain = <2>;
1183                         bus-range = <0x00 0xff>;
1184                         num-lanes = <1>;
1185                         #address-cells = <3>;
1186                         #size-cells = <2>;
1187
1188                         ranges = <0x81000000 0 0x35e00000 0x35e00000 0 0x00100000   /* downstream I/O */
1189                                   0x82000000 0 0x32000000 0x32000000 0 0x03e00000>; /* non-prefetchable memory */
1190
1191                         interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
1192                         interrupt-names = "msi";
1193                         #interrupt-cells = <1>;
1194                         interrupt-map-mask = <0 0 0 0x7>;
1195                         interrupt-map = <0 0 0 1 &intc 0 72 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1196                                         <0 0 0 2 &intc 0 73 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1197                                         <0 0 0 3 &intc 0 74 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1198                                         <0 0 0 4 &intc 0 75 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1199
1200                         clocks = <&gcc PCIE_2_A_CLK>,
1201                                  <&gcc PCIE_2_H_CLK>,
1202                                  <&gcc PCIE_2_PHY_CLK>,
1203                                  <&gcc PCIE_2_AUX_CLK>,
1204                                  <&gcc PCIE_2_ALT_REF_CLK>;
1205                         clock-names = "core", "iface", "phy", "aux", "ref";
1206
1207                         assigned-clocks = <&gcc PCIE_2_ALT_REF_CLK>;
1208                         assigned-clock-rates = <100000000>;
1209
1210                         resets = <&gcc PCIE_2_ACLK_RESET>,
1211                                  <&gcc PCIE_2_HCLK_RESET>,
1212                                  <&gcc PCIE_2_POR_RESET>,
1213                                  <&gcc PCIE_2_PCI_RESET>,
1214                                  <&gcc PCIE_2_PHY_RESET>,
1215                                  <&gcc PCIE_2_EXT_RESET>;
1216                         reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
1217
1218                         pinctrl-0 = <&pcie2_pins>;
1219                         pinctrl-names = "default";
1220
1221                         perst-gpios = <&qcom_pinmux 63 GPIO_ACTIVE_LOW>;
1222
1223                         phy-tx0-term-offset = <7>;
1224
1225                         status = "disabled";
1226                 };
1227
1228                 adm_dma: dma@18300000 {
1229                         compatible = "qcom,adm";
1230                         reg = <0x18300000 0x100000>;
1231                         interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
1232                         #dma-cells = <1>;
1233
1234                         clocks = <&gcc ADM0_CLK>, <&gcc ADM0_PBUS_CLK>;
1235                         clock-names = "core", "iface";
1236
1237                         resets = <&gcc ADM0_RESET>,
1238                                  <&gcc ADM0_PBUS_RESET>,
1239                                  <&gcc ADM0_C0_RESET>,
1240                                  <&gcc ADM0_C1_RESET>,
1241                                  <&gcc ADM0_C2_RESET>;
1242                         reset-names = "clk", "pbus", "c0", "c1", "c2";
1243                         qcom,ee = <0>;
1244
1245                         status = "disabled";
1246                 };
1247
1248                 nand: nand@1ac00000 {
1249                         compatible = "qcom,ipq806x-nand";
1250                         reg = <0x1ac00000 0x800>;
1251
1252                         clocks = <&gcc EBI2_CLK>,
1253                                  <&gcc EBI2_AON_CLK>;
1254                         clock-names = "core", "aon";
1255
1256                         dmas = <&adm_dma 3>;
1257                         dma-names = "rxtx";
1258                         qcom,cmd-crci = <15>;
1259                         qcom,data-crci = <3>;
1260
1261                         status = "disabled";
1262
1263                         #address-cells = <1>;
1264                         #size-cells = <0>;
1265                 };
1266
1267                 nss_common: syscon@03000000 {
1268                         compatible = "syscon";
1269                         reg = <0x03000000 0x0000FFFF>;
1270                 };
1271
1272                 qsgmii_csr: syscon@1bb00000 {
1273                         compatible = "syscon";
1274                         reg = <0x1bb00000 0x000001FF>;
1275                 };
1276
1277                 stmmac_axi_setup: stmmac-axi-config {
1278                         snps,wr_osr_lmt = <7>;
1279                         snps,rd_osr_lmt = <7>;
1280                         snps,blen = <16 0 0 0 0 0 0>;
1281                 };
1282
1283                 gmac0: ethernet@37000000 {
1284                         device_type = "network";
1285                         compatible = "qcom,ipq806x-gmac";
1286                         reg = <0x37000000 0x200000>;
1287                         interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
1288                         interrupt-names = "macirq";
1289
1290                         snps,axi-config = <&stmmac_axi_setup>;
1291                         snps,pbl = <32>;
1292                         snps,aal = <1>;
1293
1294                         qcom,nss-common = <&nss_common>;
1295                         qcom,qsgmii-csr = <&qsgmii_csr>;
1296
1297                         clocks = <&gcc GMAC_CORE1_CLK>;
1298                         clock-names = "stmmaceth";
1299
1300                         resets = <&gcc GMAC_CORE1_RESET>;
1301                         reset-names = "stmmaceth";
1302
1303                         status = "disabled";
1304                 };
1305
1306                 gmac1: ethernet@37200000 {
1307                         device_type = "network";
1308                         compatible = "qcom,ipq806x-gmac";
1309                         reg = <0x37200000 0x200000>;
1310                         interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
1311                         interrupt-names = "macirq";
1312
1313                         snps,axi-config = <&stmmac_axi_setup>;
1314                         snps,pbl = <32>;
1315                         snps,aal = <1>;
1316
1317                         qcom,nss-common = <&nss_common>;
1318                         qcom,qsgmii-csr = <&qsgmii_csr>;
1319
1320                         clocks = <&gcc GMAC_CORE2_CLK>;
1321                         clock-names = "stmmaceth";
1322
1323                         resets = <&gcc GMAC_CORE2_RESET>;
1324                         reset-names = "stmmaceth";
1325
1326                         status = "disabled";
1327                 };
1328
1329                 gmac2: ethernet@37400000 {
1330                         device_type = "network";
1331                         compatible = "qcom,ipq806x-gmac";
1332                         reg = <0x37400000 0x200000>;
1333                         interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
1334                         interrupt-names = "macirq";
1335
1336                         snps,axi-config = <&stmmac_axi_setup>;
1337                         snps,pbl = <32>;
1338                         snps,aal = <1>;
1339
1340                         qcom,nss-common = <&nss_common>;
1341                         qcom,qsgmii-csr = <&qsgmii_csr>;
1342
1343                         clocks = <&gcc GMAC_CORE3_CLK>;
1344                         clock-names = "stmmaceth";
1345
1346                         resets = <&gcc GMAC_CORE3_RESET>;
1347                         reset-names = "stmmaceth";
1348
1349                         status = "disabled";
1350                 };
1351
1352                 gmac3: ethernet@37600000 {
1353                         device_type = "network";
1354                         compatible = "qcom,ipq806x-gmac";
1355                         reg = <0x37600000 0x200000>;
1356                         interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
1357                         interrupt-names = "macirq";
1358
1359                         snps,axi-config = <&stmmac_axi_setup>;
1360                         snps,pbl = <32>;
1361                         snps,aal = <1>;
1362
1363                         qcom,nss-common = <&nss_common>;
1364                         qcom,qsgmii-csr = <&qsgmii_csr>;
1365
1366                         clocks = <&gcc GMAC_CORE4_CLK>;
1367                         clock-names = "stmmaceth";
1368
1369                         resets = <&gcc GMAC_CORE4_RESET>;
1370                         reset-names = "stmmaceth";
1371
1372                         status = "disabled";
1373                 };
1374
1375                 /* Temporary fixed regulator */
1376                 vsdcc_fixed: vsdcc-regulator {
1377                         compatible = "regulator-fixed";
1378                         regulator-name = "SDCC Power";
1379                         regulator-min-microvolt = <3300000>;
1380                         regulator-max-microvolt = <3300000>;
1381                         regulator-always-on;
1382                 };
1383
1384                 sdcc1bam:dma@12402000 {
1385                         compatible = "qcom,bam-v1.3.0";
1386                         reg = <0x12402000 0x8000>;
1387                         interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1388                         clocks = <&gcc SDC1_H_CLK>;
1389                         clock-names = "bam_clk";
1390                         #dma-cells = <1>;
1391                         qcom,ee = <0>;
1392                 };
1393
1394                 sdcc3bam:dma@12182000 {
1395                         compatible = "qcom,bam-v1.3.0";
1396                         reg = <0x12182000 0x8000>;
1397                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1398                         clocks = <&gcc SDC3_H_CLK>;
1399                         clock-names = "bam_clk";
1400                         #dma-cells = <1>;
1401                         qcom,ee = <0>;
1402                 };
1403
1404                 amba {
1405                         compatible = "arm,amba-bus";
1406                         #address-cells = <1>;
1407                         #size-cells = <1>;
1408                         ranges;
1409                         sdcc1: sdcc@12400000 {
1410                                 status          = "disabled";
1411                                 compatible      = "arm,pl18x", "arm,primecell";
1412                                 arm,primecell-periphid = <0x00051180>;
1413                                 reg             = <0x12400000 0x2000>;
1414                                 interrupts      = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
1415                                 interrupt-names = "cmd_irq";
1416                                 clocks          = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
1417                                 clock-names     = "mclk", "apb_pclk";
1418                                 bus-width       = <8>;
1419                                 max-frequency   = <96000000>;
1420                                 non-removable;
1421                                 cap-sd-highspeed;
1422                                 cap-mmc-highspeed;
1423                                 vmmc-supply = <&vsdcc_fixed>;
1424                                 dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
1425                                 dma-names = "tx", "rx";
1426                         };
1427
1428                         sdcc3: sdcc@12180000 {
1429                                 compatible      = "arm,pl18x", "arm,primecell";
1430                                 arm,primecell-periphid = <0x00051180>;
1431                                 status          = "disabled";
1432                                 reg             = <0x12180000 0x2000>;
1433                                 interrupts      = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
1434                                 interrupt-names = "cmd_irq";
1435                                 clocks          = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
1436                                 clock-names     = "mclk", "apb_pclk";
1437                                 bus-width       = <8>;
1438                                 cap-sd-highspeed;
1439                                 cap-mmc-highspeed;
1440                                 max-frequency   = <192000000>;
1441                                 #mmc-ddr-1_8v;
1442                                 sd-uhs-sdr104;
1443                                 sd-uhs-ddr50;
1444                                 vqmmc-supply = <&vsdcc_fixed>;
1445                                 dmas = <&sdcc3bam 2>, <&sdcc3bam 1>;
1446                                 dma-names = "tx", "rx";
1447                         };
1448                 };
1449         };
1450
1451         sfpb_mutex: sfpb-mutex {
1452                 compatible = "qcom,sfpb-mutex";
1453                 syscon = <&sfpb_mutex_block 4 4>;
1454
1455                 #hwlock-cells = <1>;
1456         };
1457
1458         smem {
1459                 compatible = "qcom,smem";
1460                 memory-region = <&smem>;
1461                 hwlocks = <&sfpb_mutex 3>;
1462         };
1463 };