target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8065.dtsi

   1 /dts-v1/;
   2
   3 #include "skeleton.dtsi"
   4 #include <dt-bindings/clock/qcom,gcc-ipq806x.h>
   5 #include <dt-bindings/clock/qcom,lcc-ipq806x.h>
   6 #include <dt-bindings/mfd/qcom-rpm.h>
   7 #include <dt-bindings/soc/qcom,gsbi.h>
   8 #include <dt-bindings/reset/qcom,gcc-ipq806x.h>
   9 #include <dt-bindings/interrupt-controller/arm-gic.h>
  10 #include <dt-bindings/interrupt-controller/irq.h>
  11 #include <dt-bindings/gpio/gpio.h>
  12
  13 / {
  14         model = "Qualcomm IPQ8065";
  15         compatible = "qcom,ipq8065", "qcom,ipq8064";
  16         interrupt-parent = <&intc>;
  17
  18         cpus {
  19                 #address-cells = <1>;
  20                 #size-cells = <0>;
  21
  22                 cpu0: cpu@0 {
  23                         compatible = "qcom,krait";
  24                         enable-method = "qcom,kpss-acc-v1";
  25                         device_type = "cpu";
  26                         reg = <0>;
  27                         next-level-cache = <&L2>;
  28                         qcom,acc = <&acc0>;
  29                         qcom,saw = <&saw0>;
  30                         clocks = <&kraitcc 0>, <&kraitcc 4>;
  31                         clock-names = "cpu", "l2";
  32                         qcom,imem = <&imem>;
  33                         clock-latency = <100000>;
  34                         cpu-supply = <&smb208_s2a>;
  35                         voltage-tolerance = <5>;
  36                         cooling-min-state = <0>;
  37                         cooling-max-state = <10>;
  38                         #cooling-cells = <2>;
  39                         cpu-idle-states = <&CPU_SPC>;
  40                 };
  41
  42                 cpu1: cpu@1 {
  43                         compatible = "qcom,krait";
  44                         enable-method = "qcom,kpss-acc-v1";
  45                         device_type = "cpu";
  46                         reg = <1>;
  47                         next-level-cache = <&L2>;
  48                         qcom,acc = <&acc1>;
  49                         qcom,saw = <&saw1>;
  50                         clocks = <&kraitcc 1>, <&kraitcc 4>;
  51                         clock-names = "cpu", "l2";
  52                         qcom,imem = <&imem>;
  53                         clock-latency = <100000>;
  54                         cpu-supply = <&smb208_s2b>;
  55                         cooling-min-state = <0>;
  56                         cooling-max-state = <10>;
  57                         #cooling-cells = <2>;
  58                         cpu-idle-states = <&CPU_SPC>;
  59                 };
  60
  61                 L2: l2-cache {
  62                         compatible = "cache";
  63                         cache-level = <2>;
  64                         qcom,saw = <&saw_l2>;
  65                 };
  66
  67                 qcom,l2 {
  68                         qcom,l2-rates = <384000000 1000000000 1200000000>;
  69                 };
  70
  71                 idle-states {
  72                         CPU_SPC: spc {
  73                                 compatible = "qcom,idle-state-spc",
  74                                                 "arm,idle-state";
  75                                 entry-latency-us = <400>;
  76                                 exit-latency-us = <900>;
  77                                 min-residency-us = <3000>;
  78                         };
  79                 };
  80         };
  81
  82         cpu-pmu {
  83                 compatible = "qcom,krait-pmu";
  84                 interrupts = <1 10 0x304>;
  85         };
  86
  87         reserved-memory {
  88                 #address-cells = <1>;
  89                 #size-cells = <1>;
  90                 ranges;
  91
  92                 nss@40000000 {
  93                         reg = <0x40000000 0x1000000>;
  94                         no-map;
  95                 };
  96
  97                 smem: smem@41000000 {
  98                         reg = <0x41000000 0x200000>;
  99                         no-map;
 100                 };
 101         };
 102
 103         clocks {
 104
 105                 cxo_board {
 106                         compatible = "fixed-clock";
 107                         #clock-cells = <0>;
 108                         clock-frequency = <25000000>;
 109                 };
 110
 111                 pxo_board {
 112                         compatible = "fixed-clock";
 113                         #clock-cells = <0>;
 114                         clock-frequency = <25000000>;
 115                 };
 116
 117                 sleep_clk: sleep_clk {
 118                         compatible = "fixed-clock";
 119                         clock-frequency = <32768>;
 120                         #clock-cells = <0>;
 121                 };
 122         };
 123
 124         kraitcc: clock-controller {
 125                 compatible = "qcom,krait-cc-v1";
 126                 #clock-cells = <1>;
 127         };
 128
 129         qcom,pvs {
 130                 qcom,pvs-format-a;
 131                 qcom,speed0-pvs0-bin-v0 =
 132                         < 1725000000 1262500 >,
 133                         < 1400000000 1175000 >,
 134                         < 1000000000 1100000 >,
 135                          < 800000000 1050000 >,
 136                          < 600000000 1000000 >,
 137                          < 384000000 975000 >;
 138                 qcom,speed0-pvs1-bin-v0 =
 139                         < 1725000000 1262500 >,
 140                         < 1400000000 1175000 >,
 141                         < 1000000000 1100000 >,
 142                          < 800000000 1050000 >,
 143                          < 600000000 1000000 >,
 144                          < 384000000 950000 >;
 145                 qcom,speed0-pvs2-bin-v0 =
 146                         < 1725000000 1200000 >,
 147                         < 1400000000 1125000 >,
 148                         < 1000000000 1050000 >,
 149                          < 800000000 1000000 >,
 150                          < 600000000 950000 >,
 151                          < 384000000 925000 >;
 152                 qcom,speed0-pvs3-bin-v0 =
 153                         < 1725000000 1175000 >,
 154                         < 1400000000 1100000 >,
 155                         < 1000000000 1025000 >,
 156                          < 800000000 975000 >,
 157                          < 600000000 925000 >,
 158                          < 384000000 900000 >;
 159                 qcom,speed0-pvs4-bin-v0 =
 160                         < 1725000000 1150000 >,
 161                         < 1400000000 1075000 >,
 162                         < 1000000000 1000000 >,
 163                          < 800000000 950000 >,
 164                          < 600000000 900000 >,
 165                          < 384000000 875000 >;
 166                 qcom,speed0-pvs5-bin-v0 =
 167                         < 1725000000 1100000 >,
 168                         < 1400000000 1025000 >,
 169                         < 1000000000 950000 >,
 170                          < 800000000 900000 >,
 171                          < 600000000 850000 >,
 172                          < 384000000 825000 >;
 173                 qcom,speed0-pvs6-bin-v0 =
 174                         < 1725000000 1050000 >,
 175                         < 1400000000 975000 >,
 176                         < 1000000000 900000 >,
 177                          < 800000000 850000 >,
 178                          < 600000000 800000 >,
 179                          < 384000000 775000 >;
 180         };
 181
 182         soc: soc {
 183                 #address-cells = <1>;
 184                 #size-cells = <1>;
 185                 ranges;
 186                 compatible = "simple-bus";
 187
 188                 lpass@28100000 {
 189                         compatible = "qcom,lpass-cpu";
 190                         status = "disabled";
 191                         clocks = <&lcc AHBIX_CLK>,
 192                                         <&lcc MI2S_OSR_CLK>,
 193                                         <&lcc MI2S_BIT_CLK>;
 194                         clock-names = "ahbix-clk",
 195                                         "mi2s-osr-clk",
 196                                         "mi2s-bit-clk";
 197                         interrupts = <0 85 1>;
 198                         interrupt-names = "lpass-irq-lpaif";
 199                         reg = <0x28100000 0x10000>;
 200                         reg-names = "lpass-lpaif";
 201                 };
 202
 203                 imem: memory@700000 {
 204                         compatible = "qcom,qfprom", "syscon";
 205                         reg = <0x00700000 0x1000>;
 206                         #address-cells = <1>;
 207                         #size-cells = <1>;
 208                         stride = <1>;
 209                         ranges = <0x0 0x00700000 0x1000>;
 210                 };
 211
 212                 rpm@108000 {
 213                         compatible = "qcom,rpm-ipq8064";
 214                         reg = <0x108000 0x1000>;
 215                         qcom,ipc = <&l2cc 0x8 2>;
 216
 217                         interrupts = <0 19 0>,
 218                                      <0 21 0>,
 219                                      <0 22 0>;
 220                         interrupt-names = "ack",
 221                                           "err",
 222                                           "wakeup";
 223
 224                         #address-cells = <1>;
 225                         #size-cells = <0>;
 226
 227                         rpmcc: clock-controller {
 228                                 compatible      = "qcom,rpmcc-ipq806x", "qcom,rpmcc";
 229                                 #clock-cells = <1>;
 230                         };
 231
 232                         smb208_regulators {
 233                                 compatible = "qcom,rpm-smb208-regulators";
 234
 235                                 smb208_s1a: s1a {
 236                                         regulator-min-microvolt = <1050000>;
 237                                         regulator-max-microvolt = <1150000>;
 238                                         qcom,switch-mode-frequency = <1200000>;
 239                                 };
 240
 241                                 smb208_s1b: s1b {
 242                                         regulator-min-microvolt = <1050000>;
 243                                         regulator-max-microvolt = <1150000>;
 244                                         qcom,switch-mode-frequency = <1200000>;
 245                                 };
 246
 247                                 smb208_s2a: s2a {
 248                                         regulator-min-microvolt = < 800000>;
 249                                         regulator-max-microvolt = <1275000>;
 250                                         qcom,switch-mode-frequency = <1200000>;
 251                                 };
 252
 253                                 smb208_s2b: s2b {
 254                                         regulator-min-microvolt = < 800000>;
 255                                         regulator-max-microvolt = <1275000>;
 256                                         qcom,switch-mode-frequency = <1200000>;
 257                                 };
 258                         };
 259                 };
 260
 261                 rng@1a500000 {
 262                         compatible = "qcom,prng";
 263                         reg = <0x1a500000 0x200>;
 264                         clocks = <&gcc PRNG_CLK>;
 265                         clock-names = "core";
 266                 };
 267
 268                 qcom,msm-imem@2A03F000 {
 269                         compatible = "qcom,msm-imem";
 270                         reg = <0x2A03F000 0x1000>; /* Address and size of IMEM */
 271                         ranges = <0x0 0x2A03F000 0x1000>;
 272                         #address-cells = <1>;
 273                         #size-cells = <1>;
 274
 275                         download_mode@0 {
 276                                 compatible = "qcom,msm-imem-download_mode";
 277                                 reg = <0x0 8>;
 278                         };
 279
 280                         restart_reason@65c {
 281                                 compatible = "qcom,msm-imem-restart_reason";
 282                                 reg = <0x65c 4>;
 283                         };
 284
 285                         l2_dump_offset@14 {
 286                                 compatible = "qcom,msm-imem-l2_dump_offset";
 287                                 reg = <0x14 8>;
 288                         };
 289                 };
 290
 291                 qcom_pinmux: pinmux@800000 {
 292                         compatible = "qcom,ipq8064-pinctrl";
 293                         reg = <0x800000 0x4000>;
 294
 295                         gpio-controller;
 296                         #gpio-cells = <2>;
 297                         interrupt-controller;
 298                         #interrupt-cells = <2>;
 299                         interrupts = <0 16 0x4>;
 300
 301                         pcie0_pins: pcie0_pinmux {
 302                                 mux {
 303                                         pins = "gpio3";
 304                                         function = "pcie1_rst";
 305                                         drive-strength = <12>;
 306                                         bias-disable;
 307                                 };
 308                         };
 309
 310                         pcie1_pins: pcie1_pinmux {
 311                                 mux {
 312                                         pins = "gpio48";
 313                                         function = "pcie2_rst";
 314                                         drive-strength = <12>;
 315                                         bias-disable;
 316                                 };
 317                         };
 318
 319                         pcie2_pins: pcie2_pinmux {
 320                                 mux {
 321                                         pins = "gpio63";
 322                                         function = "pcie3_rst";
 323                                         drive-strength = <12>;
 324                                         bias-disable;
 325                                 };
 326                         };
 327                 };
 328
 329                 intc: interrupt-controller@2000000 {
 330                         compatible = "qcom,msm-qgic2";
 331                         interrupt-controller;
 332                         #interrupt-cells = <3>;
 333                         reg = <0x02000000 0x1000>,
 334                               <0x02002000 0x1000>;
 335                 };
 336
 337                 timer@200a000 {
 338                         compatible = "qcom,kpss-timer", "qcom,msm-timer";
 339                         interrupts = <1 1 0x301>,
 340                                      <1 2 0x301>,
 341                                      <1 3 0x301>,
 342                                      <1 4 0x301>,
 343                                      <1 5 0x301>;
 344                         reg = <0x0200a000 0x100>;
 345                         clock-frequency = <25000000>,
 346                                           <32768>;
 347                         clocks = <&sleep_clk>;
 348                         clock-names = "sleep";
 349                         cpu-offset = <0x80000>;
 350                 };
 351
 352                 acc0: clock-controller@2088000 {
 353                         compatible = "qcom,kpss-acc-v1";
 354                         reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
 355                         clock-output-names = "acpu0_aux";
 356                 };
 357
 358                 acc1: clock-controller@2098000 {
 359                         compatible = "qcom,kpss-acc-v1";
 360                         reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
 361                         clock-output-names = "acpu1_aux";
 362                 };
 363
 364                 l2cc: clock-controller@2011000 {
 365                         compatible = "qcom,kpss-gcc", "syscon";
 366                         reg = <0x2011000 0x1000>;
 367                         clock-output-names = "acpu_l2_aux";
 368                 };
 369
 370                 saw0: regulator@2089000 {
 371                         compatible = "qcom,saw2", "syscon";
 372                         reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
 373                         regulator;
 374                 };
 375
 376                 saw1: regulator@2099000 {
 377                         compatible = "qcom,saw2", "syscon";
 378                         reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
 379                         regulator;
 380                 };
 381
 382                 saw_l2: regulator@02012000 {
 383                         compatible = "qcom,saw2", "syscon";
 384                         reg = <0x02012000 0x1000>;
 385                         regulator;
 386                 };
 387
 388                 sic_non_secure: sic-non-secure@12100000 {
 389                         compatible = "syscon";
 390                         reg = <0x12100000 0x10000>;
 391                 };
 392
 393                 gsbi1: gsbi@12440000 {
 394                         compatible = "qcom,gsbi-v1.0.0";
 395                         cell-index = <1>;
 396                         reg = <0x12440000 0x100>;
 397                         clocks = <&gcc GSBI1_H_CLK>;
 398                         clock-names = "iface";
 399                         #address-cells = <1>;
 400                         #size-cells = <1>;
 401                         ranges;
 402                         status = "disabled";
 403
 404                         syscon-tcsr = <&tcsr>;
 405
 406                         uart1: serial@12450000 {
 407                                 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
 408                                 reg = <0x12450000 0x1000>,
 409                                       <0x12440000 0x1000>;
 410                                 interrupts = <0 193 0x0>;
 411                                 clocks = <&gcc GSBI1_UART_CLK>, <&gcc GSBI1_H_CLK>;
 412                                 clock-names = "core", "iface";
 413                                 status = "disabled";
 414                         };
 415
 416                         i2c@12460000 {
 417                                 compatible = "qcom,i2c-qup-v1.1.1";
 418                                 reg = <0x12460000 0x1000>;
 419                                 interrupts = <0 194 0>;
 420
 421                                 clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
 422                                 clock-names = "core", "iface";
 423                                 status = "disabled";
 424
 425                                 #address-cells = <1>;
 426                                 #size-cells = <0>;
 427                         };
 428
 429                 };
 430
 431                 gsbi2: gsbi@12480000 {
 432                         compatible = "qcom,gsbi-v1.0.0";
 433                         cell-index = <2>;
 434                         reg = <0x12480000 0x100>;
 435                         clocks = <&gcc GSBI2_H_CLK>;
 436                         clock-names = "iface";
 437                         #address-cells = <1>;
 438                         #size-cells = <1>;
 439                         ranges;
 440                         status = "disabled";
 441
 442                         syscon-tcsr = <&tcsr>;
 443
 444                         uart2: serial@12490000 {
 445                                 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
 446                                 reg = <0x12490000 0x1000>,
 447                                       <0x12480000 0x1000>;
 448                                 interrupts = <0 195 0x0>;
 449                                 clocks = <&gcc GSBI2_UART_CLK>, <&gcc GSBI2_H_CLK>;
 450                                 clock-names = "core", "iface";
 451                                 status = "disabled";
 452                         };
 453
 454                         i2c@124a0000 {
 455                                 compatible = "qcom,i2c-qup-v1.1.1";
 456                                 reg = <0x124a0000 0x1000>;
 457                                 interrupts = <0 196 0>;
 458
 459                                 clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
 460                                 clock-names = "core", "iface";
 461                                 status = "disabled";
 462
 463                                 #address-cells = <1>;
 464                                 #size-cells = <0>;
 465                         };
 466
 467                 };
 468
 469                 gsbi4: gsbi@16300000 {
 470                         compatible = "qcom,gsbi-v1.0.0";
 471                         cell-index = <4>;
 472                         reg = <0x16300000 0x100>;
 473                         clocks = <&gcc GSBI4_H_CLK>;
 474                         clock-names = "iface";
 475                         #address-cells = <1>;
 476                         #size-cells = <1>;
 477                         ranges;
 478                         status = "disabled";
 479
 480                         syscon-tcsr = <&tcsr>;
 481
 482                         uart4: serial@16340000 {
 483                                 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
 484                                 reg = <0x16340000 0x1000>,
 485                                       <0x16300000 0x1000>;
 486                                 interrupts = <0 152 0x0>;
 487                                 clocks = <&gcc GSBI4_UART_CLK>, <&gcc GSBI4_H_CLK>;
 488                                 clock-names = "core", "iface";
 489                                 status = "disabled";
 490                         };
 491
 492                         i2c@16380000 {
 493                                 compatible = "qcom,i2c-qup-v1.1.1";
 494                                 reg = <0x16380000 0x1000>;
 495                                 interrupts = <0 153 0>;
 496
 497                                 clocks = <&gcc GSBI4_QUP_CLK>, <&gcc GSBI4_H_CLK>;
 498                                 clock-names = "core", "iface";
 499                                 status = "disabled";
 500
 501                                 #address-cells = <1>;
 502                                 #size-cells = <0>;
 503                         };
 504                 };
 505
 506                 gsbi5: gsbi@1a200000 {
 507                         compatible = "qcom,gsbi-v1.0.0";
 508                         cell-index = <5>;
 509                         reg = <0x1a200000 0x100>;
 510                         clocks = <&gcc GSBI5_H_CLK>;
 511                         clock-names = "iface";
 512                         #address-cells = <1>;
 513                         #size-cells = <1>;
 514                         ranges;
 515                         status = "disabled";
 516
 517                         syscon-tcsr = <&tcsr>;
 518
 519                         uart5: serial@1a240000 {
 520                                 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
 521                                 reg = <0x1a240000 0x1000>,
 522                                       <0x1a200000 0x1000>;
 523                                 interrupts = <0 154 0x0>;
 524                                 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
 525                                 clock-names = "core", "iface";
 526                                 status = "disabled";
 527                         };
 528
 529                         i2c@1a280000 {
 530                                 compatible = "qcom,i2c-qup-v1.1.1";
 531                                 reg = <0x1a280000 0x1000>;
 532                                 interrupts = <0 155 0>;
 533
 534                                 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
 535                                 clock-names = "core", "iface";
 536                                 status = "disabled";
 537
 538                                 #address-cells = <1>;
 539                                 #size-cells = <0>;
 540                         };
 541
 542                         spi@1a280000 {
 543                                 compatible = "qcom,spi-qup-v1.1.1";
 544                                 reg = <0x1a280000 0x1000>;
 545                                 interrupts = <0 155 0>;
 546
 547                                 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
 548                                 clock-names = "core", "iface";
 549                                 status = "disabled";
 550
 551                                 #address-cells = <1>;
 552                                 #size-cells = <0>;
 553                         };
 554                 };
 555
 556                 gsbi6: gsbi@16500000 {
 557                         compatible = "qcom,gsbi-v1.0.0";
 558                         cell-index = <6>;
 559                         reg = <0x16500000 0x100>;
 560                         clocks = <&gcc GSBI6_H_CLK>;
 561                         clock-names = "iface";
 562                         #address-cells = <1>;
 563                         #size-cells = <1>;
 564                         ranges;
 565                         status = "disabled";
 566
 567                         syscon-tcsr = <&tcsr>;
 568
 569                         uart6: serial@16540000 {
 570                                 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
 571                                 reg = <0x16540000 0x1000>,
 572                                       <0x16500000 0x1000>;
 573                                 interrupts = <0 156 0x0>;
 574                                 clocks = <&gcc GSBI6_UART_CLK>, <&gcc GSBI6_H_CLK>;
 575                                 clock-names = "core", "iface";
 576                                 status = "disabled";
 577                         };
 578
 579                         i2c@16580000 {
 580                                 compatible = "qcom,i2c-qup-v1.1.1";
 581                                 reg = <0x16580000 0x1000>;
 582                                 interrupts = <0 157 0>;
 583
 584                                 clocks = <&gcc GSBI6_QUP_CLK>, <&gcc GSBI6_H_CLK>;
 585                                 clock-names = "core", "iface";
 586                                 status = "disabled";
 587
 588                                 #address-cells = <1>;
 589                                 #size-cells = <0>;
 590                         };
 591
 592                         spi@16580000 {
 593                                 compatible = "qcom,spi-qup-v1.1.1";
 594                                 reg = <0x16580000 0x1000>;
 595                                 interrupts = <0 157 0>;
 596
 597                                 clocks = <&gcc GSBI6_QUP_CLK>, <&gcc GSBI6_H_CLK>;
 598                                 clock-names = "core", "iface";
 599                                 status = "disabled";
 600
 601                                 #address-cells = <1>;
 602                                 #size-cells = <0>;
 603                         };
 604                 };
 605
 606                 gsbi7: gsbi@16600000 {
 607                         compatible = "qcom,gsbi-v1.0.0";
 608                         cell-index = <7>;
 609                         reg = <0x16600000 0x100>;
 610                         clocks = <&gcc GSBI7_H_CLK>;
 611                         clock-names = "iface";
 612                         #address-cells = <1>;
 613                         #size-cells = <1>;
 614                         ranges;
 615                         status = "disabled";
 616
 617                         syscon-tcsr = <&tcsr>;
 618
 619                         uart7: serial@16640000 {
 620                                 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
 621                                 reg = <0x16640000 0x1000>,
 622                                       <0x16600000 0x1000>;
 623                                 interrupts = <0 158 0x0>;
 624                                 clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
 625                                 clock-names = "core", "iface";
 626                                 status = "disabled";
 627                         };
 628
 629                         i2c@16680000 {
 630                                 compatible = "qcom,i2c-qup-v1.1.1";
 631                                 reg = <0x16680000 0x1000>;
 632                                 interrupts = <0 159 0>;
 633
 634                                 clocks = <&gcc GSBI7_QUP_CLK>, <&gcc GSBI7_H_CLK>;
 635                                 clock-names = "core", "iface";
 636                                 status = "disabled";
 637
 638                                 #address-cells = <1>;
 639                                 #size-cells = <0>;
 640                         };
 641
 642                 };
 643
 644                 sata_phy: sata-phy@1b400000 {
 645                         compatible = "qcom,ipq806x-sata-phy";
 646                         reg = <0x1b400000 0x200>;
 647
 648                         clocks = <&gcc SATA_PHY_CFG_CLK>;
 649                         clock-names = "cfg";
 650
 651                         #phy-cells = <0>;
 652                         status = "disabled";
 653                 };
 654
 655                 sata@29000000 {
 656                         compatible = "qcom,ipq806x-ahci", "generic-ahci";
 657                         reg = <0x29000000 0x180>;
 658
 659                         interrupts = <0 209 0x0>;
 660
 661                         clocks = <&gcc SFAB_SATA_S_H_CLK>,
 662                                  <&gcc SATA_H_CLK>,
 663                                  <&gcc SATA_A_CLK>,
 664                                  <&gcc SATA_RXOOB_CLK>,
 665                                  <&gcc SATA_PMALIVE_CLK>;
 666                         clock-names = "slave_face", "iface", "core",
 667                                         "rxoob", "pmalive";
 668
 669                         assigned-clocks = <&gcc SATA_RXOOB_CLK>, <&gcc SATA_PMALIVE_CLK>;
 670                         assigned-clock-rates = <100000000>, <100000000>;
 671
 672                         phys = <&sata_phy>;
 673                         phy-names = "sata-phy";
 674                         status = "disabled";
 675                 };
 676
 677                 qcom,ssbi@500000 {
 678                         compatible = "qcom,ssbi";
 679                         reg = <0x00500000 0x1000>;
 680                         qcom,controller-type = "pmic-arbiter";
 681                 };
 682
 683                 gcc: clock-controller@900000 {
 684                         compatible = "qcom,gcc-ipq8064";
 685                         reg = <0x00900000 0x4000>;
 686                         #clock-cells = <1>;
 687                         #reset-cells = <1>;
 688                         #power-domain-cells = <1>;
 689                 };
 690
 691                 lcc: clock-controller@28000000 {
 692                         compatible = "qcom,lcc-ipq8064";
 693                         reg = <0x28000000 0x1000>;
 694                         #clock-cells = <1>;
 695                         #reset-cells = <1>;
 696                 };
 697
 698                 tcsr: syscon@1a400000 {
 699                         compatible = "qcom,tcsr-ipq8064", "syscon";
 700                         reg = <0x1a400000 0x100>;
 701                 };
 702
 703                 tsens: tsens-ipq806x {
 704                         compatible = "qcom,ipq806x-tsens";
 705                         reg = <0x900000 0x3678>, <0x700000 0x420>;
 706                         reg-names = "tsens_physical", "tsens_eeprom_physical";
 707                         interrupts = <0 178 0>;
 708                         qcom,sensors = <11>;
 709                         qcom,tsens_factor = <1000>;
 710                         qcom,slope = <1176 1176 1154 1176 1111 1132 1132 1199 1132 1199 1132>;
 711                 };
 712
 713                 qcom,msm-thermal {
 714                         compatible = "qcom,msm-thermal";
 715                         qcom,sensor-id = <0>;
 716                         qcom,poll-ms = <250>;
 717                         qcom,limit-temp = <105>;
 718                         qcom,temp-hysteresis = <10>;
 719                         qcom,freq-step = <2>;
 720                         qcom,core-limit-temp = <115>;
 721                         qcom,core-temp-hysteresis = <10>;
 722                         qcom,core-control-mask = <0xe>;
 723                 };
 724
 725                 sfpb_mutex_block: syscon@1200600 {
 726                         compatible = "syscon";
 727                         reg = <0x01200600 0x100>;
 728                 };
 729
 730                 hs_phy_1: phy@100f8800 {
 731                         compatible = "qcom,dwc3-hs-usb-phy";
 732                         reg = <0x100f8800 0x30>;
 733                         clocks = <&gcc USB30_1_UTMI_CLK>;
 734                         clock-names = "ref";
 735                         #phy-cells = <0>;
 736
 737                         status = "disabled";
 738                 };
 739
 740                 ss_phy_1: phy@100f8830 {
 741                         compatible = "qcom,dwc3-ss-usb-phy";
 742                         reg = <0x100f8830 0x30>;
 743                         clocks = <&gcc USB30_1_MASTER_CLK>;
 744                         clock-names = "ref";
 745                         #phy-cells = <0>;
 746
 747                         status = "disabled";
 748                 };
 749
 750                 hs_phy_0: phy@110f8800 {
 751                         compatible = "qcom,dwc3-hs-usb-phy";
 752                         reg = <0x110f8800 0x30>;
 753                         clocks = <&gcc USB30_0_UTMI_CLK>;
 754                         clock-names = "ref";
 755                         #phy-cells = <0>;
 756
 757                         status = "disabled";
 758                 };
 759
 760                 ss_phy_0: phy@110f8830 {
 761                         compatible = "qcom,dwc3-ss-usb-phy";
 762                         reg = <0x110f8830 0x30>;
 763                         clocks = <&gcc USB30_0_MASTER_CLK>;
 764                         clock-names = "ref";
 765                         #phy-cells = <0>;
 766
 767                         status = "disabled";
 768                 };
 769
 770                 usb3_0: usb30@0 {
 771                         compatible = "qcom,dwc3";
 772                         #address-cells = <1>;
 773                         #size-cells = <1>;
 774                         clocks = <&gcc USB30_0_MASTER_CLK>;
 775                         clock-names = "core";
 776
 777                         ranges;
 778
 779                         status = "disabled";
 780                         resets = <&gcc USB30_0_MASTER_RESET>;
 781                         reset-names = "usb30_mstr_rst";
 782
 783                         dwc3@11000000 {
 784                                 compatible = "snps,dwc3";
 785                                 reg = <0x11000000 0xcd00>;
 786                                 interrupts = <0 110 0x4>;
 787                                 phys = <&hs_phy_0>, <&ss_phy_0>;
 788                                 phy-names = "usb2-phy", "usb3-phy";
 789                                 tx-fifo-resize;
 790                                 dr_mode = "host";
 791                         };
 792                 };
 793
 794                 usb3_1: usb30@1 {
 795                         compatible = "qcom,dwc3";
 796                         #address-cells = <1>;
 797                         #size-cells = <1>;
 798                         clocks = <&gcc USB30_1_MASTER_CLK>;
 799                         clock-names = "core";
 800
 801                         ranges;
 802
 803                         status = "disabled";
 804
 805                         dwc3@10000000 {
 806                                 compatible = "snps,dwc3";
 807                                 reg = <0x10000000 0xcd00>;
 808                                 interrupts = <0 205 0x4>;
 809                                 phys = <&hs_phy_1>, <&ss_phy_1>;
 810                                 phy-names = "usb2-phy", "usb3-phy";
 811                                 tx-fifo-resize;
 812                                 dr_mode = "host";
 813                         };
 814                 };
 815
 816                 pcie0: pci@1b500000 {
 817                         compatible = "qcom,pcie-v0";
 818                         reg = <0x1b500000 0x1000
 819                                0x1b502000 0x80
 820                                0x1b600000 0x100
 821                                0x0ff00000 0x100000>;
 822                         reg-names = "dbi", "elbi", "parf", "config";
 823                         device_type = "pci";
 824                         linux,pci-domain = <0>;
 825                         bus-range = <0x00 0xff>;
 826                         num-lanes = <1>;
 827                         #address-cells = <3>;
 828                         #size-cells = <2>;
 829
 830                         ranges = <0x81000000 0 0x0fe00000 0x0fe00000 0 0x00100000   /* downstream I/O */
 831                                   0x82000000 0 0x08000000 0x08000000 0 0x07e00000>; /* non-prefetchable memory */
 832
 833                         interrupts = <GIC_SPI 35 IRQ_TYPE_NONE>;
 834                         interrupt-names = "msi";
 835                         #interrupt-cells = <1>;
 836                         interrupt-map-mask = <0 0 0 0x7>;
 837                         interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
 838                                         <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
 839                                         <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
 840                                         <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
 841
 842                         clocks = <&gcc PCIE_A_CLK>,
 843                                  <&gcc PCIE_H_CLK>,
 844                                  <&gcc PCIE_PHY_CLK>,
 845                                  <&gcc PCIE_AUX_CLK>,
 846                                  <&gcc PCIE_ALT_REF_CLK>;
 847                         clock-names = "core", "iface", "phy", "aux", "ref";
 848
 849                         assigned-clocks = <&gcc PCIE_ALT_REF_CLK>;
 850                         assigned-clock-rates = <100000000>;
 851
 852                         resets = <&gcc PCIE_ACLK_RESET>,
 853                                  <&gcc PCIE_HCLK_RESET>,
 854                                  <&gcc PCIE_POR_RESET>,
 855                                  <&gcc PCIE_PCI_RESET>,
 856                                  <&gcc PCIE_PHY_RESET>,
 857                                  <&gcc PCIE_EXT_RESET>;
 858                         reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
 859
 860                         pinctrl-0 = <&pcie0_pins>;
 861                         pinctrl-names = "default";
 862
 863                         perst-gpios = <&qcom_pinmux 3 GPIO_ACTIVE_LOW>;
 864
 865                         status = "disabled";
 866                 };
 867
 868                 pcie1: pci@1b700000 {
 869                         compatible = "qcom,pcie-v0";
 870                         reg = <0x1b700000 0x1000
 871                                0x1b702000 0x80
 872                                0x1b800000 0x100
 873                                0x31f00000 0x100000>;
 874                         reg-names = "dbi", "elbi", "parf", "config";
 875                         device_type = "pci";
 876                         linux,pci-domain = <1>;
 877                         bus-range = <0x00 0xff>;
 878                         num-lanes = <1>;
 879                         #address-cells = <3>;
 880                         #size-cells = <2>;
 881
 882                         ranges = <0x81000000 0 0x31e00000 0x31e00000 0 0x00100000   /* downstream I/O */
 883                                   0x82000000 0 0x2e000000 0x2e000000 0 0x03e00000>; /* non-prefetchable memory */
 884
 885                         interrupts = <GIC_SPI 57 IRQ_TYPE_NONE>;
 886                         interrupt-names = "msi";
 887                         #interrupt-cells = <1>;
 888                         interrupt-map-mask = <0 0 0 0x7>;
 889                         interrupt-map = <0 0 0 1 &intc 0 58 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
 890                                         <0 0 0 2 &intc 0 59 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
 891                                         <0 0 0 3 &intc 0 60 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
 892                                         <0 0 0 4 &intc 0 61 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
 893
 894                         clocks = <&gcc PCIE_1_A_CLK>,
 895                                  <&gcc PCIE_1_H_CLK>,
 896                                  <&gcc PCIE_1_PHY_CLK>,
 897                                  <&gcc PCIE_1_AUX_CLK>,
 898                                  <&gcc PCIE_1_ALT_REF_CLK>;
 899                         clock-names = "core", "iface", "phy", "aux", "ref";
 900
 901                         assigned-clocks = <&gcc PCIE_1_ALT_REF_CLK>;
 902                         assigned-clock-rates = <100000000>;
 903
 904                         resets = <&gcc PCIE_1_ACLK_RESET>,
 905                                  <&gcc PCIE_1_HCLK_RESET>,
 906                                  <&gcc PCIE_1_POR_RESET>,
 907                                  <&gcc PCIE_1_PCI_RESET>,
 908                                  <&gcc PCIE_1_PHY_RESET>,
 909                                  <&gcc PCIE_1_EXT_RESET>;
 910                         reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
 911
 912                         pinctrl-0 = <&pcie1_pins>;
 913                         pinctrl-names = "default";
 914
 915                         perst-gpios = <&qcom_pinmux 48 GPIO_ACTIVE_LOW>;
 916
 917                         status = "disabled";
 918                 };
 919
 920                 pcie2: pci@1b900000 {
 921                         compatible = "qcom,pcie-v0";
 922                         reg = <0x1b900000 0x1000
 923                                0x1b902000 0x80
 924                                0x1ba00000 0x100
 925                                0x35f00000 0x100000>;
 926                         reg-names = "dbi", "elbi", "parf", "config";
 927                         device_type = "pci";
 928                         linux,pci-domain = <2>;
 929                         bus-range = <0x00 0xff>;
 930                         num-lanes = <1>;
 931                         #address-cells = <3>;
 932                         #size-cells = <2>;
 933
 934                         ranges = <0x81000000 0 0x35e00000 0x35e00000 0 0x00100000   /* downstream I/O */
 935                                   0x82000000 0 0x32000000 0x32000000 0 0x03e00000>; /* non-prefetchable memory */
 936
 937                         interrupts = <GIC_SPI 71 IRQ_TYPE_NONE>;
 938                         interrupt-names = "msi";
 939                         #interrupt-cells = <1>;
 940                         interrupt-map-mask = <0 0 0 0x7>;
 941                         interrupt-map = <0 0 0 1 &intc 0 72 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
 942                                         <0 0 0 2 &intc 0 73 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
 943                                         <0 0 0 3 &intc 0 74 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
 944                                         <0 0 0 4 &intc 0 75 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
 945
 946                         clocks = <&gcc PCIE_2_A_CLK>,
 947                                  <&gcc PCIE_2_H_CLK>,
 948                                  <&gcc PCIE_2_PHY_CLK>,
 949                                  <&gcc PCIE_2_AUX_CLK>,
 950                                  <&gcc PCIE_2_ALT_REF_CLK>;
 951                         clock-names = "core", "iface", "phy", "aux", "ref";
 952
 953                         assigned-clocks = <&gcc PCIE_2_ALT_REF_CLK>;
 954                         assigned-clock-rates = <100000000>;
 955
 956                         resets = <&gcc PCIE_2_ACLK_RESET>,
 957                                  <&gcc PCIE_2_HCLK_RESET>,
 958                                  <&gcc PCIE_2_POR_RESET>,
 959                                  <&gcc PCIE_2_PCI_RESET>,
 960                                  <&gcc PCIE_2_PHY_RESET>,
 961                                  <&gcc PCIE_2_EXT_RESET>;
 962                         reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
 963
 964                         pinctrl-0 = <&pcie2_pins>;
 965                         pinctrl-names = "default";
 966
 967                         perst-gpios = <&qcom_pinmux 63 GPIO_ACTIVE_LOW>;
 968
 969                         status = "disabled";
 970                 };
 971
 972                 adm_dma: dma@18300000 {
 973                         compatible = "qcom,adm";
 974                         reg = <0x18300000 0x100000>;
 975                         interrupts = <GIC_SPI 170 IRQ_TYPE_NONE>;
 976                         #dma-cells = <1>;
 977
 978                         clocks = <&gcc ADM0_CLK>, <&gcc ADM0_PBUS_CLK>;
 979                         clock-names = "core", "iface";
 980
 981                         resets = <&gcc ADM0_RESET>,
 982                                  <&gcc ADM0_PBUS_RESET>,
 983                                  <&gcc ADM0_C0_RESET>,
 984                                  <&gcc ADM0_C1_RESET>,
 985                                  <&gcc ADM0_C2_RESET>;
 986                         reset-names = "clk", "pbus", "c0", "c1", "c2";
 987                         qcom,ee = <0>;
 988
 989                         status = "disabled";
 990                 };
 991
 992                 nand@1ac00000 {
 993                         compatible = "qcom,ebi2-nandc";
 994                         reg = <0x1ac00000 0x800>;
 995
 996                         clocks = <&gcc EBI2_CLK>,
 997                                  <&gcc EBI2_AON_CLK>;
 998                         clock-names = "core", "aon";
 999
1000                         dmas = <&adm_dma 3>;
1001                         dma-names = "rxtx";
1002                         qcom,cmd-crci = <15>;
1003                         qcom,data-crci = <3>;
1004
1005                         status = "disabled";
1006                 };
1007
1008                 nss_common: syscon@03000000 {
1009                         compatible = "syscon";
1010                         reg = <0x03000000 0x0000FFFF>;
1011                 };
1012
1013                 qsgmii_csr: syscon@1bb00000 {
1014                         compatible = "syscon";
1015                         reg = <0x1bb00000 0x000001FF>;
1016                 };
1017
1018                 gmac0: ethernet@37000000 {
1019                         device_type = "network";
1020                         compatible = "qcom,ipq806x-gmac", "snps,dwmac";
1021                         reg = <0x37000000 0x200000>;
1022                         interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
1023                         interrupt-names = "macirq";
1024
1025                         qcom,nss-common = <&nss_common>;
1026                         qcom,qsgmii-csr = <&qsgmii_csr>;
1027
1028                         clocks = <&gcc GMAC_CORE1_CLK>;
1029                         clock-names = "stmmaceth";
1030
1031                         resets = <&gcc GMAC_CORE1_RESET>;
1032                         reset-names = "stmmaceth";
1033
1034                         status = "disabled";
1035                 };
1036
1037                 gmac1: ethernet@37200000 {
1038                         device_type = "network";
1039                         compatible = "qcom,ipq806x-gmac", "snps,dwmac";
1040                         reg = <0x37200000 0x200000>;
1041                         interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
1042                         interrupt-names = "macirq";
1043
1044                         qcom,nss-common = <&nss_common>;
1045                         qcom,qsgmii-csr = <&qsgmii_csr>;
1046
1047                         clocks = <&gcc GMAC_CORE2_CLK>;
1048                         clock-names = "stmmaceth";
1049
1050                         resets = <&gcc GMAC_CORE2_RESET>;
1051                         reset-names = "stmmaceth";
1052
1053                         status = "disabled";
1054                 };
1055
1056                 gmac2: ethernet@37400000 {
1057                         device_type = "network";
1058                         compatible = "qcom,ipq806x-gmac", "snps,dwmac";
1059                         reg = <0x37400000 0x200000>;
1060                         interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
1061                         interrupt-names = "macirq";
1062
1063                         qcom,nss-common = <&nss_common>;
1064                         qcom,qsgmii-csr = <&qsgmii_csr>;
1065
1066                         clocks = <&gcc GMAC_CORE3_CLK>;
1067                         clock-names = "stmmaceth";
1068
1069                         resets = <&gcc GMAC_CORE3_RESET>;
1070                         reset-names = "stmmaceth";
1071
1072                         status = "disabled";
1073                 };
1074
1075                 gmac3: ethernet@37600000 {
1076                         device_type = "network";
1077                         compatible = "qcom,ipq806x-gmac", "snps,dwmac";
1078                         reg = <0x37600000 0x200000>;
1079                         interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
1080                         interrupt-names = "macirq";
1081
1082                         qcom,nss-common = <&nss_common>;
1083                         qcom,qsgmii-csr = <&qsgmii_csr>;
1084
1085                         clocks = <&gcc GMAC_CORE4_CLK>;
1086                         clock-names = "stmmaceth";
1087
1088                         resets = <&gcc GMAC_CORE4_RESET>;
1089                         reset-names = "stmmaceth";
1090
1091                         status = "disabled";
1092                 };
1093
1094                 /* Temporary fixed regulator */
1095                 vsdcc_fixed: vsdcc-regulator {
1096                         compatible = "regulator-fixed";
1097                         regulator-name = "SDCC Power";
1098                         regulator-min-microvolt = <3300000>;
1099                         regulator-max-microvolt = <3300000>;
1100                         regulator-always-on;
1101                 };
1102
1103                 sdcc1bam:dma@12402000 {
1104                         compatible = "qcom,bam-v1.3.0";
1105                         reg = <0x12402000 0x8000>;
1106                         interrupts = <0 98 0>;
1107                         clocks = <&gcc SDC1_H_CLK>;
1108                         clock-names = "bam_clk";
1109                         #dma-cells = <1>;
1110                         qcom,ee = <0>;
1111                 };
1112
1113                 sdcc3bam:dma@12182000 {
1114                         compatible = "qcom,bam-v1.3.0";
1115                         reg = <0x12182000 0x8000>;
1116                         interrupts = <0 96 0>;
1117                         clocks = <&gcc SDC3_H_CLK>;
1118                         clock-names = "bam_clk";
1119                         #dma-cells = <1>;
1120                         qcom,ee = <0>;
1121                 };
1122
1123                 amba {
1124                         compatible = "arm,amba-bus";
1125                         #address-cells = <1>;
1126                         #size-cells = <1>;
1127                         ranges;
1128                         sdcc1: sdcc@12400000 {
1129                                 status          = "disabled";
1130                                 compatible      = "arm,pl18x", "arm,primecell";
1131                                 arm,primecell-periphid = <0x00051180>;
1132                                 reg             = <0x12400000 0x2000>;
1133                                 interrupts      = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
1134                                 interrupt-names = "cmd_irq";
1135                                 clocks          = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
1136                                 clock-names     = "mclk", "apb_pclk";
1137                                 bus-width       = <8>;
1138                                 max-frequency   = <48000000>;
1139                                 non-removable;
1140                                 cap-sd-highspeed;
1141                                 cap-mmc-highspeed;
1142                                 vmmc-supply = <&vsdcc_fixed>;
1143                                 #dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
1144                                 #dma-names = "tx", "rx";
1145                         };
1146
1147                         sdcc3: sdcc@12180000 {
1148                                 compatible      = "arm,pl18x", "arm,primecell";
1149                                 arm,primecell-periphid = <0x00051180>;
1150                                 status          = "disabled";
1151                                 reg             = <0x12180000 0x2000>;
1152                                 interrupts      = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
1153                                 interrupt-names = "cmd_irq";
1154                                 clocks          = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
1155                                 clock-names     = "mclk", "apb_pclk";
1156                                 bus-width       = <8>;
1157                                 cap-sd-highspeed;
1158                                 cap-mmc-highspeed;
1159                                 max-frequency   = <192000000>;
1160                                 #mmc-ddr-1_8v;
1161                                 sd-uhs-sdr50;
1162                                 vmmc-supply = <&vsdcc_fixed>;
1163                                 #dmas = <&sdcc3bam 2>, <&sdcc3bam 1>;
1164                                 #dma-names = "tx", "rx";
1165                         };
1166                 };
1167         };
1168
1169         sfpb_mutex: sfpb-mutex {
1170                 compatible = "qcom,sfpb-mutex";
1171                 syscon = <&sfpb_mutex_block 4 4>;
1172
1173                 #hwlock-cells = <1>;
1174         };
1175
1176         smem {
1177                 compatible = "qcom,smem";
1178                 memory-region = <&smem>;
1179                 hwlocks = <&sfpb_mutex 3>;
1180         };
1181 };