target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8065.dtsi

   1 /dts-v1/;
   2
   3 #include "skeleton.dtsi"
   4 #include <dt-bindings/clock/qcom,gcc-ipq806x.h>
   5 #include <dt-bindings/clock/qcom,lcc-ipq806x.h>
   6 #include <dt-bindings/mfd/qcom-rpm.h>
   7 #include <dt-bindings/soc/qcom,gsbi.h>
   8 #include <dt-bindings/reset/qcom,gcc-ipq806x.h>
   9 #include <dt-bindings/interrupt-controller/arm-gic.h>
  10 #include <dt-bindings/interrupt-controller/irq.h>
  11 #include <dt-bindings/gpio/gpio.h>
  12
  13 / {
  14         model = "Qualcomm IPQ8065";
  15         compatible = "qcom,ipq8065", "qcom,ipq8064";
  16         interrupt-parent = <&intc>;
  17
  18         cpus {
  19                 #address-cells = <1>;
  20                 #size-cells = <0>;
  21
  22                 cpu0: cpu@0 {
  23                         compatible = "qcom,krait";
  24                         enable-method = "qcom,kpss-acc-v1";
  25                         device_type = "cpu";
  26                         reg = <0>;
  27                         next-level-cache = <&L2>;
  28                         qcom,acc = <&acc0>;
  29                         qcom,saw = <&saw0>;
  30                         clocks = <&kraitcc 0>, <&kraitcc 4>;
  31                         clock-names = "cpu", "l2";
  32                         qcom,imem = <&imem>;
  33                         clock-latency = <100000>;
  34                         cpu-supply = <&smb208_s2a>;
  35                         voltage-tolerance = <5>;
  36                         cooling-min-state = <0>;
  37                         cooling-max-state = <10>;
  38                         #cooling-cells = <2>;
  39                         cpu-idle-states = <&CPU_SPC>;
  40                 };
  41
  42                 cpu1: cpu@1 {
  43                         compatible = "qcom,krait";
  44                         enable-method = "qcom,kpss-acc-v1";
  45                         device_type = "cpu";
  46                         reg = <1>;
  47                         next-level-cache = <&L2>;
  48                         qcom,acc = <&acc1>;
  49                         qcom,saw = <&saw1>;
  50                         clocks = <&kraitcc 1>, <&kraitcc 4>;
  51                         clock-names = "cpu", "l2";
  52                         qcom,imem = <&imem>;
  53                         clock-latency = <100000>;
  54                         cpu-supply = <&smb208_s2b>;
  55                         cooling-min-state = <0>;
  56                         cooling-max-state = <10>;
  57                         #cooling-cells = <2>;
  58                         cpu-idle-states = <&CPU_SPC>;
  59                 };
  60
  61                 L2: l2-cache {
  62                         compatible = "cache";
  63                         cache-level = <2>;
  64                         qcom,saw = <&saw_l2>;
  65                 };
  66
  67                 qcom,l2 {
  68                         qcom,l2-rates = <384000000 1000000000 1200000000>;
  69                 };
  70
  71                 idle-states {
  72                         CPU_SPC: spc {
  73                                 compatible = "qcom,idle-state-spc",
  74                                                 "arm,idle-state";
  75                                 entry-latency-us = <400>;
  76                                 exit-latency-us = <900>;
  77                                 min-residency-us = <3000>;
  78                         };
  79                 };
  80         };
  81
  82         cpu-pmu {
  83                 compatible = "qcom,krait-pmu";
  84                 interrupts = <1 10 0x304>;
  85         };
  86
  87         reserved-memory {
  88                 #address-cells = <1>;
  89                 #size-cells = <1>;
  90                 ranges;
  91
  92                 nss@40000000 {
  93                         reg = <0x40000000 0x1000000>;
  94                         no-map;
  95                 };
  96
  97                 smem: smem@41000000 {
  98                         reg = <0x41000000 0x200000>;
  99                         no-map;
 100                 };
 101         };
 102
 103         clocks {
 104
 105                 cxo_board {
 106                         compatible = "fixed-clock";
 107                         #clock-cells = <0>;
 108                         clock-frequency = <25000000>;
 109                 };
 110
 111                 pxo_board {
 112                         compatible = "fixed-clock";
 113                         #clock-cells = <0>;
 114                         clock-frequency = <25000000>;
 115                 };
 116
 117                 sleep_clk: sleep_clk {
 118                         compatible = "fixed-clock";
 119                         clock-frequency = <32768>;
 120                         #clock-cells = <0>;
 121                 };
 122         };
 123
 124         kraitcc: clock-controller {
 125                 compatible = "qcom,krait-cc-v1";
 126                 #clock-cells = <1>;
 127         };
 128
 129         qcom,pvs {
 130                 qcom,pvs-format-a;
 131                 qcom,speed0-pvs0-bin-v0 =
 132                         < 1725000000 1262500 >,
 133                         < 1400000000 1175000 >,
 134                         < 1000000000 1100000 >,
 135                          < 800000000 1050000 >,
 136                          < 600000000 1000000 >,
 137                          < 384000000 975000 >;
 138                 qcom,speed0-pvs1-bin-v0 =
 139                         < 1725000000 1262500 >,
 140                         < 1400000000 1175000 >,
 141                         < 1000000000 1100000 >,
 142                          < 800000000 1050000 >,
 143                          < 600000000 1000000 >,
 144                          < 384000000 950000 >;
 145                 qcom,speed0-pvs2-bin-v0 =
 146                         < 1725000000 1200000 >,
 147                         < 1400000000 1125000 >,
 148                         < 1000000000 1050000 >,
 149                          < 800000000 1000000 >,
 150                          < 600000000 950000 >,
 151                          < 384000000 925000 >;
 152                 qcom,speed0-pvs3-bin-v0 =
 153                         < 1725000000 1175000 >,
 154                         < 1400000000 1100000 >,
 155                         < 1000000000 1025000 >,
 156                          < 800000000 975000 >,
 157                          < 600000000 925000 >,
 158                          < 384000000 900000 >;
 159                 qcom,speed0-pvs4-bin-v0 =
 160                         < 1725000000 1150000 >,
 161                         < 1400000000 1075000 >,
 162                         < 1000000000 1000000 >,
 163                          < 800000000 950000 >,
 164                          < 600000000 900000 >,
 165                          < 384000000 875000 >;
 166                 qcom,speed0-pvs5-bin-v0 =
 167                         < 1725000000 1100000 >,
 168                         < 1400000000 1025000 >,
 169                         < 1000000000 950000 >,
 170                          < 800000000 900000 >,
 171                          < 600000000 850000 >,
 172                          < 384000000 825000 >;
 173                 qcom,speed0-pvs6-bin-v0 =
 174                         < 1725000000 1050000 >,
 175                         < 1400000000 975000 >,
 176                         < 1000000000 900000 >,
 177                          < 800000000 850000 >,
 178                          < 600000000 800000 >,
 179                          < 384000000 775000 >;
 180         };
 181
 182         soc: soc {
 183                 #address-cells = <1>;
 184                 #size-cells = <1>;
 185                 ranges;
 186                 compatible = "simple-bus";
 187
 188                 lpass@28100000 {
 189                         compatible = "qcom,lpass-cpu";
 190                         status = "disabled";
 191                         clocks = <&lcc AHBIX_CLK>,
 192                                         <&lcc MI2S_OSR_CLK>,
 193                                         <&lcc MI2S_BIT_CLK>;
 194                         clock-names = "ahbix-clk",
 195                                         "mi2s-osr-clk",
 196                                         "mi2s-bit-clk";
 197                         interrupts = <0 85 1>;
 198                         interrupt-names = "lpass-irq-lpaif";
 199                         reg = <0x28100000 0x10000>;
 200                         reg-names = "lpass-lpaif";
 201                 };
 202
 203                 imem: memory@700000 {
 204                         compatible = "qcom,qfprom", "syscon";
 205                         reg = <0x00700000 0x1000>;
 206                         #address-cells = <1>;
 207                         #size-cells = <1>;
 208                         stride = <1>;
 209                         ranges = <0x0 0x00700000 0x1000>;
 210                 };
 211
 212                 rpm@108000 {
 213                         compatible = "qcom,rpm-ipq8064";
 214                         reg = <0x108000 0x1000>;
 215                         qcom,ipc = <&l2cc 0x8 2>;
 216
 217                         interrupts = <0 19 0>,
 218                                      <0 21 0>,
 219                                      <0 22 0>;
 220                         interrupt-names = "ack",
 221                                           "err",
 222                                           "wakeup";
 223
 224                         #address-cells = <1>;
 225                         #size-cells = <0>;
 226
 227                         clocks = <&gcc RPM_MSG_RAM_H_CLK>;
 228                         clock-names = "ram";
 229
 230                         rpmcc: clock-controller {
 231                                 compatible      = "qcom,rpmcc-ipq806x", "qcom,rpmcc";
 232                                 #clock-cells = <1>;
 233                         };
 234
 235                         smb208_regulators {
 236                                 compatible = "qcom,rpm-smb208-regulators";
 237
 238                                 smb208_s1a: s1a {
 239                                         regulator-min-microvolt = <1050000>;
 240                                         regulator-max-microvolt = <1150000>;
 241                                         qcom,switch-mode-frequency = <1200000>;
 242                                 };
 243
 244                                 smb208_s1b: s1b {
 245                                         regulator-min-microvolt = <1050000>;
 246                                         regulator-max-microvolt = <1150000>;
 247                                         qcom,switch-mode-frequency = <1200000>;
 248                                 };
 249
 250                                 smb208_s2a: s2a {
 251                                         regulator-min-microvolt = < 800000>;
 252                                         regulator-max-microvolt = <1275000>;
 253                                         qcom,switch-mode-frequency = <1200000>;
 254                                 };
 255
 256                                 smb208_s2b: s2b {
 257                                         regulator-min-microvolt = < 800000>;
 258                                         regulator-max-microvolt = <1275000>;
 259                                         qcom,switch-mode-frequency = <1200000>;
 260                                 };
 261                         };
 262                 };
 263
 264                 rng@1a500000 {
 265                         compatible = "qcom,prng";
 266                         reg = <0x1a500000 0x200>;
 267                         clocks = <&gcc PRNG_CLK>;
 268                         clock-names = "core";
 269                 };
 270
 271                 qcom,msm-imem@2A03F000 {
 272                         compatible = "qcom,msm-imem";
 273                         reg = <0x2A03F000 0x1000>; /* Address and size of IMEM */
 274                         ranges = <0x0 0x2A03F000 0x1000>;
 275                         #address-cells = <1>;
 276                         #size-cells = <1>;
 277
 278                         download_mode@0 {
 279                                 compatible = "qcom,msm-imem-download_mode";
 280                                 reg = <0x0 8>;
 281                         };
 282
 283                         restart_reason@65c {
 284                                 compatible = "qcom,msm-imem-restart_reason";
 285                                 reg = <0x65c 4>;
 286                         };
 287
 288                         l2_dump_offset@14 {
 289                                 compatible = "qcom,msm-imem-l2_dump_offset";
 290                                 reg = <0x14 8>;
 291                         };
 292                 };
 293
 294                 qcom_pinmux: pinmux@800000 {
 295                         compatible = "qcom,ipq8064-pinctrl";
 296                         reg = <0x800000 0x4000>;
 297
 298                         gpio-controller;
 299                         #gpio-cells = <2>;
 300                         interrupt-controller;
 301                         #interrupt-cells = <2>;
 302                         interrupts = <0 16 0x4>;
 303
 304                         pcie0_pins: pcie0_pinmux {
 305                                 mux {
 306                                         pins = "gpio3";
 307                                         function = "pcie1_rst";
 308                                         drive-strength = <2>;
 309                                         bias-disable;
 310                                 };
 311                         };
 312
 313                         pcie1_pins: pcie1_pinmux {
 314                                 mux {
 315                                         pins = "gpio48";
 316                                         function = "pcie2_rst";
 317                                         drive-strength = <2>;
 318                                         bias-disable;
 319                                 };
 320                         };
 321
 322                         pcie2_pins: pcie2_pinmux {
 323                                 mux {
 324                                         pins = "gpio63";
 325                                         function = "pcie3_rst";
 326                                         drive-strength = <2>;
 327                                         bias-disable;
 328                                         output-low;
 329                                 };
 330                         };
 331                 };
 332
 333                 intc: interrupt-controller@2000000 {
 334                         compatible = "qcom,msm-qgic2";
 335                         interrupt-controller;
 336                         #interrupt-cells = <3>;
 337                         reg = <0x02000000 0x1000>,
 338                               <0x02002000 0x1000>;
 339                 };
 340
 341                 timer@200a000 {
 342                         compatible = "qcom,kpss-timer", "qcom,msm-timer";
 343                         interrupts = <1 1 0x301>,
 344                                      <1 2 0x301>,
 345                                      <1 3 0x301>,
 346                                      <1 4 0x301>,
 347                                      <1 5 0x301>;
 348                         reg = <0x0200a000 0x100>;
 349                         clock-frequency = <25000000>,
 350                                           <32768>;
 351                         clocks = <&sleep_clk>;
 352                         clock-names = "sleep";
 353                         cpu-offset = <0x80000>;
 354                 };
 355
 356                 acc0: clock-controller@2088000 {
 357                         compatible = "qcom,kpss-acc-v1";
 358                         reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
 359                         clock-output-names = "acpu0_aux";
 360                 };
 361
 362                 acc1: clock-controller@2098000 {
 363                         compatible = "qcom,kpss-acc-v1";
 364                         reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
 365                         clock-output-names = "acpu1_aux";
 366                 };
 367
 368                 l2cc: clock-controller@2011000 {
 369                         compatible = "qcom,kpss-gcc", "syscon";
 370                         reg = <0x2011000 0x1000>;
 371                         clock-output-names = "acpu_l2_aux";
 372                 };
 373
 374                 saw0: regulator@2089000 {
 375                         compatible = "qcom,saw2", "syscon";
 376                         reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
 377                         regulator;
 378                 };
 379
 380                 saw1: regulator@2099000 {
 381                         compatible = "qcom,saw2", "syscon";
 382                         reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
 383                         regulator;
 384                 };
 385
 386                 saw_l2: regulator@02012000 {
 387                         compatible = "qcom,saw2", "syscon";
 388                         reg = <0x02012000 0x1000>;
 389                         regulator;
 390                 };
 391
 392                 sic_non_secure: sic-non-secure@12100000 {
 393                         compatible = "syscon";
 394                         reg = <0x12100000 0x10000>;
 395                 };
 396
 397                 gsbi1: gsbi@12440000 {
 398                         compatible = "qcom,gsbi-v1.0.0";
 399                         cell-index = <1>;
 400                         reg = <0x12440000 0x100>;
 401                         clocks = <&gcc GSBI1_H_CLK>;
 402                         clock-names = "iface";
 403                         #address-cells = <1>;
 404                         #size-cells = <1>;
 405                         ranges;
 406                         status = "disabled";
 407
 408                         syscon-tcsr = <&tcsr>;
 409
 410                         uart1: serial@12450000 {
 411                                 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
 412                                 reg = <0x12450000 0x1000>,
 413                                       <0x12440000 0x1000>;
 414                                 interrupts = <0 193 0x0>;
 415                                 clocks = <&gcc GSBI1_UART_CLK>, <&gcc GSBI1_H_CLK>;
 416                                 clock-names = "core", "iface";
 417                                 status = "disabled";
 418                         };
 419
 420                         i2c@12460000 {
 421                                 compatible = "qcom,i2c-qup-v1.1.1";
 422                                 reg = <0x12460000 0x1000>;
 423                                 interrupts = <0 194 0>;
 424
 425                                 clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
 426                                 clock-names = "core", "iface";
 427                                 status = "disabled";
 428
 429                                 #address-cells = <1>;
 430                                 #size-cells = <0>;
 431                         };
 432
 433                 };
 434
 435                 gsbi2: gsbi@12480000 {
 436                         compatible = "qcom,gsbi-v1.0.0";
 437                         cell-index = <2>;
 438                         reg = <0x12480000 0x100>;
 439                         clocks = <&gcc GSBI2_H_CLK>;
 440                         clock-names = "iface";
 441                         #address-cells = <1>;
 442                         #size-cells = <1>;
 443                         ranges;
 444                         status = "disabled";
 445
 446                         syscon-tcsr = <&tcsr>;
 447
 448                         uart2: serial@12490000 {
 449                                 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
 450                                 reg = <0x12490000 0x1000>,
 451                                       <0x12480000 0x1000>;
 452                                 interrupts = <0 195 0x0>;
 453                                 clocks = <&gcc GSBI2_UART_CLK>, <&gcc GSBI2_H_CLK>;
 454                                 clock-names = "core", "iface";
 455                                 status = "disabled";
 456                         };
 457
 458                         i2c@124a0000 {
 459                                 compatible = "qcom,i2c-qup-v1.1.1";
 460                                 reg = <0x124a0000 0x1000>;
 461                                 interrupts = <0 196 0>;
 462
 463                                 clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
 464                                 clock-names = "core", "iface";
 465                                 status = "disabled";
 466
 467                                 #address-cells = <1>;
 468                                 #size-cells = <0>;
 469                         };
 470
 471                 };
 472
 473                 gsbi4: gsbi@16300000 {
 474                         compatible = "qcom,gsbi-v1.0.0";
 475                         cell-index = <4>;
 476                         reg = <0x16300000 0x100>;
 477                         clocks = <&gcc GSBI4_H_CLK>;
 478                         clock-names = "iface";
 479                         #address-cells = <1>;
 480                         #size-cells = <1>;
 481                         ranges;
 482                         status = "disabled";
 483
 484                         syscon-tcsr = <&tcsr>;
 485
 486                         uart4: serial@16340000 {
 487                                 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
 488                                 reg = <0x16340000 0x1000>,
 489                                       <0x16300000 0x1000>;
 490                                 interrupts = <0 152 0x0>;
 491                                 clocks = <&gcc GSBI4_UART_CLK>, <&gcc GSBI4_H_CLK>;
 492                                 clock-names = "core", "iface";
 493                                 status = "disabled";
 494                         };
 495
 496                         i2c@16380000 {
 497                                 compatible = "qcom,i2c-qup-v1.1.1";
 498                                 reg = <0x16380000 0x1000>;
 499                                 interrupts = <0 153 0>;
 500
 501                                 clocks = <&gcc GSBI4_QUP_CLK>, <&gcc GSBI4_H_CLK>;
 502                                 clock-names = "core", "iface";
 503                                 status = "disabled";
 504
 505                                 #address-cells = <1>;
 506                                 #size-cells = <0>;
 507                         };
 508                 };
 509
 510                 gsbi5: gsbi@1a200000 {
 511                         compatible = "qcom,gsbi-v1.0.0";
 512                         cell-index = <5>;
 513                         reg = <0x1a200000 0x100>;
 514                         clocks = <&gcc GSBI5_H_CLK>;
 515                         clock-names = "iface";
 516                         #address-cells = <1>;
 517                         #size-cells = <1>;
 518                         ranges;
 519                         status = "disabled";
 520
 521                         syscon-tcsr = <&tcsr>;
 522
 523                         uart5: serial@1a240000 {
 524                                 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
 525                                 reg = <0x1a240000 0x1000>,
 526                                       <0x1a200000 0x1000>;
 527                                 interrupts = <0 154 0x0>;
 528                                 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
 529                                 clock-names = "core", "iface";
 530                                 status = "disabled";
 531                         };
 532
 533                         i2c@1a280000 {
 534                                 compatible = "qcom,i2c-qup-v1.1.1";
 535                                 reg = <0x1a280000 0x1000>;
 536                                 interrupts = <0 155 0>;
 537
 538                                 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
 539                                 clock-names = "core", "iface";
 540                                 status = "disabled";
 541
 542                                 #address-cells = <1>;
 543                                 #size-cells = <0>;
 544                         };
 545
 546                         spi@1a280000 {
 547                                 compatible = "qcom,spi-qup-v1.1.1";
 548                                 reg = <0x1a280000 0x1000>;
 549                                 interrupts = <0 155 0>;
 550
 551                                 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
 552                                 clock-names = "core", "iface";
 553                                 status = "disabled";
 554
 555                                 #address-cells = <1>;
 556                                 #size-cells = <0>;
 557                         };
 558                 };
 559
 560                 gsbi6: gsbi@16500000 {
 561                         compatible = "qcom,gsbi-v1.0.0";
 562                         cell-index = <6>;
 563                         reg = <0x16500000 0x100>;
 564                         clocks = <&gcc GSBI6_H_CLK>;
 565                         clock-names = "iface";
 566                         #address-cells = <1>;
 567                         #size-cells = <1>;
 568                         ranges;
 569                         status = "disabled";
 570
 571                         syscon-tcsr = <&tcsr>;
 572
 573                         uart6: serial@16540000 {
 574                                 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
 575                                 reg = <0x16540000 0x1000>,
 576                                       <0x16500000 0x1000>;
 577                                 interrupts = <0 156 0x0>;
 578                                 clocks = <&gcc GSBI6_UART_CLK>, <&gcc GSBI6_H_CLK>;
 579                                 clock-names = "core", "iface";
 580                                 status = "disabled";
 581                         };
 582
 583                         i2c@16580000 {
 584                                 compatible = "qcom,i2c-qup-v1.1.1";
 585                                 reg = <0x16580000 0x1000>;
 586                                 interrupts = <0 157 0>;
 587
 588                                 clocks = <&gcc GSBI6_QUP_CLK>, <&gcc GSBI6_H_CLK>;
 589                                 clock-names = "core", "iface";
 590                                 status = "disabled";
 591
 592                                 #address-cells = <1>;
 593                                 #size-cells = <0>;
 594                         };
 595
 596                         spi@16580000 {
 597                                 compatible = "qcom,spi-qup-v1.1.1";
 598                                 reg = <0x16580000 0x1000>;
 599                                 interrupts = <0 157 0>;
 600
 601                                 clocks = <&gcc GSBI6_QUP_CLK>, <&gcc GSBI6_H_CLK>;
 602                                 clock-names = "core", "iface";
 603                                 status = "disabled";
 604
 605                                 #address-cells = <1>;
 606                                 #size-cells = <0>;
 607                         };
 608                 };
 609
 610                 gsbi7: gsbi@16600000 {
 611                         compatible = "qcom,gsbi-v1.0.0";
 612                         cell-index = <7>;
 613                         reg = <0x16600000 0x100>;
 614                         clocks = <&gcc GSBI7_H_CLK>;
 615                         clock-names = "iface";
 616                         #address-cells = <1>;
 617                         #size-cells = <1>;
 618                         ranges;
 619                         status = "disabled";
 620
 621                         syscon-tcsr = <&tcsr>;
 622
 623                         uart7: serial@16640000 {
 624                                 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
 625                                 reg = <0x16640000 0x1000>,
 626                                       <0x16600000 0x1000>;
 627                                 interrupts = <0 158 0x0>;
 628                                 clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
 629                                 clock-names = "core", "iface";
 630                                 status = "disabled";
 631                         };
 632
 633                         i2c@16680000 {
 634                                 compatible = "qcom,i2c-qup-v1.1.1";
 635                                 reg = <0x16680000 0x1000>;
 636                                 interrupts = <0 159 0>;
 637
 638                                 clocks = <&gcc GSBI7_QUP_CLK>, <&gcc GSBI7_H_CLK>;
 639                                 clock-names = "core", "iface";
 640                                 status = "disabled";
 641
 642                                 #address-cells = <1>;
 643                                 #size-cells = <0>;
 644                         };
 645
 646                 };
 647
 648                 sata_phy: sata-phy@1b400000 {
 649                         compatible = "qcom,ipq806x-sata-phy";
 650                         reg = <0x1b400000 0x200>;
 651
 652                         clocks = <&gcc SATA_PHY_CFG_CLK>;
 653                         clock-names = "cfg";
 654
 655                         #phy-cells = <0>;
 656                         status = "disabled";
 657                 };
 658
 659                 sata@29000000 {
 660                         compatible = "qcom,ipq806x-ahci", "generic-ahci";
 661                         reg = <0x29000000 0x180>;
 662
 663                         interrupts = <0 209 0x0>;
 664
 665                         clocks = <&gcc SFAB_SATA_S_H_CLK>,
 666                                  <&gcc SATA_H_CLK>,
 667                                  <&gcc SATA_A_CLK>,
 668                                  <&gcc SATA_RXOOB_CLK>,
 669                                  <&gcc SATA_PMALIVE_CLK>;
 670                         clock-names = "slave_face", "iface", "core",
 671                                         "rxoob", "pmalive";
 672
 673                         assigned-clocks = <&gcc SATA_RXOOB_CLK>, <&gcc SATA_PMALIVE_CLK>;
 674                         assigned-clock-rates = <100000000>, <100000000>;
 675
 676                         phys = <&sata_phy>;
 677                         phy-names = "sata-phy";
 678                         status = "disabled";
 679                 };
 680
 681                 qcom,ssbi@500000 {
 682                         compatible = "qcom,ssbi";
 683                         reg = <0x00500000 0x1000>;
 684                         qcom,controller-type = "pmic-arbiter";
 685                 };
 686
 687                 gcc: clock-controller@900000 {
 688                         compatible = "qcom,gcc-ipq8064";
 689                         reg = <0x00900000 0x4000>;
 690                         #clock-cells = <1>;
 691                         #reset-cells = <1>;
 692                         #power-domain-cells = <1>;
 693                 };
 694
 695                 lcc: clock-controller@28000000 {
 696                         compatible = "qcom,lcc-ipq8064";
 697                         reg = <0x28000000 0x1000>;
 698                         #clock-cells = <1>;
 699                         #reset-cells = <1>;
 700                 };
 701
 702                 tcsr: syscon@1a400000 {
 703                         compatible = "qcom,tcsr-ipq8064", "syscon";
 704                         reg = <0x1a400000 0x100>;
 705                 };
 706
 707                 tsens: tsens-ipq806x {
 708                         compatible = "qcom,ipq806x-tsens";
 709                         reg = <0x900000 0x3678>, <0x700000 0x420>;
 710                         reg-names = "tsens_physical", "tsens_eeprom_physical";
 711                         interrupts = <0 178 0>;
 712                         qcom,sensors = <11>;
 713                         qcom,tsens_factor = <1000>;
 714                         qcom,slope = <1176 1176 1154 1176 1111 1132 1132 1199 1132 1199 1132>;
 715                 };
 716
 717                 qcom,msm-thermal {
 718                         compatible = "qcom,msm-thermal";
 719                         qcom,sensor-id = <0>;
 720                         qcom,poll-ms = <250>;
 721                         qcom,limit-temp = <105>;
 722                         qcom,temp-hysteresis = <10>;
 723                         qcom,freq-step = <2>;
 724                         qcom,core-limit-temp = <115>;
 725                         qcom,core-temp-hysteresis = <10>;
 726                         qcom,core-control-mask = <0xe>;
 727                 };
 728
 729                 sfpb_mutex_block: syscon@1200600 {
 730                         compatible = "syscon";
 731                         reg = <0x01200600 0x100>;
 732                 };
 733
 734                 hs_phy_1: phy@100f8800 {
 735                         compatible = "qcom,dwc3-hs-usb-phy";
 736                         reg = <0x100f8800 0x30>;
 737                         clocks = <&gcc USB30_1_UTMI_CLK>;
 738                         clock-names = "ref";
 739                         #phy-cells = <0>;
 740
 741                         status = "disabled";
 742                 };
 743
 744                 ss_phy_1: phy@100f8830 {
 745                         compatible = "qcom,dwc3-ss-usb-phy";
 746                         reg = <0x100f8830 0x30>;
 747                         clocks = <&gcc USB30_1_MASTER_CLK>;
 748                         clock-names = "ref";
 749                         #phy-cells = <0>;
 750
 751                         status = "disabled";
 752                 };
 753
 754                 hs_phy_0: phy@110f8800 {
 755                         compatible = "qcom,dwc3-hs-usb-phy";
 756                         reg = <0x110f8800 0x30>;
 757                         clocks = <&gcc USB30_0_UTMI_CLK>;
 758                         clock-names = "ref";
 759                         #phy-cells = <0>;
 760
 761                         status = "disabled";
 762                 };
 763
 764                 ss_phy_0: phy@110f8830 {
 765                         compatible = "qcom,dwc3-ss-usb-phy";
 766                         reg = <0x110f8830 0x30>;
 767                         clocks = <&gcc USB30_0_MASTER_CLK>;
 768                         clock-names = "ref";
 769                         #phy-cells = <0>;
 770
 771                         status = "disabled";
 772                 };
 773
 774                 usb3_0: usb30@0 {
 775                         compatible = "qcom,dwc3";
 776                         #address-cells = <1>;
 777                         #size-cells = <1>;
 778                         clocks = <&gcc USB30_0_MASTER_CLK>;
 779                         clock-names = "core";
 780
 781                         ranges;
 782
 783                         status = "disabled";
 784                         resets = <&gcc USB30_0_MASTER_RESET>;
 785                         reset-names = "usb30_mstr_rst";
 786
 787                         dwc3@11000000 {
 788                                 compatible = "snps,dwc3";
 789                                 reg = <0x11000000 0xcd00>;
 790                                 interrupts = <0 110 0x4>;
 791                                 phys = <&hs_phy_0>, <&ss_phy_0>;
 792                                 phy-names = "usb2-phy", "usb3-phy";
 793                                 tx-fifo-resize;
 794                                 dr_mode = "host";
 795                         };
 796                 };
 797
 798                 usb3_1: usb30@1 {
 799                         compatible = "qcom,dwc3";
 800                         #address-cells = <1>;
 801                         #size-cells = <1>;
 802                         clocks = <&gcc USB30_1_MASTER_CLK>;
 803                         clock-names = "core";
 804
 805                         ranges;
 806
 807                         status = "disabled";
 808
 809                         dwc3@10000000 {
 810                                 compatible = "snps,dwc3";
 811                                 reg = <0x10000000 0xcd00>;
 812                                 interrupts = <0 205 0x4>;
 813                                 phys = <&hs_phy_1>, <&ss_phy_1>;
 814                                 phy-names = "usb2-phy", "usb3-phy";
 815                                 tx-fifo-resize;
 816                                 dr_mode = "host";
 817                         };
 818                 };
 819
 820                 pcie0: pci@1b500000 {
 821                         compatible = "qcom,pcie-v0";
 822                         reg = <0x1b500000 0x1000
 823                                0x1b502000 0x80
 824                                0x1b600000 0x100
 825                                0x0ff00000 0x100000>;
 826                         reg-names = "dbi", "elbi", "parf", "config";
 827                         device_type = "pci";
 828                         linux,pci-domain = <0>;
 829                         bus-range = <0x00 0xff>;
 830                         num-lanes = <1>;
 831                         #address-cells = <3>;
 832                         #size-cells = <2>;
 833
 834                         ranges = <0x81000000 0 0x0fe00000 0x0fe00000 0 0x00100000   /* downstream I/O */
 835                                   0x82000000 0 0x08000000 0x08000000 0 0x07e00000>; /* non-prefetchable memory */
 836
 837                         interrupts = <GIC_SPI 35 IRQ_TYPE_NONE>;
 838                         interrupt-names = "msi";
 839                         #interrupt-cells = <1>;
 840                         interrupt-map-mask = <0 0 0 0x7>;
 841                         interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
 842                                         <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
 843                                         <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
 844                                         <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
 845
 846                         clocks = <&gcc PCIE_A_CLK>,
 847                                  <&gcc PCIE_H_CLK>,
 848                                  <&gcc PCIE_PHY_CLK>,
 849                                  <&gcc PCIE_AUX_CLK>,
 850                                  <&gcc PCIE_ALT_REF_CLK>;
 851                         clock-names = "core", "iface", "phy", "aux", "ref";
 852
 853                         assigned-clocks = <&gcc PCIE_ALT_REF_CLK>;
 854                         assigned-clock-rates = <100000000>;
 855
 856                         resets = <&gcc PCIE_ACLK_RESET>,
 857                                  <&gcc PCIE_HCLK_RESET>,
 858                                  <&gcc PCIE_POR_RESET>,
 859                                  <&gcc PCIE_PCI_RESET>,
 860                                  <&gcc PCIE_PHY_RESET>,
 861                                  <&gcc PCIE_EXT_RESET>;
 862                         reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
 863
 864                         pinctrl-0 = <&pcie0_pins>;
 865                         pinctrl-names = "default";
 866
 867                         perst-gpios = <&qcom_pinmux 3 GPIO_ACTIVE_LOW>;
 868
 869                         status = "disabled";
 870                 };
 871
 872                 pcie1: pci@1b700000 {
 873                         compatible = "qcom,pcie-v0";
 874                         reg = <0x1b700000 0x1000
 875                                0x1b702000 0x80
 876                                0x1b800000 0x100
 877                                0x31f00000 0x100000>;
 878                         reg-names = "dbi", "elbi", "parf", "config";
 879                         device_type = "pci";
 880                         linux,pci-domain = <1>;
 881                         bus-range = <0x00 0xff>;
 882                         num-lanes = <1>;
 883                         #address-cells = <3>;
 884                         #size-cells = <2>;
 885
 886                         ranges = <0x81000000 0 0x31e00000 0x31e00000 0 0x00100000   /* downstream I/O */
 887                                   0x82000000 0 0x2e000000 0x2e000000 0 0x03e00000>; /* non-prefetchable memory */
 888
 889                         interrupts = <GIC_SPI 57 IRQ_TYPE_NONE>;
 890                         interrupt-names = "msi";
 891                         #interrupt-cells = <1>;
 892                         interrupt-map-mask = <0 0 0 0x7>;
 893                         interrupt-map = <0 0 0 1 &intc 0 58 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
 894                                         <0 0 0 2 &intc 0 59 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
 895                                         <0 0 0 3 &intc 0 60 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
 896                                         <0 0 0 4 &intc 0 61 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
 897
 898                         clocks = <&gcc PCIE_1_A_CLK>,
 899                                  <&gcc PCIE_1_H_CLK>,
 900                                  <&gcc PCIE_1_PHY_CLK>,
 901                                  <&gcc PCIE_1_AUX_CLK>,
 902                                  <&gcc PCIE_1_ALT_REF_CLK>;
 903                         clock-names = "core", "iface", "phy", "aux", "ref";
 904
 905                         assigned-clocks = <&gcc PCIE_1_ALT_REF_CLK>;
 906                         assigned-clock-rates = <100000000>;
 907
 908                         resets = <&gcc PCIE_1_ACLK_RESET>,
 909                                  <&gcc PCIE_1_HCLK_RESET>,
 910                                  <&gcc PCIE_1_POR_RESET>,
 911                                  <&gcc PCIE_1_PCI_RESET>,
 912                                  <&gcc PCIE_1_PHY_RESET>,
 913                                  <&gcc PCIE_1_EXT_RESET>;
 914                         reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
 915
 916                         pinctrl-0 = <&pcie1_pins>;
 917                         pinctrl-names = "default";
 918
 919                         perst-gpios = <&qcom_pinmux 48 GPIO_ACTIVE_LOW>;
 920
 921                         status = "disabled";
 922                 };
 923
 924                 pcie2: pci@1b900000 {
 925                         compatible = "qcom,pcie-v0";
 926                         reg = <0x1b900000 0x1000
 927                                0x1b902000 0x80
 928                                0x1ba00000 0x100
 929                                0x35f00000 0x100000>;
 930                         reg-names = "dbi", "elbi", "parf", "config";
 931                         device_type = "pci";
 932                         linux,pci-domain = <2>;
 933                         bus-range = <0x00 0xff>;
 934                         num-lanes = <1>;
 935                         #address-cells = <3>;
 936                         #size-cells = <2>;
 937
 938                         ranges = <0x81000000 0 0x35e00000 0x35e00000 0 0x00100000   /* downstream I/O */
 939                                   0x82000000 0 0x32000000 0x32000000 0 0x03e00000>; /* non-prefetchable memory */
 940
 941                         interrupts = <GIC_SPI 71 IRQ_TYPE_NONE>;
 942                         interrupt-names = "msi";
 943                         #interrupt-cells = <1>;
 944                         interrupt-map-mask = <0 0 0 0x7>;
 945                         interrupt-map = <0 0 0 1 &intc 0 72 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
 946                                         <0 0 0 2 &intc 0 73 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
 947                                         <0 0 0 3 &intc 0 74 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
 948                                         <0 0 0 4 &intc 0 75 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
 949
 950                         clocks = <&gcc PCIE_2_A_CLK>,
 951                                  <&gcc PCIE_2_H_CLK>,
 952                                  <&gcc PCIE_2_PHY_CLK>,
 953                                  <&gcc PCIE_2_AUX_CLK>,
 954                                  <&gcc PCIE_2_ALT_REF_CLK>;
 955                         clock-names = "core", "iface", "phy", "aux", "ref";
 956
 957                         assigned-clocks = <&gcc PCIE_2_ALT_REF_CLK>;
 958                         assigned-clock-rates = <100000000>;
 959
 960                         resets = <&gcc PCIE_2_ACLK_RESET>,
 961                                  <&gcc PCIE_2_HCLK_RESET>,
 962                                  <&gcc PCIE_2_POR_RESET>,
 963                                  <&gcc PCIE_2_PCI_RESET>,
 964                                  <&gcc PCIE_2_PHY_RESET>,
 965                                  <&gcc PCIE_2_EXT_RESET>;
 966                         reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
 967
 968                         pinctrl-0 = <&pcie2_pins>;
 969                         pinctrl-names = "default";
 970
 971                         perst-gpios = <&qcom_pinmux 63 GPIO_ACTIVE_LOW>;
 972
 973                         status = "disabled";
 974                 };
 975
 976                 adm_dma: dma@18300000 {
 977                         compatible = "qcom,adm";
 978                         reg = <0x18300000 0x100000>;
 979                         interrupts = <GIC_SPI 170 IRQ_TYPE_NONE>;
 980                         #dma-cells = <1>;
 981
 982                         clocks = <&gcc ADM0_CLK>, <&gcc ADM0_PBUS_CLK>;
 983                         clock-names = "core", "iface";
 984
 985                         resets = <&gcc ADM0_RESET>,
 986                                  <&gcc ADM0_PBUS_RESET>,
 987                                  <&gcc ADM0_C0_RESET>,
 988                                  <&gcc ADM0_C1_RESET>,
 989                                  <&gcc ADM0_C2_RESET>;
 990                         reset-names = "clk", "pbus", "c0", "c1", "c2";
 991                         qcom,ee = <0>;
 992
 993                         status = "disabled";
 994                 };
 995
 996                 nand@1ac00000 {
 997                         compatible = "qcom,ebi2-nandc";
 998                         reg = <0x1ac00000 0x800>;
 999
1000                         clocks = <&gcc EBI2_CLK>,
1001                                  <&gcc EBI2_AON_CLK>;
1002                         clock-names = "core", "aon";
1003
1004                         dmas = <&adm_dma 3>;
1005                         dma-names = "rxtx";
1006                         qcom,cmd-crci = <15>;
1007                         qcom,data-crci = <3>;
1008
1009                         status = "disabled";
1010                 };
1011
1012                 nss_common: syscon@03000000 {
1013                         compatible = "syscon";
1014                         reg = <0x03000000 0x0000FFFF>;
1015                 };
1016
1017                 qsgmii_csr: syscon@1bb00000 {
1018                         compatible = "syscon";
1019                         reg = <0x1bb00000 0x000001FF>;
1020                 };
1021
1022                 gmac0: ethernet@37000000 {
1023                         device_type = "network";
1024                         compatible = "qcom,ipq806x-gmac", "snps,dwmac";
1025                         reg = <0x37000000 0x200000>;
1026                         interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
1027                         interrupt-names = "macirq";
1028
1029                         qcom,nss-common = <&nss_common>;
1030                         qcom,qsgmii-csr = <&qsgmii_csr>;
1031
1032                         clocks = <&gcc GMAC_CORE1_CLK>;
1033                         clock-names = "stmmaceth";
1034
1035                         resets = <&gcc GMAC_CORE1_RESET>;
1036                         reset-names = "stmmaceth";
1037
1038                         status = "disabled";
1039                 };
1040
1041                 gmac1: ethernet@37200000 {
1042                         device_type = "network";
1043                         compatible = "qcom,ipq806x-gmac", "snps,dwmac";
1044                         reg = <0x37200000 0x200000>;
1045                         interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
1046                         interrupt-names = "macirq";
1047
1048                         qcom,nss-common = <&nss_common>;
1049                         qcom,qsgmii-csr = <&qsgmii_csr>;
1050
1051                         clocks = <&gcc GMAC_CORE2_CLK>;
1052                         clock-names = "stmmaceth";
1053
1054                         resets = <&gcc GMAC_CORE2_RESET>;
1055                         reset-names = "stmmaceth";
1056
1057                         status = "disabled";
1058                 };
1059
1060                 gmac2: ethernet@37400000 {
1061                         device_type = "network";
1062                         compatible = "qcom,ipq806x-gmac", "snps,dwmac";
1063                         reg = <0x37400000 0x200000>;
1064                         interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
1065                         interrupt-names = "macirq";
1066
1067                         qcom,nss-common = <&nss_common>;
1068                         qcom,qsgmii-csr = <&qsgmii_csr>;
1069
1070                         clocks = <&gcc GMAC_CORE3_CLK>;
1071                         clock-names = "stmmaceth";
1072
1073                         resets = <&gcc GMAC_CORE3_RESET>;
1074                         reset-names = "stmmaceth";
1075
1076                         status = "disabled";
1077                 };
1078
1079                 gmac3: ethernet@37600000 {
1080                         device_type = "network";
1081                         compatible = "qcom,ipq806x-gmac", "snps,dwmac";
1082                         reg = <0x37600000 0x200000>;
1083                         interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
1084                         interrupt-names = "macirq";
1085
1086                         qcom,nss-common = <&nss_common>;
1087                         qcom,qsgmii-csr = <&qsgmii_csr>;
1088
1089                         clocks = <&gcc GMAC_CORE4_CLK>;
1090                         clock-names = "stmmaceth";
1091
1092                         resets = <&gcc GMAC_CORE4_RESET>;
1093                         reset-names = "stmmaceth";
1094
1095                         status = "disabled";
1096                 };
1097
1098                 /* Temporary fixed regulator */
1099                 vsdcc_fixed: vsdcc-regulator {
1100                         compatible = "regulator-fixed";
1101                         regulator-name = "SDCC Power";
1102                         regulator-min-microvolt = <3300000>;
1103                         regulator-max-microvolt = <3300000>;
1104                         regulator-always-on;
1105                 };
1106
1107                 sdcc1bam:dma@12402000 {
1108                         compatible = "qcom,bam-v1.3.0";
1109                         reg = <0x12402000 0x8000>;
1110                         interrupts = <0 98 0>;
1111                         clocks = <&gcc SDC1_H_CLK>;
1112                         clock-names = "bam_clk";
1113                         #dma-cells = <1>;
1114                         qcom,ee = <0>;
1115                 };
1116
1117                 sdcc3bam:dma@12182000 {
1118                         compatible = "qcom,bam-v1.3.0";
1119                         reg = <0x12182000 0x8000>;
1120                         interrupts = <0 96 0>;
1121                         clocks = <&gcc SDC3_H_CLK>;
1122                         clock-names = "bam_clk";
1123                         #dma-cells = <1>;
1124                         qcom,ee = <0>;
1125                 };
1126
1127                 amba {
1128                         compatible = "arm,amba-bus";
1129                         #address-cells = <1>;
1130                         #size-cells = <1>;
1131                         ranges;
1132                         sdcc1: sdcc@12400000 {
1133                                 status          = "disabled";
1134                                 compatible      = "arm,pl18x", "arm,primecell";
1135                                 arm,primecell-periphid = <0x00051180>;
1136                                 reg             = <0x12400000 0x2000>;
1137                                 interrupts      = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
1138                                 interrupt-names = "cmd_irq";
1139                                 clocks          = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
1140                                 clock-names     = "mclk", "apb_pclk";
1141                                 bus-width       = <8>;
1142                                 max-frequency   = <48000000>;
1143                                 non-removable;
1144                                 cap-sd-highspeed;
1145                                 cap-mmc-highspeed;
1146                                 vmmc-supply = <&vsdcc_fixed>;
1147                                 #dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
1148                                 #dma-names = "tx", "rx";
1149                         };
1150
1151                         sdcc3: sdcc@12180000 {
1152                                 compatible      = "arm,pl18x", "arm,primecell";
1153                                 arm,primecell-periphid = <0x00051180>;
1154                                 status          = "disabled";
1155                                 reg             = <0x12180000 0x2000>;
1156                                 interrupts      = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
1157                                 interrupt-names = "cmd_irq";
1158                                 clocks          = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
1159                                 clock-names     = "mclk", "apb_pclk";
1160                                 bus-width       = <8>;
1161                                 cap-sd-highspeed;
1162                                 cap-mmc-highspeed;
1163                                 max-frequency   = <192000000>;
1164                                 #mmc-ddr-1_8v;
1165                                 sd-uhs-sdr50;
1166                                 vmmc-supply = <&vsdcc_fixed>;
1167                                 #dmas = <&sdcc3bam 2>, <&sdcc3bam 1>;
1168                                 #dma-names = "tx", "rx";
1169                         };
1170                 };
1171         };
1172
1173         sfpb_mutex: sfpb-mutex {
1174                 compatible = "qcom,sfpb-mutex";
1175                 syscon = <&sfpb_mutex_block 4 4>;
1176
1177                 #hwlock-cells = <1>;
1178         };
1179
1180         smem {
1181                 compatible = "qcom,smem";
1182                 memory-region = <&smem>;
1183                 hwlocks = <&sfpb_mutex 3>;
1184         };
1185 };