target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8065.dtsi

   1 /dts-v1/;
   2
   3 #include "skeleton.dtsi"
   4 #include <dt-bindings/clock/qcom,gcc-ipq806x.h>
   5 #include <dt-bindings/clock/qcom,lcc-ipq806x.h>
   6 #include <dt-bindings/mfd/qcom-rpm.h>
   7 #include <dt-bindings/soc/qcom,gsbi.h>
   8 #include <dt-bindings/reset/qcom,gcc-ipq806x.h>
   9 #include <dt-bindings/interrupt-controller/arm-gic.h>
  10 #include <dt-bindings/gpio/gpio.h>
  11
  12 / {
  13         model = "Qualcomm IPQ8065";
  14         compatible = "qcom,ipq8065";
  15         interrupt-parent = <&intc>;
  16
  17         cpus {
  18                 #address-cells = <1>;
  19                 #size-cells = <0>;
  20
  21                 cpu@0 {
  22                         compatible = "qcom,krait";
  23                         enable-method = "qcom,kpss-acc-v1";
  24                         device_type = "cpu";
  25                         reg = <0>;
  26                         next-level-cache = <&L2>;
  27                         qcom,acc = <&acc0>;
  28                         qcom,saw = <&saw0>;
  29                         clocks = <&kraitcc 0>;
  30                         clock-names = "cpu";
  31                         qcom,imem = <&imem>;
  32                         clock-latency = <100000>;
  33                         core-supply = <&smb208_s2a>;
  34                         voltage-tolerance = <5>;
  35                         cooling-min-state = <0>;
  36                         cooling-max-state = <10>;
  37                         #cooling-cells = <2>;
  38
  39                         operating-points-0-0 = <
  40                                 /* kHz      uV */
  41                                 1725000 1262500
  42                                 1400000 1175000
  43                                 1000000 1100000
  44                                  800000 1050000
  45                                  600000 1000000
  46                                  384000 975000
  47                         >;
  48                         operating-points-0-1 = <
  49                                 /* kHz      uV */
  50                                 1725000 1262500
  51                                 1400000 1175000
  52                                 1000000 1100000
  53                                  800000 1050000
  54                                  600000 1000000
  55                                  384000 950000
  56                         >;
  57                         operating-points-0-2 = <
  58                                 /* kHz      uV */
  59                                 1725000 1200000
  60                                 1400000 1125000
  61                                 1000000 1050000
  62                                  800000 1000000
  63                                  600000 950000
  64                                  384000 925000
  65                         >;
  66                         operating-points-0-3 = <
  67                                 /* kHz      uV */
  68                                 1725000 1175000
  69                                 1400000 1100000
  70                                 1000000 1025000
  71                                  800000 975000
  72                                  600000 925000
  73                                  384000 900000
  74                         >;
  75                         operating-points-0-4 = <
  76                                 /* kHz      uV */
  77                                 1725000 1150000
  78                                 1400000 1075000
  79                                 1000000 1000000
  80                                  800000 950000
  81                                  600000 900000
  82                                  384000 875000
  83                         >;
  84                         operating-points-0-5 = <
  85                                 /* kHz      uV */
  86                                 1725000 1100000
  87                                 1400000 1025000
  88                                 1000000 950000
  89                                  800000 900000
  90                                  600000 850000
  91                                  384000 825000
  92                         >;
  93                         operating-points-0-6 = <
  94                                 /* kHz      uV */
  95                                 1725000 1050000
  96                                 1400000 975000
  97                                 1000000 900000
  98                                  800000 850000
  99                                  600000 800000
 100                                  384000 775000
 101                         >;
 102                 };
 103
 104                 cpu@1 {
 105                         compatible = "qcom,krait";
 106                         enable-method = "qcom,kpss-acc-v1";
 107                         device_type = "cpu";
 108                         reg = <1>;
 109                         next-level-cache = <&L2>;
 110                         qcom,acc = <&acc1>;
 111                         qcom,saw = <&saw1>;
 112                         clocks = <&kraitcc 1>;
 113                         clock-names = "cpu";
 114                         qcom,imem = <&imem>;
 115                         clock-latency = <100000>;
 116                         core-supply = <&smb208_s2b>;
 117                         cooling-min-state = <0>;
 118                         cooling-max-state = <10>;
 119                         #cooling-cells = <2>;
 120
 121                         operating-points-0-0 = <
 122                                 /* kHz      uV */
 123                                 1725000 1262500
 124                                 1400000 1175000
 125                                 1000000 1100000
 126                                  800000 1050000
 127                                  600000 1000000
 128                                  384000 975000
 129                         >;
 130                         operating-points-0-1 = <
 131                                 /* kHz      uV */
 132                                 1725000 1262500
 133                                 1400000 1175000
 134                                 1000000 1100000
 135                                  800000 1050000
 136                                  600000 1000000
 137                                  384000 950000
 138                         >;
 139                         operating-points-0-2 = <
 140                                 /* kHz      uV */
 141                                 1725000 1200000
 142                                 1400000 1125000
 143                                 1000000 1050000
 144                                  800000 1000000
 145                                  600000 950000
 146                                  384000 925000
 147                         >;
 148                         operating-points-0-3 = <
 149                                 /* kHz      uV */
 150                                 1725000 1175000
 151                                 1400000 1100000
 152                                 1000000 1025000
 153                                  800000 975000
 154                                  600000 925000
 155                                  384000 900000
 156                         >;
 157                         operating-points-0-4 = <
 158                                 /* kHz      uV */
 159                                 1725000 1150000
 160                                 1400000 1075000
 161                                 1000000 1000000
 162                                  800000 950000
 163                                  600000 900000
 164                                  384000 875000
 165                         >;
 166                         operating-points-0-5 = <
 167                                 /* kHz      uV */
 168                                 1725000 1100000
 169                                 1400000 1025000
 170                                 1000000 950000
 171                                  800000 900000
 172                                  600000 850000
 173                                  384000 825000
 174                         >;
 175                         operating-points-0-6 = <
 176                                 /* kHz      uV */
 177                                 1725000 1050000
 178                                 1400000 975000
 179                                 1000000 900000
 180                                  800000 850000
 181                                  600000 800000
 182                                  384000 775000
 183                         >;
 184                 };
 185
 186                 L2: l2-cache {
 187                         compatible = "cache";
 188                         cache-level = <2>;
 189                         clocks = <&kraitcc 4>;
 190                         clock-names = "cache";
 191                         cache-points-kHz = <
 192                                 /* kHz    uV    CPU kHz */
 193                                 1200000 1150000 1200000
 194                                 1000000 1100000  600000
 195                                  384000 1100000  384000
 196                         >;
 197                         vdd_dig-supply = <&smb208_s1a>;
 198                 };
 199         };
 200
 201         cpu-pmu {
 202                 compatible = "qcom,krait-pmu";
 203                 interrupts = <1 10 0x304>;
 204         };
 205
 206         reserved-memory {
 207                 #address-cells = <1>;
 208                 #size-cells = <1>;
 209                 ranges;
 210
 211                 nss@40000000 {
 212                         reg = <0x40000000 0x1000000>;
 213                         no-map;
 214                 };
 215
 216                 smem: smem@41000000 {
 217                         reg = <0x41000000 0x200000>;
 218                         no-map;
 219                 };
 220         };
 221
 222         clocks {
 223                 sleep_clk: sleep_clk {
 224                         compatible = "fixed-clock";
 225                         clock-frequency = <32768>;
 226                         #clock-cells = <0>;
 227                 };
 228         };
 229
 230         kraitcc: clock-controller {
 231                 compatible = "qcom,krait-cc-v1";
 232                 #clock-cells = <1>;
 233         };
 234
 235         qcom,pvs {
 236                 qcom,pvs-format-a;
 237                 qcom,speed0-pvs0-bin-v0 =
 238                         < 1725000000 1262500 >,
 239                         < 1400000000 1175000 >,
 240                         < 1000000000 1100000 >,
 241                          < 800000000 1050000 >,
 242                          < 600000000 1000000 >,
 243                          < 384000000 975000 >;
 244                 qcom,speed0-pvs1-bin-v0 =
 245                         < 1725000000 1262500 >,
 246                         < 1400000000 1175000 >,
 247                         < 1000000000 1100000 >,
 248                          < 800000000 1050000 >,
 249                          < 600000000 1000000 >,
 250                          < 384000000 950000 >;
 251                 qcom,speed0-pvs2-bin-v0 =
 252                         < 1725000000 1200000 >,
 253                         < 1400000000 1125000 >,
 254                         < 1000000000 1050000 >,
 255                          < 800000000 1000000 >,
 256                          < 600000000 950000 >,
 257                          < 384000000 925000 >;
 258                 qcom,speed0-pvs3-bin-v0 =
 259                         < 1725000000 1175000 >,
 260                         < 1400000000 1100000 >,
 261                         < 1000000000 1025000 >,
 262                          < 800000000 975000 >,
 263                          < 600000000 925000 >,
 264                          < 384000000 900000 >;
 265                 qcom,speed0-pvs4-bin-v0 =
 266                         < 1725000000 1150000 >,
 267                         < 1400000000 1075000 >,
 268                         < 1000000000 1000000 >,
 269                          < 800000000 950000 >,
 270                          < 600000000 900000 >,
 271                          < 384000000 875000 >;
 272                 qcom,speed0-pvs5-bin-v0 =
 273                         < 1725000000 1100000 >,
 274                         < 1400000000 1025000 >,
 275                         < 1000000000 950000 >,
 276                          < 800000000 900000 >,
 277                          < 600000000 850000 >,
 278                          < 384000000 825000 >;
 279                 qcom,speed0-pvs6-bin-v0 =
 280                         < 1725000000 1050000 >,
 281                         < 1400000000 975000 >,
 282                         < 1000000000 900000 >,
 283                          < 800000000 850000 >,
 284                          < 600000000 800000 >,
 285                          < 384000000 775000 >;
 286         };
 287
 288         soc: soc {
 289                 #address-cells = <1>;
 290                 #size-cells = <1>;
 291                 ranges;
 292                 compatible = "simple-bus";
 293
 294                 lpass@28100000 {
 295                         compatible = "qcom,lpass-cpu";
 296                         status = "disabled";
 297                         clocks = <&lcc AHBIX_CLK>,
 298                                         <&lcc MI2S_OSR_CLK>,
 299                                         <&lcc MI2S_BIT_CLK>;
 300                         clock-names = "ahbix-clk",
 301                                         "mi2s-osr-clk",
 302                                         "mi2s-bit-clk";
 303                         interrupts = <0 85 1>;
 304                         interrupt-names = "lpass-irq-lpaif";
 305                         reg = <0x28100000 0x10000>;
 306                         reg-names = "lpass-lpaif";
 307                 };
 308
 309                 imem: memory@700000 {
 310                         compatible = "qcom,qfprom", "syscon";
 311                         reg = <0x00700000 0x1000>;
 312                         #address-cells = <1>;
 313                         #size-cells = <1>;
 314                         stride = <1>;
 315                         ranges = <0x0 0x00700000 0x1000>;
 316                 };
 317
 318                 rpm@108000 {
 319                         compatible = "qcom,rpm-ipq8064";
 320                         reg = <0x108000 0x1000>;
 321                         qcom,ipc = <&l2cc 0x8 2>;
 322
 323                         interrupts = <0 19 0>,
 324                                      <0 21 0>,
 325                                      <0 22 0>;
 326                         interrupt-names = "ack",
 327                                           "err",
 328                                           "wakeup";
 329
 330                         #address-cells = <1>;
 331                         #size-cells = <0>;
 332
 333                         smb208_regulators {
 334                                 compatible = "qcom,rpm-smb208-regulators";
 335
 336                                 smb208_s1a: s1a {
 337                                         regulator-min-microvolt = <1050000>;
 338                                         regulator-max-microvolt = <1150000>;
 339                                         qcom,switch-mode-frequency = <1200000>;
 340                                 };
 341
 342                                 smb208_s1b: s1b {
 343                                         regulator-min-microvolt = <1050000>;
 344                                         regulator-max-microvolt = <1150000>;
 345                                         qcom,switch-mode-frequency = <1200000>;
 346                                 };
 347
 348                                 smb208_s2a: s2a {
 349                                         regulator-min-microvolt = < 800000>;
 350                                         regulator-max-microvolt = <1275000>;
 351                                         qcom,switch-mode-frequency = <1200000>;
 352                                 };
 353
 354                                 smb208_s2b: s2b {
 355                                         regulator-min-microvolt = < 800000>;
 356                                         regulator-max-microvolt = <1275000>;
 357                                         qcom,switch-mode-frequency = <1200000>;
 358                                 };
 359                         };
 360
 361                         rpm_clocks {
 362                                 #clock-cells = <0>;
 363                                 compatible = "qcom,rpm-clk";
 364                                 qcom,rpm-clk-active-only;
 365
 366                                 cxo_clk: cxo {
 367                                         reg = <QCOM_RPM_CXO_CLK>;
 368                                         qcom,rpm-clk-name = "cxo";
 369                                         qcom,rpm-clk-freq = <25000000>;
 370                                 };
 371
 372                                 pxo_clk: pxo {
 373                                         reg = <QCOM_RPM_PXO_CLK>;
 374                                         qcom,rpm-clk-name = "pxo";
 375                                         qcom,rpm-clk-freq = <25000000>;
 376                                 };
 377
 378                                 ebi1_clk: ebi1 {
 379                                         reg = <QCOM_RPM_EBI1_CLK>;
 380                                         qcom,rpm-clk-name = "ebi1";
 381                                         qcom,rpm-clk-freq = <533000000>;
 382                                 };
 383
 384                                 apps_fabric_clk: apps-fabric {
 385                                         reg = <QCOM_RPM_APPS_FABRIC_CLK>;
 386                                         qcom,rpm-clk-name = "apps-fabric";
 387                                         qcom,rpm-clk-freq = <533000000>;
 388                                 };
 389
 390                                 nss_fabric0_clk: nss-fabric0 {
 391                                         reg = <QCOM_RPM_NSS_FABRIC_0_CLK>;
 392                                         qcom,rpm-clk-name = "nss-fabric0";
 393                                         qcom,rpm-clk-freq = <533000000>;
 394                                 };
 395
 396                                 nss_fabric1_clk: nss-fabric1 {
 397                                         reg = <QCOM_RPM_NSS_FABRIC_1_CLK>;
 398                                         qcom,rpm-clk-name = "nss-fabric1";
 399                                         qcom,rpm-clk-freq = <266000000>;
 400                                 };
 401                         };
 402                 };
 403
 404                 rng@1a500000 {
 405                         compatible = "qcom,prng";
 406                         reg = <0x1a500000 0x200>;
 407                         clocks = <&gcc PRNG_CLK>;
 408                         clock-names = "core";
 409                 };
 410
 411                 qcom,msm-imem@2A03F000 {
 412                         compatible = "qcom,msm-imem";
 413                         reg = <0x2A03F000 0x1000>; /* Address and size of IMEM */
 414                         ranges = <0x0 0x2A03F000 0x1000>;
 415                         #address-cells = <1>;
 416                         #size-cells = <1>;
 417
 418                         download_mode@0 {
 419                                 compatible = "qcom,msm-imem-download_mode";
 420                                 reg = <0x0 8>;
 421                         };
 422
 423                         restart_reason@65c {
 424                                 compatible = "qcom,msm-imem-restart_reason";
 425                                 reg = <0x65c 4>;
 426                         };
 427
 428                         l2_dump_offset@14 {
 429                                 compatible = "qcom,msm-imem-l2_dump_offset";
 430                                 reg = <0x14 8>;
 431                         };
 432                 };
 433
 434                 qcom_pinmux: pinmux@800000 {
 435                         compatible = "qcom,ipq8064-pinctrl";
 436                         reg = <0x800000 0x4000>;
 437
 438                         gpio-controller;
 439                         #gpio-cells = <2>;
 440                         interrupt-controller;
 441                         #interrupt-cells = <2>;
 442                         interrupts = <0 16 0x4>;
 443
 444                         pcie0_pins: pcie0_pinmux {
 445                                 mux {
 446                                         pins = "gpio3";
 447                                         function = "pcie1_rst";
 448                                         drive-strength = <12>;
 449                                         bias-disable;
 450                                 };
 451                         };
 452
 453                         pcie1_pins: pcie1_pinmux {
 454                                 mux {
 455                                         pins = "gpio48";
 456                                         function = "pcie2_rst";
 457                                         drive-strength = <12>;
 458                                         bias-disable;
 459                                 };
 460                         };
 461
 462                         pcie2_pins: pcie2_pinmux {
 463                                 mux {
 464                                         pins = "gpio63";
 465                                         function = "pcie3_rst";
 466                                         drive-strength = <12>;
 467                                         bias-disable;
 468                                 };
 469                         };
 470                 };
 471
 472                 intc: interrupt-controller@2000000 {
 473                         compatible = "qcom,msm-qgic2";
 474                         interrupt-controller;
 475                         #interrupt-cells = <3>;
 476                         reg = <0x02000000 0x1000>,
 477                               <0x02002000 0x1000>;
 478                 };
 479
 480                 timer@200a000 {
 481                         compatible = "qcom,kpss-timer", "qcom,msm-timer";
 482                         interrupts = <1 1 0x301>,
 483                                      <1 2 0x301>,
 484                                      <1 3 0x301>,
 485                                      <1 4 0x301>,
 486                                      <1 5 0x301>;
 487                         reg = <0x0200a000 0x100>;
 488                         clock-frequency = <25000000>,
 489                                           <32768>;
 490                         clocks = <&sleep_clk>;
 491                         clock-names = "sleep";
 492                         cpu-offset = <0x80000>;
 493                 };
 494
 495                 acc0: clock-controller@2088000 {
 496                         compatible = "qcom,kpss-acc-v1";
 497                         reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
 498                         clock-output-names = "acpu0_aux";
 499                 };
 500
 501                 acc1: clock-controller@2098000 {
 502                         compatible = "qcom,kpss-acc-v1";
 503                         reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
 504                         clock-output-names = "acpu1_aux";
 505                 };
 506
 507                 l2cc: clock-controller@2011000 {
 508                         compatible = "qcom,kpss-gcc", "syscon";
 509                         reg = <0x2011000 0x1000>;
 510                         clock-output-names = "acpu_l2_aux";
 511                 };
 512
 513                 saw0: regulator@2089000 {
 514                         compatible = "qcom,saw2";
 515                         reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
 516                         regulator;
 517                 };
 518
 519                 saw1: regulator@2099000 {
 520                         compatible = "qcom,saw2";
 521                         reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
 522                         regulator;
 523                 };
 524
 525                 gsbi1: gsbi@12440000 {
 526                         compatible = "qcom,gsbi-v1.0.0";
 527                         cell-index = <1>;
 528                         reg = <0x12440000 0x100>;
 529                         clocks = <&gcc GSBI1_H_CLK>;
 530                         clock-names = "iface";
 531                         #address-cells = <1>;
 532                         #size-cells = <1>;
 533                         ranges;
 534                         status = "disabled";
 535
 536                         syscon-tcsr = <&tcsr>;
 537
 538                         uart1: serial@12450000 {
 539                                 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
 540                                 reg = <0x12450000 0x1000>,
 541                                       <0x12440000 0x1000>;
 542                                 interrupts = <0 193 0x0>;
 543                                 clocks = <&gcc GSBI1_UART_CLK>, <&gcc GSBI1_H_CLK>;
 544                                 clock-names = "core", "iface";
 545                                 status = "disabled";
 546                         };
 547
 548                         i2c@12460000 {
 549                                 compatible = "qcom,i2c-qup-v1.1.1";
 550                                 reg = <0x12460000 0x1000>;
 551                                 interrupts = <0 194 0>;
 552
 553                                 clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
 554                                 clock-names = "core", "iface";
 555                                 status = "disabled";
 556
 557                                 #address-cells = <1>;
 558                                 #size-cells = <0>;
 559                         };
 560
 561                 };
 562
 563                 gsbi2: gsbi@12480000 {
 564                         compatible = "qcom,gsbi-v1.0.0";
 565                         cell-index = <2>;
 566                         reg = <0x12480000 0x100>;
 567                         clocks = <&gcc GSBI2_H_CLK>;
 568                         clock-names = "iface";
 569                         #address-cells = <1>;
 570                         #size-cells = <1>;
 571                         ranges;
 572                         status = "disabled";
 573
 574                         syscon-tcsr = <&tcsr>;
 575
 576                         uart2: serial@12490000 {
 577                                 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
 578                                 reg = <0x12490000 0x1000>,
 579                                       <0x12480000 0x1000>;
 580                                 interrupts = <0 195 0x0>;
 581                                 clocks = <&gcc GSBI2_UART_CLK>, <&gcc GSBI2_H_CLK>;
 582                                 clock-names = "core", "iface";
 583                                 status = "disabled";
 584                         };
 585
 586                         i2c@124a0000 {
 587                                 compatible = "qcom,i2c-qup-v1.1.1";
 588                                 reg = <0x124a0000 0x1000>;
 589                                 interrupts = <0 196 0>;
 590
 591                                 clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
 592                                 clock-names = "core", "iface";
 593                                 status = "disabled";
 594
 595                                 #address-cells = <1>;
 596                                 #size-cells = <0>;
 597                         };
 598
 599                 };
 600
 601                 gsbi4: gsbi@16300000 {
 602                         compatible = "qcom,gsbi-v1.0.0";
 603                         cell-index = <4>;
 604                         reg = <0x16300000 0x100>;
 605                         clocks = <&gcc GSBI4_H_CLK>;
 606                         clock-names = "iface";
 607                         #address-cells = <1>;
 608                         #size-cells = <1>;
 609                         ranges;
 610                         status = "disabled";
 611
 612                         syscon-tcsr = <&tcsr>;
 613
 614                         uart4: serial@16340000 {
 615                                 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
 616                                 reg = <0x16340000 0x1000>,
 617                                       <0x16300000 0x1000>;
 618                                 interrupts = <0 152 0x0>;
 619                                 clocks = <&gcc GSBI4_UART_CLK>, <&gcc GSBI4_H_CLK>;
 620                                 clock-names = "core", "iface";
 621                                 status = "disabled";
 622                         };
 623
 624                         i2c@16380000 {
 625                                 compatible = "qcom,i2c-qup-v1.1.1";
 626                                 reg = <0x16380000 0x1000>;
 627                                 interrupts = <0 153 0>;
 628
 629                                 clocks = <&gcc GSBI4_QUP_CLK>, <&gcc GSBI4_H_CLK>;
 630                                 clock-names = "core", "iface";
 631                                 status = "disabled";
 632
 633                                 #address-cells = <1>;
 634                                 #size-cells = <0>;
 635                         };
 636                 };
 637
 638                 gsbi5: gsbi@1a200000 {
 639                         compatible = "qcom,gsbi-v1.0.0";
 640                         cell-index = <5>;
 641                         reg = <0x1a200000 0x100>;
 642                         clocks = <&gcc GSBI5_H_CLK>;
 643                         clock-names = "iface";
 644                         #address-cells = <1>;
 645                         #size-cells = <1>;
 646                         ranges;
 647                         status = "disabled";
 648
 649                         syscon-tcsr = <&tcsr>;
 650
 651                         uart5: serial@1a240000 {
 652                                 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
 653                                 reg = <0x1a240000 0x1000>,
 654                                       <0x1a200000 0x1000>;
 655                                 interrupts = <0 154 0x0>;
 656                                 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
 657                                 clock-names = "core", "iface";
 658                                 status = "disabled";
 659                         };
 660
 661                         i2c@1a280000 {
 662                                 compatible = "qcom,i2c-qup-v1.1.1";
 663                                 reg = <0x1a280000 0x1000>;
 664                                 interrupts = <0 155 0>;
 665
 666                                 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
 667                                 clock-names = "core", "iface";
 668                                 status = "disabled";
 669
 670                                 #address-cells = <1>;
 671                                 #size-cells = <0>;
 672                         };
 673
 674                         spi@1a280000 {
 675                                 compatible = "qcom,spi-qup-v1.1.1";
 676                                 reg = <0x1a280000 0x1000>;
 677                                 interrupts = <0 155 0>;
 678
 679                                 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
 680                                 clock-names = "core", "iface";
 681                                 status = "disabled";
 682
 683                                 #address-cells = <1>;
 684                                 #size-cells = <0>;
 685                         };
 686                 };
 687
 688                 gsbi6: gsbi@16500000 {
 689                         compatible = "qcom,gsbi-v1.0.0";
 690                         cell-index = <6>;
 691                         reg = <0x16500000 0x100>;
 692                         clocks = <&gcc GSBI6_H_CLK>;
 693                         clock-names = "iface";
 694                         #address-cells = <1>;
 695                         #size-cells = <1>;
 696                         ranges;
 697                         status = "disabled";
 698
 699                         syscon-tcsr = <&tcsr>;
 700
 701                         uart6: serial@16540000 {
 702                                 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
 703                                 reg = <0x16540000 0x1000>,
 704                                       <0x16500000 0x1000>;
 705                                 interrupts = <0 156 0x0>;
 706                                 clocks = <&gcc GSBI6_UART_CLK>, <&gcc GSBI6_H_CLK>;
 707                                 clock-names = "core", "iface";
 708                                 status = "disabled";
 709                         };
 710
 711                         i2c@16580000 {
 712                                 compatible = "qcom,i2c-qup-v1.1.1";
 713                                 reg = <0x16580000 0x1000>;
 714                                 interrupts = <0 157 0>;
 715
 716                                 clocks = <&gcc GSBI6_QUP_CLK>, <&gcc GSBI6_H_CLK>;
 717                                 clock-names = "core", "iface";
 718                                 status = "disabled";
 719
 720                                 #address-cells = <1>;
 721                                 #size-cells = <0>;
 722                         };
 723
 724                         spi@16580000 {
 725                                 compatible = "qcom,spi-qup-v1.1.1";
 726                                 reg = <0x16580000 0x1000>;
 727                                 interrupts = <0 157 0>;
 728
 729                                 clocks = <&gcc GSBI6_QUP_CLK>, <&gcc GSBI6_H_CLK>;
 730                                 clock-names = "core", "iface";
 731                                 status = "disabled";
 732
 733                                 #address-cells = <1>;
 734                                 #size-cells = <0>;
 735                         };
 736                 };
 737
 738                 gsbi7: gsbi@16600000 {
 739                         compatible = "qcom,gsbi-v1.0.0";
 740                         cell-index = <7>;
 741                         reg = <0x16600000 0x100>;
 742                         clocks = <&gcc GSBI7_H_CLK>;
 743                         clock-names = "iface";
 744                         #address-cells = <1>;
 745                         #size-cells = <1>;
 746                         ranges;
 747                         status = "disabled";
 748
 749                         syscon-tcsr = <&tcsr>;
 750
 751                         uart7: serial@16640000 {
 752                                 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
 753                                 reg = <0x16640000 0x1000>,
 754                                       <0x16600000 0x1000>;
 755                                 interrupts = <0 158 0x0>;
 756                                 clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
 757                                 clock-names = "core", "iface";
 758                                 status = "disabled";
 759                         };
 760
 761                         i2c@16680000 {
 762                                 compatible = "qcom,i2c-qup-v1.1.1";
 763                                 reg = <0x16680000 0x1000>;
 764                                 interrupts = <0 159 0>;
 765
 766                                 clocks = <&gcc GSBI7_QUP_CLK>, <&gcc GSBI7_H_CLK>;
 767                                 clock-names = "core", "iface";
 768                                 status = "disabled";
 769
 770                                 #address-cells = <1>;
 771                                 #size-cells = <0>;
 772                         };
 773
 774                 };
 775
 776                 sata_phy: sata-phy@1b400000 {
 777                         compatible = "qcom,ipq806x-sata-phy";
 778                         reg = <0x1b400000 0x200>;
 779
 780                         clocks = <&gcc SATA_PHY_CFG_CLK>;
 781                         clock-names = "cfg";
 782
 783                         #phy-cells = <0>;
 784                         status = "disabled";
 785                 };
 786
 787                 sata@29000000 {
 788                         compatible = "qcom,ipq806x-ahci", "generic-ahci";
 789                         reg = <0x29000000 0x180>;
 790
 791                         interrupts = <0 209 0x0>;
 792
 793                         clocks = <&gcc SFAB_SATA_S_H_CLK>,
 794                                  <&gcc SATA_H_CLK>,
 795                                  <&gcc SATA_A_CLK>,
 796                                  <&gcc SATA_RXOOB_CLK>,
 797                                  <&gcc SATA_PMALIVE_CLK>;
 798                         clock-names = "slave_face", "iface", "core",
 799                                         "rxoob", "pmalive";
 800
 801                         assigned-clocks = <&gcc SATA_RXOOB_CLK>, <&gcc SATA_PMALIVE_CLK>;
 802                         assigned-clock-rates = <100000000>, <100000000>;
 803
 804                         phys = <&sata_phy>;
 805                         phy-names = "sata-phy";
 806                         status = "disabled";
 807                 };
 808
 809                 qcom,ssbi@500000 {
 810                         compatible = "qcom,ssbi";
 811                         reg = <0x00500000 0x1000>;
 812                         qcom,controller-type = "pmic-arbiter";
 813                 };
 814
 815                 gcc: clock-controller@900000 {
 816                         compatible = "qcom,gcc-ipq8064";
 817                         reg = <0x00900000 0x4000>;
 818                         #clock-cells = <1>;
 819                         #reset-cells = <1>;
 820                 };
 821
 822                 lcc: clock-controller@28000000 {
 823                         compatible = "qcom,lcc-ipq8064";
 824                         reg = <0x28000000 0x1000>;
 825                         #clock-cells = <1>;
 826                         #reset-cells = <1>;
 827                 };
 828
 829                 tcsr: syscon@1a400000 {
 830                         compatible = "qcom,tcsr-ipq8064", "syscon";
 831                         reg = <0x1a400000 0x100>;
 832                 };
 833
 834                 tsens: tsens-ipq806x {
 835                         compatible = "qcom,ipq806x-tsens";
 836                         reg = <0x900000 0x3678>, <0x700000 0x420>;
 837                         reg-names = "tsens_physical", "tsens_eeprom_physical";
 838                         interrupts = <0 178 0>;
 839                         qcom,sensors = <11>;
 840                         qcom,tsens_factor = <1000>;
 841                         qcom,slope = <1176 1176 1154 1176 1111 1132 1132 1199 1132 1199 1132>;
 842                 };
 843
 844                 qcom,msm-thermal {
 845                         compatible = "qcom,msm-thermal";
 846                         qcom,sensor-id = <0>;
 847                         qcom,poll-ms = <250>;
 848                         qcom,limit-temp = <105>;
 849                         qcom,temp-hysteresis = <10>;
 850                         qcom,freq-step = <2>;
 851                         qcom,core-limit-temp = <115>;
 852                         qcom,core-temp-hysteresis = <10>;
 853                         qcom,core-control-mask = <0xe>;
 854                 };
 855
 856                 sfpb_mutex_block: syscon@1200600 {
 857                         compatible = "syscon";
 858                         reg = <0x01200600 0x100>;
 859                 };
 860
 861                 hs_phy_1: phy@100f8800 {
 862                         compatible = "qcom,dwc3-hs-usb-phy";
 863                         reg = <0x100f8800 0x30>;
 864                         clocks = <&gcc USB30_1_UTMI_CLK>;
 865                         clock-names = "ref";
 866                         #phy-cells = <0>;
 867
 868                         status = "disabled";
 869                 };
 870
 871                 ss_phy_1: phy@100f8830 {
 872                         compatible = "qcom,dwc3-ss-usb-phy";
 873                         reg = <0x100f8830 0x30>;
 874                         clocks = <&gcc USB30_1_MASTER_CLK>;
 875                         clock-names = "ref";
 876                         #phy-cells = <0>;
 877
 878                         status = "disabled";
 879                 };
 880
 881                 hs_phy_0: phy@110f8800 {
 882                         compatible = "qcom,dwc3-hs-usb-phy";
 883                         reg = <0x110f8800 0x30>;
 884                         clocks = <&gcc USB30_0_UTMI_CLK>;
 885                         clock-names = "ref";
 886                         #phy-cells = <0>;
 887
 888                         status = "disabled";
 889                 };
 890
 891                 ss_phy_0: phy@110f8830 {
 892                         compatible = "qcom,dwc3-ss-usb-phy";
 893                         reg = <0x110f8830 0x30>;
 894                         clocks = <&gcc USB30_0_MASTER_CLK>;
 895                         clock-names = "ref";
 896                         #phy-cells = <0>;
 897
 898                         status = "disabled";
 899                 };
 900
 901                 usb3_0: usb30@0 {
 902                         compatible = "qcom,dwc3";
 903                         #address-cells = <1>;
 904                         #size-cells = <1>;
 905                         clocks = <&gcc USB30_0_MASTER_CLK>;
 906                         clock-names = "core";
 907
 908                         ranges;
 909
 910                         status = "disabled";
 911                         resets = <&gcc USB30_0_MASTER_RESET>;
 912                         reset-names = "usb30_mstr_rst";
 913
 914                         dwc3@11000000 {
 915                                 compatible = "snps,dwc3";
 916                                 reg = <0x11000000 0xcd00>;
 917                                 interrupts = <0 110 0x4>;
 918                                 phys = <&hs_phy_0>, <&ss_phy_0>;
 919                                 phy-names = "usb2-phy", "usb3-phy";
 920                                 tx-fifo-resize;
 921                                 dr_mode = "host";
 922                         };
 923                 };
 924
 925                 usb3_1: usb30@1 {
 926                         compatible = "qcom,dwc3";
 927                         #address-cells = <1>;
 928                         #size-cells = <1>;
 929                         clocks = <&gcc USB30_1_MASTER_CLK>;
 930                         clock-names = "core";
 931
 932                         ranges;
 933
 934                         status = "disabled";
 935
 936                         dwc3@10000000 {
 937                                 compatible = "snps,dwc3";
 938                                 reg = <0x10000000 0xcd00>;
 939                                 interrupts = <0 205 0x4>;
 940                                 phys = <&hs_phy_1>, <&ss_phy_1>;
 941                                 phy-names = "usb2-phy", "usb3-phy";
 942                                 tx-fifo-resize;
 943                                 dr_mode = "host";
 944                         };
 945                 };
 946
 947                 pcie0: pci@1b500000 {
 948                         compatible = "qcom,pcie-v0";
 949                         reg = <0x1b500000 0x1000
 950                                0x1b502000 0x80
 951                                0x1b600000 0x100
 952                                0x0ff00000 0x100000>;
 953                         reg-names = "dbi", "elbi", "parf", "config";
 954                         device_type = "pci";
 955                         linux,pci-domain = <0>;
 956                         bus-range = <0x00 0xff>;
 957                         num-lanes = <1>;
 958                         #address-cells = <3>;
 959                         #size-cells = <2>;
 960
 961                         ranges = <0x81000000 0 0x0fe00000 0x0fe00000 0 0x00100000   /* downstream I/O */
 962                                   0x82000000 0 0x08000000 0x08000000 0 0x07e00000>; /* non-prefetchable memory */
 963
 964                         interrupts = <GIC_SPI 35 IRQ_TYPE_NONE>;
 965                         interrupt-names = "msi";
 966                         #interrupt-cells = <1>;
 967                         interrupt-map-mask = <0 0 0 0x7>;
 968                         interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
 969                                         <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
 970                                         <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
 971                                         <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
 972
 973                         clocks = <&gcc PCIE_A_CLK>,
 974                                  <&gcc PCIE_H_CLK>,
 975                                  <&gcc PCIE_PHY_CLK>,
 976                                  <&gcc PCIE_AUX_CLK>,
 977                                  <&gcc PCIE_ALT_REF_CLK>;
 978                         clock-names = "core", "iface", "phy", "aux", "ref";
 979
 980                         assigned-clocks = <&gcc PCIE_ALT_REF_CLK>;
 981                         assigned-clock-rates = <100000000>;
 982
 983                         resets = <&gcc PCIE_ACLK_RESET>,
 984                                  <&gcc PCIE_HCLK_RESET>,
 985                                  <&gcc PCIE_POR_RESET>,
 986                                  <&gcc PCIE_PCI_RESET>,
 987                                  <&gcc PCIE_PHY_RESET>,
 988                                  <&gcc PCIE_EXT_RESET>;
 989                         reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
 990
 991                         pinctrl-0 = <&pcie0_pins>;
 992                         pinctrl-names = "default";
 993
 994                         perst-gpio = <&qcom_pinmux 3 GPIO_ACTIVE_LOW>;
 995
 996                         status = "disabled";
 997                 };
 998
 999                 pcie1: pci@1b700000 {
1000                         compatible = "qcom,pcie-v0";
1001                         reg = <0x1b700000 0x1000
1002                                0x1b702000 0x80
1003                                0x1b800000 0x100
1004                                0x31f00000 0x100000>;
1005                         reg-names = "dbi", "elbi", "parf", "config";
1006                         device_type = "pci";
1007                         linux,pci-domain = <1>;
1008                         bus-range = <0x00 0xff>;
1009                         num-lanes = <1>;
1010                         #address-cells = <3>;
1011                         #size-cells = <2>;
1012
1013                         ranges = <0x81000000 0 0x31e00000 0x31e00000 0 0x00100000   /* downstream I/O */
1014                                   0x82000000 0 0x2e000000 0x2e000000 0 0x03e00000>; /* non-prefetchable memory */
1015
1016                         interrupts = <GIC_SPI 57 IRQ_TYPE_NONE>;
1017                         interrupt-names = "msi";
1018                         #interrupt-cells = <1>;
1019                         interrupt-map-mask = <0 0 0 0x7>;
1020                         interrupt-map = <0 0 0 1 &intc 0 58 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1021                                         <0 0 0 2 &intc 0 59 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1022                                         <0 0 0 3 &intc 0 60 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1023                                         <0 0 0 4 &intc 0 61 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1024
1025                         clocks = <&gcc PCIE_1_A_CLK>,
1026                                  <&gcc PCIE_1_H_CLK>,
1027                                  <&gcc PCIE_1_PHY_CLK>,
1028                                  <&gcc PCIE_1_AUX_CLK>,
1029                                  <&gcc PCIE_1_ALT_REF_CLK>;
1030                         clock-names = "core", "iface", "phy", "aux", "ref";
1031
1032                         assigned-clocks = <&gcc PCIE_1_ALT_REF_CLK>;
1033                         assigned-clock-rates = <100000000>;
1034
1035                         resets = <&gcc PCIE_1_ACLK_RESET>,
1036                                  <&gcc PCIE_1_HCLK_RESET>,
1037                                  <&gcc PCIE_1_POR_RESET>,
1038                                  <&gcc PCIE_1_PCI_RESET>,
1039                                  <&gcc PCIE_1_PHY_RESET>,
1040                                  <&gcc PCIE_1_EXT_RESET>;
1041                         reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
1042
1043                         pinctrl-0 = <&pcie1_pins>;
1044                         pinctrl-names = "default";
1045
1046                         perst-gpio = <&qcom_pinmux 48 GPIO_ACTIVE_LOW>;
1047
1048                         status = "disabled";
1049                 };
1050
1051                 pcie2: pci@1b900000 {
1052                         compatible = "qcom,pcie-v0";
1053                         reg = <0x1b900000 0x1000
1054                                0x1b902000 0x80
1055                                0x1ba00000 0x100
1056                                0x35f00000 0x100000>;
1057                         reg-names = "dbi", "elbi", "parf", "config";
1058                         device_type = "pci";
1059                         linux,pci-domain = <2>;
1060                         bus-range = <0x00 0xff>;
1061                         num-lanes = <1>;
1062                         #address-cells = <3>;
1063                         #size-cells = <2>;
1064
1065                         ranges = <0x81000000 0 0x35e00000 0x35e00000 0 0x00100000   /* downstream I/O */
1066                                   0x82000000 0 0x32000000 0x32000000 0 0x03e00000>; /* non-prefetchable memory */
1067
1068                         interrupts = <GIC_SPI 71 IRQ_TYPE_NONE>;
1069                         interrupt-names = "msi";
1070                         #interrupt-cells = <1>;
1071                         interrupt-map-mask = <0 0 0 0x7>;
1072                         interrupt-map = <0 0 0 1 &intc 0 72 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1073                                         <0 0 0 2 &intc 0 73 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1074                                         <0 0 0 3 &intc 0 74 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1075                                         <0 0 0 4 &intc 0 75 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1076
1077                         clocks = <&gcc PCIE_2_A_CLK>,
1078                                  <&gcc PCIE_2_H_CLK>,
1079                                  <&gcc PCIE_2_PHY_CLK>,
1080                                  <&gcc PCIE_2_AUX_CLK>,
1081                                  <&gcc PCIE_2_ALT_REF_CLK>;
1082                         clock-names = "core", "iface", "phy", "aux", "ref";
1083
1084                         assigned-clocks = <&gcc PCIE_2_ALT_REF_CLK>;
1085                         assigned-clock-rates = <100000000>;
1086
1087                         resets = <&gcc PCIE_2_ACLK_RESET>,
1088                                  <&gcc PCIE_2_HCLK_RESET>,
1089                                  <&gcc PCIE_2_POR_RESET>,
1090                                  <&gcc PCIE_2_PCI_RESET>,
1091                                  <&gcc PCIE_2_PHY_RESET>,
1092                                  <&gcc PCIE_2_EXT_RESET>;
1093                         reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
1094
1095                         pinctrl-0 = <&pcie2_pins>;
1096                         pinctrl-names = "default";
1097
1098                         perst-gpio = <&qcom_pinmux 63 GPIO_ACTIVE_LOW>;
1099
1100                         status = "disabled";
1101                 };
1102
1103                 adm_dma: dma@18300000 {
1104                         compatible = "qcom,adm";
1105                         reg = <0x18300000 0x100000>;
1106                         interrupts = <0 170 0>;
1107                         #dma-cells = <1>;
1108
1109                         clocks = <&gcc ADM0_CLK>, <&gcc ADM0_PBUS_CLK>;
1110                         clock-names = "core", "iface";
1111
1112                         resets = <&gcc ADM0_RESET>,
1113                                  <&gcc ADM0_PBUS_RESET>,
1114                                  <&gcc ADM0_C0_RESET>,
1115                                  <&gcc ADM0_C1_RESET>,
1116                                  <&gcc ADM0_C2_RESET>;
1117                         reset-names = "clk", "pbus", "c0", "c1", "c2";
1118                         qcom,ee = <0>;
1119
1120                         status = "disabled";
1121                 };
1122
1123                 nand@1ac00000 {
1124                         compatible = "qcom,ebi2-nandc";
1125                         reg = <0x1ac00000 0x800>;
1126
1127                         clocks = <&gcc EBI2_CLK>,
1128                                  <&gcc EBI2_AON_CLK>;
1129                         clock-names = "core", "aon";
1130
1131                         dmas = <&adm_dma 3>;
1132                         dma-names = "rxtx";
1133                         qcom,cmd-crci = <15>;
1134                         qcom,data-crci = <3>;
1135
1136                         status = "disabled";
1137                 };
1138
1139                 nss_common: syscon@03000000 {
1140                         compatible = "syscon";
1141                         reg = <0x03000000 0x0000FFFF>;
1142                 };
1143
1144                 qsgmii_csr: syscon@1bb00000 {
1145                         compatible = "syscon";
1146                         reg = <0x1bb00000 0x000001FF>;
1147                 };
1148
1149                 gmac0: ethernet@37000000 {
1150                         device_type = "network";
1151                         compatible = "qcom,ipq806x-gmac", "snps,dwmac";
1152                         reg = <0x37000000 0x200000>;
1153                         interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
1154                         interrupt-names = "macirq";
1155
1156                         qcom,nss-common = <&nss_common>;
1157                         qcom,qsgmii-csr = <&qsgmii_csr>;
1158
1159                         clocks = <&gcc GMAC_CORE1_CLK>;
1160                         clock-names = "stmmaceth";
1161
1162                         resets = <&gcc GMAC_CORE1_RESET>;
1163                         reset-names = "stmmaceth";
1164
1165                         status = "disabled";
1166                 };
1167
1168                 gmac1: ethernet@37200000 {
1169                         device_type = "network";
1170                         compatible = "qcom,ipq806x-gmac", "snps,dwmac";
1171                         reg = <0x37200000 0x200000>;
1172                         interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
1173                         interrupt-names = "macirq";
1174
1175                         qcom,nss-common = <&nss_common>;
1176                         qcom,qsgmii-csr = <&qsgmii_csr>;
1177
1178                         clocks = <&gcc GMAC_CORE2_CLK>;
1179                         clock-names = "stmmaceth";
1180
1181                         resets = <&gcc GMAC_CORE2_RESET>;
1182                         reset-names = "stmmaceth";
1183
1184                         status = "disabled";
1185                 };
1186
1187                 gmac2: ethernet@37400000 {
1188                         device_type = "network";
1189                         compatible = "qcom,ipq806x-gmac", "snps,dwmac";
1190                         reg = <0x37400000 0x200000>;
1191                         interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
1192                         interrupt-names = "macirq";
1193
1194                         qcom,nss-common = <&nss_common>;
1195                         qcom,qsgmii-csr = <&qsgmii_csr>;
1196
1197                         clocks = <&gcc GMAC_CORE3_CLK>;
1198                         clock-names = "stmmaceth";
1199
1200                         resets = <&gcc GMAC_CORE3_RESET>;
1201                         reset-names = "stmmaceth";
1202
1203                         status = "disabled";
1204                 };
1205
1206                 gmac3: ethernet@37600000 {
1207                         device_type = "network";
1208                         compatible = "qcom,ipq806x-gmac", "snps,dwmac";
1209                         reg = <0x37600000 0x200000>;
1210                         interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
1211                         interrupt-names = "macirq";
1212
1213                         qcom,nss-common = <&nss_common>;
1214                         qcom,qsgmii-csr = <&qsgmii_csr>;
1215
1216                         clocks = <&gcc GMAC_CORE4_CLK>;
1217                         clock-names = "stmmaceth";
1218
1219                         resets = <&gcc GMAC_CORE4_RESET>;
1220                         reset-names = "stmmaceth";
1221
1222                         status = "disabled";
1223                 };
1224                 /* Temporary fixed regulator */
1225                 vsdcc_fixed: vsdcc-regulator {
1226                         compatible = "regulator-fixed";
1227                         regulator-name = "SDCC Power";
1228                         regulator-min-microvolt = <3300000>;
1229                         regulator-max-microvolt = <3300000>;
1230                         regulator-always-on;
1231                 };
1232
1233                 sdcc1bam:dma@12402000 {
1234                         compatible = "qcom,bam-v1.3.0";
1235                         reg = <0x12402000 0x8000>;
1236                         interrupts = <0 98 0>;
1237                         clocks = <&gcc SDC1_H_CLK>;
1238                         clock-names = "bam_clk";
1239                         #dma-cells = <1>;
1240                         qcom,ee = <0>;
1241                 };
1242
1243                 sdcc3bam:dma@12182000 {
1244                         compatible = "qcom,bam-v1.3.0";
1245                         reg = <0x12182000 0x8000>;
1246                         interrupts = <0 96 0>;
1247                         clocks = <&gcc SDC3_H_CLK>;
1248                         clock-names = "bam_clk";
1249                         #dma-cells = <1>;
1250                         qcom,ee = <0>;
1251                 };
1252
1253                 amba {
1254                         compatible = "arm,amba-bus";
1255                         #address-cells = <1>;
1256                         #size-cells = <1>;
1257                         ranges;
1258                         sdcc1: sdcc@12400000 {
1259                                 status          = "disabled";
1260                                 compatible      = "arm,pl18x", "arm,primecell";
1261                                 arm,primecell-periphid = <0x00051180>;
1262                                 reg             = <0x12400000 0x2000>;
1263                                 interrupts      = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
1264                                 interrupt-names = "cmd_irq";
1265                                 clocks          = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
1266                                 clock-names     = "mclk", "apb_pclk";
1267                                 bus-width       = <8>;
1268                                 max-frequency   = <48000000>;
1269                                 non-removable;
1270                                 cap-sd-highspeed;
1271                                 cap-mmc-highspeed;
1272                                 vmmc-supply = <&vsdcc_fixed>;
1273                                 #dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
1274                                 #dma-names = "tx", "rx";
1275                         };
1276
1277                         sdcc3: sdcc@12180000 {
1278                                 compatible      = "arm,pl18x", "arm,primecell";
1279                                 arm,primecell-periphid = <0x00051180>;
1280                                 status          = "disabled";
1281                                 reg             = <0x12180000 0x2000>;
1282                                 interrupts      = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
1283                                 interrupt-names = "cmd_irq";
1284                                 clocks          = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
1285                                 clock-names     = "mclk", "apb_pclk";
1286                                 bus-width       = <8>;
1287                                 cap-sd-highspeed;
1288                                 cap-mmc-highspeed;
1289                                 max-frequency   = <192000000>;
1290                                 #mmc-ddr-1_8v;
1291                                 sd-uhs-sdr50;
1292                                 vmmc-supply = <&vsdcc_fixed>;
1293                                 #dmas = <&sdcc3bam 2>, <&sdcc3bam 1>;
1294                                 #dma-names = "tx", "rx";
1295                         };
1296                 };
1297
1298         };
1299
1300         sfpb_mutex: sfpb-mutex {
1301                 compatible = "qcom,sfpb-mutex";
1302                 syscon = <&sfpb_mutex_block 4 4>;
1303
1304                 #hwlock-cells = <1>;
1305         };
1306
1307         smem {
1308                 compatible = "qcom,smem";
1309                 memory-region = <&smem>;
1310                 hwlocks = <&sfpb_mutex 3>;
1311         };
1312 };