target/linux/ipq40xx/patches-4.14/071-qcom-ipq4019-use-v2-of-the-kpss-bringup-mechanism.patch

   1 From 364123029d8d547336323fbd3d659ecd0bba913f Mon Sep 17 00:00:00 2001
   2 From: Matthew McClintock <mmcclint@codeaurora.org>
   3 Date: Mon, 23 Jul 2018 08:41:02 +0200
   4 Subject: [PATCH 5/8] qcom: ipq4019: use v2 of the kpss bringup mechanism
   5
   6 v1 was the incorrect choice here and sometimes the board
   7 would not come up properly.
   8
   9 Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org>
  10 Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
  11 Signed-off-by: John Crispin <john@phrozen.org>
  12 ---
  13  arch/arm/boot/dts/qcom-ipq4019.dtsi | 25 +++++++++++++++++--------
  14  1 file changed, 17 insertions(+), 8 deletions(-)
  15
  16 --- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
  17 +++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
  18 @@ -34,7 +34,8 @@
  19                 cpu@0 {
  20                         device_type = "cpu";
  21                         compatible = "arm,cortex-a7";
  22 -                       enable-method = "qcom,kpss-acc-v1";
  23 +                       enable-method = "qcom,kpss-acc-v2";
  24 +                       next-level-cache = <&L2>;
  25                         qcom,acc = <&acc0>;
  26                         qcom,saw = <&saw0>;
  27                         reg = <0x0>;
  28 @@ -53,7 +54,8 @@
  29                 cpu@1 {
  30                         device_type = "cpu";
  31                         compatible = "arm,cortex-a7";
  32 -                       enable-method = "qcom,kpss-acc-v1";
  33 +                       enable-method = "qcom,kpss-acc-v2";
  34 +                       next-level-cache = <&L2>;
  35                         qcom,acc = <&acc1>;
  36                         qcom,saw = <&saw1>;
  37                         reg = <0x1>;
  38 @@ -64,7 +66,8 @@
  39                 cpu@2 {
  40                         device_type = "cpu";
  41                         compatible = "arm,cortex-a7";
  42 -                       enable-method = "qcom,kpss-acc-v1";
  43 +                       enable-method = "qcom,kpss-acc-v2";
  44 +                       next-level-cache = <&L2>;
  45                         qcom,acc = <&acc2>;
  46                         qcom,saw = <&saw2>;
  47                         reg = <0x2>;
  48 @@ -75,13 +78,20 @@
  49                 cpu@3 {
  50                         device_type = "cpu";
  51                         compatible = "arm,cortex-a7";
  52 -                       enable-method = "qcom,kpss-acc-v1";
  53 +                       enable-method = "qcom,kpss-acc-v2";
  54 +                       next-level-cache = <&L2>;
  55                         qcom,acc = <&acc3>;
  56                         qcom,saw = <&saw3>;
  57                         reg = <0x3>;
  58                         clocks = <&gcc GCC_APPS_CLK_SRC>;
  59                         clock-frequency = <0>;
  60                 };
  61 +
  62 +               L2: l2-cache {
  63 +                       compatible = "cache";
  64 +                       cache-level = <2>;
  65 +                       qcom,saw = <&saw_l2>;
  66 +               };
  67         };
  68
  69         pmu {
  70 @@ -213,22 +223,22 @@
  71                 };
  72
  73                  acc0: clock-controller@b088000 {
  74 -                        compatible = "qcom,kpss-acc-v1";
  75 +                       compatible = "qcom,kpss-acc-v2";
  76                          reg = <0x0b088000 0x1000>, <0xb008000 0x1000>;
  77                  };
  78
  79                  acc1: clock-controller@b098000 {
  80 -                        compatible = "qcom,kpss-acc-v1";
  81 +                       compatible = "qcom,kpss-acc-v2";
  82                          reg = <0x0b098000 0x1000>, <0xb008000 0x1000>;
  83                  };
  84
  85                  acc2: clock-controller@b0a8000 {
  86 -                        compatible = "qcom,kpss-acc-v1";
  87 +                       compatible = "qcom,kpss-acc-v2";
  88                          reg = <0x0b0a8000 0x1000>, <0xb008000 0x1000>;
  89                  };
  90
  91                  acc3: clock-controller@b0b8000 {
  92 -                        compatible = "qcom,kpss-acc-v1";
  93 +                       compatible = "qcom,kpss-acc-v2";
  94                          reg = <0x0b0b8000 0x1000>, <0xb008000 0x1000>;
  95                  };
  96
  97 @@ -256,6 +266,12 @@
  98                          regulator;
  99                  };
 100
 101 +               saw_l2: regulator@b012000 {
 102 +                       compatible = "qcom,saw2";
 103 +                       reg = <0xb012000 0x1000>;
 104 +                       regulator;
 105 +               };
 106 +
 107                 serial@78af000 {
 108                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 109                         reg = <0x78af000 0x200>;