ipq40xx: files-4.19: Clear some DTC warnings
[oweals/openwrt.git] / target / linux / ipq40xx / files-4.19 / arch / arm / boot / dts / qcom-ipq4028-wpj428.dts
1 /* Copyright (c) 2015, The Linux Foundation. All rights reserved.
2  * Copyright (c) 2017, Christian Mehlis <christian@m3hlis.de>
3  * Copyright (c) 2017-2018, Sven Eckelmann <sven.eckelmann@openmesh.com>
4  *
5  * Permission to use, copy, modify, and/or distribute this software for any
6  * purpose with or without fee is hereby granted, provided that the above
7  * copyright notice and this permission notice appear in all copies.
8  *
9  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16  *
17  */
18
19 #include "qcom-ipq4019.dtsi"
20 #include <dt-bindings/gpio/gpio.h>
21 #include <dt-bindings/input/input.h>
22 #include <dt-bindings/soc/qcom,tcsr.h>
23
24 / {
25         model = "Compex WPJ428";
26         compatible = "compex,wpj428", "qcom,ipq4019";
27
28         soc {
29                 mdio@90000 {
30                         status = "okay";
31                 };
32
33                 ess-psgmii@98000 {
34                         status = "okay";
35                 };
36
37                 tcsr@194b000 {
38                         /* select hostmode */
39                         compatible = "qcom,tcsr";
40                         reg = <0x194b000 0x100>;
41                         qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
42                         status = "okay";
43                 };
44
45                 tcsr@1949000 {
46                         compatible = "qcom,tcsr";
47                         reg = <0x1949000 0x100>;
48                         qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
49                 };
50
51                 ess_tcsr@1953000 {
52                         compatible = "qcom,tcsr";
53                         reg = <0x1953000 0x1000>;
54                         qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
55                 };
56
57                 tcsr@1957000 {
58                         compatible = "qcom,tcsr";
59                         reg = <0x1957000 0x100>;
60                         qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
61                 };
62
63                 usb2: usb2@60f8800 {
64                         status = "okay";
65                 };
66
67                 usb3: usb3@8af8800 {
68                         status = "okay";
69                 };
70
71                 crypto@8e3a000 {
72                         status = "okay";
73                 };
74
75                 watchdog@b017000 {
76                         status = "okay";
77                 };
78
79                 ess-switch@c000000 {
80                         switch_lan_bmp = <0x10>;
81                         switch_wan_bmp = <0x20>;
82
83                         status = "okay";
84                 };
85
86                 edma@c080000 {
87                         status = "okay";
88                 };
89         };
90
91         gpio-keys {
92                 compatible = "gpio-keys";
93
94                 reset {
95                         label = "reset";
96                         gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
97                         linux,code = <KEY_RESTART>;
98                 };
99         };
100
101         aliases {
102                 led-boot = &status;
103                 led-failsafe = &status;
104                 led-upgrade = &status;
105         };
106
107         gpio-leds {
108                 compatible = "gpio-leds";
109
110                 status: rss4 {
111                         label = "wpj428:green:rss4";
112                         gpios = <&tlmm 5 GPIO_ACTIVE_HIGH>;
113                 };
114
115                 rss3 {
116                         label = "wpj428:green:rss3";
117                         gpios = <&tlmm 4 GPIO_ACTIVE_HIGH>;
118                 };
119         };
120
121         beeper: beeper {
122                 compatible = "gpio-beeper";
123                 gpios = <&tlmm 58 GPIO_ACTIVE_HIGH>;
124         };
125 };
126
127 &tlmm {
128         serial_pins: serial_pinmux {
129                 mux {
130                         pins = "gpio60", "gpio61";
131                         function = "blsp_uart0";
132                         bias-disable;
133                 };
134         };
135
136         spi_0_pins: spi_0_pinmux {
137                 pin {
138                         function = "blsp_spi0";
139                         pins = "gpio55", "gpio56", "gpio57";
140                         drive-strength = <12>;
141                         bias-disable;
142                 };
143                 pin_cs {
144                         function = "gpio";
145                         pins = "gpio54";
146                         drive-strength = <2>;
147                         bias-disable;
148                         output-high;
149                 };
150         };
151 };
152
153 &blsp_dma {
154         status = "okay";
155 };
156
157 &blsp1_spi1 {
158         pinctrl-0 = <&spi_0_pins>;
159         pinctrl-names = "default";
160         status = "okay";
161         cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;
162
163         m25p80@0 {
164                 compatible = "jedec,spi-nor";
165                 reg = <0>;
166                 spi-max-frequency = <24000000>;
167
168                 partitions {
169                         compatible = "fixed-partitions";
170                         #address-cells = <1>;
171                         #size-cells = <1>;
172
173                         partition0@0 {
174                                 label = "0:SBL1";
175                                 reg = <0x00000000 0x00040000>;
176                                 read-only;
177                         };
178                         partition1@40000 {
179                                 label = "0:MIBIB";
180                                 reg = <0x00040000 0x00020000>;
181                                 read-only;
182                         };
183                         partition2@60000 {
184                                 label = "0:QSEE";
185                                 reg = <0x00060000 0x00060000>;
186                                 read-only;
187                         };
188                         partition3@c0000 {
189                                 label = "0:CDT";
190                                 reg = <0x000c0000 0x00010000>;
191                                 read-only;
192                         };
193                         partition4@d0000 {
194                                 label = "0:DDRPARAMS";
195                                 reg = <0x000d0000 0x00010000>;
196                                 read-only;
197                         };
198                         partition5@e0000 {
199                                 label = "0:APPSBLENV"; /* uboot env*/
200                                 reg = <0x000e0000 0x00010000>;
201                                 read-only;
202                         };
203                         partition5@f0000 {
204                                 label = "0:APPSBL"; /* uboot */
205                                 reg = <0x000f0000 0x00080000>;
206                                 read-only;
207                         };
208                         partition5@170000 {
209                                 label = "0:ART";
210                                 reg = <0x00170000 0x00010000>;
211                                 read-only;
212                         };
213                         partition6@180000 {
214                                 compatible = "denx,fit";
215                                 label = "firmware";
216                                 reg = <0x00180000 0x01e80000>;
217                         };
218                 };
219         };
220 };
221
222 &blsp1_uart1 {
223         pinctrl-0 = <&serial_pins>;
224         pinctrl-names = "default";
225         status = "okay";
226 };
227
228 &cryptobam {
229         status = "okay";
230 };
231
232 &gmac0 {
233         qcom,phy_mdio_addr = <4>;
234         qcom,poll_required = <1>;
235         qcom,forced_speed = <1000>;
236         qcom,forced_duplex = <1>;
237         vlan_tag = <2 0x20>;
238 };
239
240 &gmac1 {
241         qcom,phy_mdio_addr = <3>;
242         qcom,poll_required = <1>;
243         qcom,forced_speed = <1000>;
244         qcom,forced_duplex = <1>;
245         vlan_tag = <1 0x10>;
246 };
247
248 &usb3_ss_phy {
249         status = "okay";
250 };
251
252 &usb3_hs_phy {
253         status = "okay";
254 };
255
256 &usb2_hs_phy {
257         status = "okay";
258 };
259
260 &wifi0 {
261         status = "okay";
262 };
263
264 &wifi1 {
265         status = "okay";
266 };