ipq40xx: 4.19: Enable pseudo random number generator
[oweals/openwrt.git] / target / linux / ipq40xx / files-4.19 / arch / arm / boot / dts / qcom-ipq4018-jalapeno.dts
1 /* Copyright (c) 2015, The Linux Foundation. All rights reserved.
2  * Copyright (c) 2018, Robert Marko <robimarko@gmail.com>
3  *
4  * Permission to use, copy, modify, and/or distribute this software for any
5  * purpose with or without fee is hereby granted, provided that the above
6  * copyright notice and this permission notice appear in all copies.
7  *
8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15  *
16  */
17
18 #include "qcom-ipq4019.dtsi"
19 #include <dt-bindings/gpio/gpio.h>
20 #include <dt-bindings/input/input.h>
21 #include <dt-bindings/soc/qcom,tcsr.h>
22
23 / {
24         model = "8devices Jalapeno";
25         compatible = "8dev,jalapeno", "qcom,ipq4019";
26
27         soc {
28                 rng@22000 {
29                         status = "okay";
30                 };
31
32                 mdio@90000 {
33                         status = "okay";
34                         pinctrl-0 = <&mdio_pins>;
35                         pinctrl-names = "default";
36                 };
37
38                 ess-psgmii@98000 {
39                         status = "okay";
40                 };
41
42                 counter@4a1000 {
43                         compatible = "qcom,qca-gcnt";
44                         reg = <0x4a1000 0x4>;
45                 };
46
47                 tcsr@1949000 {
48                         compatible = "qcom,tcsr";
49                         reg = <0x1949000 0x100>;
50                         qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
51                 };
52
53                 tcsr@194b000 {
54                         /* select hostmode */
55                         compatible = "qcom,tcsr";
56                         reg = <0x194b000 0x100>;
57                         qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
58                         status = "okay";
59                 };
60
61                 ess_tcsr@1953000 {
62                         compatible = "qcom,tcsr";
63                         reg = <0x1953000 0x1000>;
64                         qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
65                 };
66
67                 tcsr@1957000 {
68                         compatible = "qcom,tcsr";
69                         reg = <0x1957000 0x100>;
70                         qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
71                 };
72
73                 usb2: usb2@60f8800 {
74                         status = "okay";
75                 };
76
77                 usb3: usb3@8af8800 {
78                         status = "okay";
79                 };
80
81                 crypto@8e3a000 {
82                         status = "okay";
83                 };
84
85                 watchdog@b017000 {
86                         status = "okay";
87                 };
88
89                 ess-switch@c000000 {
90                         status = "okay";
91                         switch_lan_bmp = <0x10>; /* lan port bitmap */
92                 };
93
94                 edma@c080000 {
95                         status = "okay";
96                 };
97         };
98 };
99
100 &tlmm {
101         mdio_pins: mdio_pinmux {
102                 pinmux_1 {
103                         pins = "gpio53";
104                         function = "mdio";
105                 };
106                 pinmux_2 {
107                         pins = "gpio52";
108                         function = "mdc";
109                 };
110                 pinconf {
111                         pins = "gpio52", "gpio53";
112                         bias-pull-up;
113                 };
114         };
115
116         serial_pins: serial_pinmux {
117                 mux {
118                         pins = "gpio60", "gpio61";
119                         function = "blsp_uart0";
120                         bias-disable;
121                 };
122         };
123
124         spi_0_pins: spi_0_pinmux {
125                 pin {
126                         function = "blsp_spi0";
127                         pins = "gpio55", "gpio56", "gpio57";
128                         drive-strength = <2>;
129                         bias-disable;
130                 };
131                 pin_cs {
132                         function = "gpio";
133                         pins = "gpio54", "gpio59";
134                         drive-strength = <2>;
135                         bias-disable;
136                         output-high;
137                 };
138         };
139 };
140
141 &blsp_dma {
142         status = "okay";
143 };
144
145 &blsp1_spi1 {
146         pinctrl-0 = <&spi_0_pins>;
147         pinctrl-names = "default";
148         cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>, <&tlmm 59 GPIO_ACTIVE_HIGH>;
149         status = "okay";
150
151         m25p80@0 {
152                 reg = <0>;
153                 compatible = "jedec,spi-nor";
154                 spi-max-frequency = <24000000>;
155
156                 partitions {
157                         compatible = "fixed-partitions";
158                         #address-cells = <1>;
159                         #size-cells = <1>;
160
161                         partition0@0 {
162                                 label = "SBL1";
163                                 reg = <0x00000000 0x00040000>;
164                                 read-only;
165                         };
166                         partition1@40000 {
167                                 label = "MIBIB";
168                                 reg = <0x00040000 0x00020000>;
169                                 read-only;
170                         };
171                         partition2@60000 {
172                                 label = "QSEE";
173                                 reg = <0x00060000 0x00060000>;
174                                 read-only;
175                         };
176                         partition3@c0000 {
177                                 label = "CDT";
178                                 reg = <0x000c0000 0x00010000>;
179                                 read-only;
180                         };
181                         partition4@d0000 {
182                                 label = "DDRPARAMS";
183                                 reg = <0x000d0000 0x00010000>;
184                                 read-only;
185                         };
186                         partition5@e0000 {
187                                 label = "APPSBLENV"; /* uboot env*/
188                                 reg = <0x000e0000 0x00010000>;
189                                 read-only;
190                         };
191                         partition5@f0000 {
192                                 label = "APPSBL"; /* uboot */
193                                 reg = <0x000f0000 0x00080000>;
194                                 read-only;
195                         };
196                         partition5@170000 {
197                                 label = "ART";
198                                 reg = <0x00170000 0x00010000>;
199                                 read-only;
200                         };
201                 };
202         };
203
204         spi-nand@1 {
205                 status = "okay";
206                 compatible = "spi-nand";
207                 reg = <1>;
208                 spi-max-frequency = <24000000>;
209                 partitions {
210                         compatible = "fixed-partitions";
211                         #address-cells = <1>;
212                         #size-cells = <1>;
213
214                         partition0@0 {
215                                 label = "ubi";
216                                 reg = <0x00000000 0x08000000>;
217                         };
218                 };
219         };
220 };
221
222 &blsp1_uart1 {
223         pinctrl-0 = <&serial_pins>;
224         pinctrl-names = "default";
225         status = "okay";
226 };
227
228 &cryptobam {
229         status = "okay";
230 };
231
232 &gmac0 {
233         qcom,poll_required = <1>;
234         qcom,poll_required_dynamic = <1>;
235         qcom,phy_mdio_addr = <3>;
236         vlan_tag = <1 0x10>;
237 };
238
239 &gmac1 {
240         qcom,poll_required = <1>;
241         qcom,poll_required_dynamic = <1>;
242         qcom,phy_mdio_addr = <4>;
243         vlan_tag = <2 0x20>;
244 };
245
246 &wifi0 {
247         status = "okay";
248         qcom,ath10k-calibration-variant = "8devices-Jalapeno";
249 };
250
251 &wifi1 {
252         status = "okay";
253         qcom,ath10k-calibration-variant = "8devices-Jalapeno";
254 };
255
256 &usb3_ss_phy {
257         status = "okay";
258 };
259
260 &usb3_hs_phy {
261         status = "okay";
262 };
263
264 &usb2_hs_phy {
265         status = "okay";
266 };