target/linux/imx6/patches-5.4/003-ARM-dts-imx-Add-GW5913-board-support.patch

   1 From 169e12f99cf9d5fce752564f32fd8df96461de43 Mon Sep 17 00:00:00 2001
   2 From: Robert Jones <rjones@gateworks.com>
   3 Date: Wed, 8 Jan 2020 07:44:23 -0800
   4 Subject: [PATCH 3/4] ARM: dts: imx: Add GW5913 board support
   5
   6 The Gateworks GW5913 is an IMX6 SoC based single board computer with:
   7  - IMX6Q or IMX6DL
   8  - 32bit DDR3 DRAM
   9  - FEC GbE RJ45 front-panel
  10  - 1x miniPCIe socket with PCI Gen2, USB2
  11  - 1x miniPCIe socket with PCI Gen2, USB2, nanoSIM
  12  - 6V to 60V DC input connector
  13  - GPS (ublox ZOE-M8Q)
  14  - bi-color front-panel LED
  15  - 256MB NAND boot device
  16  - nanoSIM socket
  17  - user pushbutton
  18  - Gateworks System Controller (hwmon, pushbutton controller, EEPROM)
  19
  20 Signed-off-by: Robert Jones <rjones@gateworks.com>
  21 Reviewed-by: Tim Harvey <tharvey@gateworks.com>
  22 Signed-off-by: Shawn Guo <shawnguo@kernel.org>
  23 ---
  24  arch/arm/boot/dts/Makefile            |   2 +
  25  arch/arm/boot/dts/imx6dl-gw5913.dts   |  14 ++
  26  arch/arm/boot/dts/imx6q-gw5913.dts    |  14 ++
  27  arch/arm/boot/dts/imx6qdl-gw5913.dtsi | 348 ++++++++++++++++++++++++++++++++++
  28  4 files changed, 378 insertions(+)
  29  create mode 100644 arch/arm/boot/dts/imx6dl-gw5913.dts
  30  create mode 100644 arch/arm/boot/dts/imx6q-gw5913.dts
  31  create mode 100644 arch/arm/boot/dts/imx6qdl-gw5913.dtsi
  32
  33 diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
  34 index 85e53cc..5b059fc 100644
  35 --- a/arch/arm/boot/dts/Makefile
  36 +++ b/arch/arm/boot/dts/Makefile
  37 @@ -424,6 +424,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
  38         imx6dl-gw5904.dtb \
  39         imx6dl-gw5907.dtb \
  40         imx6dl-gw5910.dtb \
  41 +       imx6dl-gw5913.dtb \
  42         imx6dl-hummingboard.dtb \
  43         imx6dl-hummingboard-emmc-som-v15.dtb \
  44         imx6dl-hummingboard-som-v15.dtb \
  45 @@ -497,6 +498,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
  46         imx6q-gw5904.dtb \
  47         imx6q-gw5907.dtb \
  48         imx6q-gw5910.dtb \
  49 +       imx6q-gw5913.dtb \
  50         imx6q-h100.dtb \
  51         imx6q-hummingboard.dtb \
  52         imx6q-hummingboard-emmc-som-v15.dtb \
  53 diff --git a/arch/arm/boot/dts/imx6dl-gw5913.dts b/arch/arm/boot/dts/imx6dl-gw5913.dts
  54 new file mode 100644
  55 index 00000000..b74e533
  56 --- /dev/null
  57 +++ b/arch/arm/boot/dts/imx6dl-gw5913.dts
  58 @@ -0,0 +1,14 @@
  59 +// SPDX-License-Identifier: GPL-2.0
  60 +/*
  61 + * Copyright 2019 Gateworks Corporation
  62 + */
  63 +
  64 +/dts-v1/;
  65 +
  66 +#include "imx6dl.dtsi"
  67 +#include "imx6qdl-gw5913.dtsi"
  68 +
  69 +/ {
  70 +       model = "Gateworks Ventana i.MX6 DualLite/Solo GW5913";
  71 +       compatible = "gw,imx6dl-gw5913", "gw,ventana", "fsl,imx6dl";
  72 +};
  73 diff --git a/arch/arm/boot/dts/imx6q-gw5913.dts b/arch/arm/boot/dts/imx6q-gw5913.dts
  74 new file mode 100644
  75 index 00000000..6f511f1
  76 --- /dev/null
  77 +++ b/arch/arm/boot/dts/imx6q-gw5913.dts
  78 @@ -0,0 +1,14 @@
  79 +// SPDX-License-Identifier: GPL-2.0
  80 +/*
  81 + * Copyright 2019 Gateworks Corporation
  82 + */
  83 +
  84 +/dts-v1/;
  85 +
  86 +#include "imx6q.dtsi"
  87 +#include "imx6qdl-gw5913.dtsi"
  88 +
  89 +/ {
  90 +       model = "Gateworks Ventana i.MX6 Dual/Quad GW5913";
  91 +       compatible = "gw,imx6q-gw5913", "gw,ventana", "fsl,imx6q";
  92 +};
  93 diff --git a/arch/arm/boot/dts/imx6qdl-gw5913.dtsi b/arch/arm/boot/dts/imx6qdl-gw5913.dtsi
  94 new file mode 100644
  95 index 00000000..635c203
  96 --- /dev/null
  97 +++ b/arch/arm/boot/dts/imx6qdl-gw5913.dtsi
  98 @@ -0,0 +1,348 @@
  99 +// SPDX-License-Identifier: GPL-2.0
 100 +/*
 101 + * Copyright 2019 Gateworks Corporation
 102 + */
 103 +
 104 +#include <dt-bindings/gpio/gpio.h>
 105 +
 106 +/ {
 107 +       /* these are used by bootloader for disabling nodes */
 108 +       aliases {
 109 +               led0 = &led0;
 110 +               led1 = &led1;
 111 +               nand = &gpmi;
 112 +               usb0 = &usbh1;
 113 +               usb1 = &usbotg;
 114 +       };
 115 +
 116 +       chosen {
 117 +               stdout-path = &uart2;
 118 +       };
 119 +
 120 +       leds {
 121 +               compatible = "gpio-leds";
 122 +               pinctrl-names = "default";
 123 +               pinctrl-0 = <&pinctrl_gpio_leds>;
 124 +
 125 +               led0: user1 {
 126 +                       label = "user1";
 127 +                       gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
 128 +                       default-state = "on";
 129 +                       linux,default-trigger = "heartbeat";
 130 +               };
 131 +
 132 +               led1: user2 {
 133 +                       label = "user2";
 134 +                       gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
 135 +                       default-state = "off";
 136 +               };
 137 +       };
 138 +
 139 +       memory@10000000 {
 140 +               device_type = "memory";
 141 +               reg = <0x10000000 0x20000000>;
 142 +       };
 143 +
 144 +       pps {
 145 +               compatible = "pps-gpio";
 146 +               pinctrl-names = "default";
 147 +               pinctrl-0 = <&pinctrl_pps>;
 148 +               gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>;
 149 +               status = "okay";
 150 +       };
 151 +
 152 +       reg_3p3v: regulator-3p3v {
 153 +               compatible = "regulator-fixed";
 154 +               regulator-name = "3P3V";
 155 +               regulator-min-microvolt = <3300000>;
 156 +               regulator-max-microvolt = <3300000>;
 157 +               regulator-always-on;
 158 +       };
 159 +
 160 +       reg_5p0v: regulator-5p0v {
 161 +               compatible = "regulator-fixed";
 162 +               regulator-name = "5P0V";
 163 +               regulator-min-microvolt = <5000000>;
 164 +               regulator-max-microvolt = <5000000>;
 165 +               regulator-always-on;
 166 +       };
 167 +};
 168 +
 169 +&fec {
 170 +       pinctrl-names = "default";
 171 +       pinctrl-0 = <&pinctrl_enet>;
 172 +       phy-mode = "rgmii-id";
 173 +       status = "okay";
 174 +};
 175 +
 176 +&gpmi {
 177 +       pinctrl-names = "default";
 178 +       pinctrl-0 = <&pinctrl_gpmi_nand>;
 179 +       status = "okay";
 180 +};
 181 +
 182 +&i2c1 {
 183 +       clock-frequency = <100000>;
 184 +       pinctrl-names = "default";
 185 +       pinctrl-0 = <&pinctrl_i2c1>;
 186 +       status = "okay";
 187 +
 188 +       gpio@23 {
 189 +               compatible = "nxp,pca9555";
 190 +               reg = <0x23>;
 191 +               gpio-controller;
 192 +               #gpio-cells = <2>;
 193 +       };
 194 +
 195 +       eeprom@50 {
 196 +               compatible = "atmel,24c02";
 197 +               reg = <0x50>;
 198 +               pagesize = <16>;
 199 +       };
 200 +
 201 +       eeprom@51 {
 202 +               compatible = "atmel,24c02";
 203 +               reg = <0x51>;
 204 +               pagesize = <16>;
 205 +       };
 206 +
 207 +       eeprom@52 {
 208 +               compatible = "atmel,24c02";
 209 +               reg = <0x52>;
 210 +               pagesize = <16>;
 211 +       };
 212 +
 213 +       eeprom@53 {
 214 +               compatible = "atmel,24c02";
 215 +               reg = <0x53>;
 216 +               pagesize = <16>;
 217 +       };
 218 +
 219 +       rtc@68 {
 220 +               compatible = "dallas,ds1672";
 221 +               reg = <0x68>;
 222 +       };
 223 +};
 224 +
 225 +&i2c2 {
 226 +       clock-frequency = <100000>;
 227 +       pinctrl-names = "default";
 228 +       pinctrl-0 = <&pinctrl_i2c2>;
 229 +       status = "okay";
 230 +};
 231 +
 232 +&i2c3 {
 233 +       clock-frequency = <100000>;
 234 +       pinctrl-names = "default";
 235 +       pinctrl-0 = <&pinctrl_i2c3>;
 236 +       status = "okay";
 237 +};
 238 +
 239 +&pcie {
 240 +       pinctrl-names = "default";
 241 +       pinctrl-0 = <&pinctrl_pcie>;
 242 +       reset-gpio = <&gpio1 0 GPIO_ACTIVE_LOW>;
 243 +       status = "okay";
 244 +};
 245 +
 246 +&pwm2 {
 247 +       pinctrl-names = "default";
 248 +       pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
 249 +       status = "disabled";
 250 +};
 251 +
 252 +&pwm3 {
 253 +       pinctrl-names = "default";
 254 +       pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
 255 +       status = "disabled";
 256 +};
 257 +
 258 +&pwm4 {
 259 +       pinctrl-names = "default";
 260 +       pinctrl-0 = <&pinctrl_pwm4>; /* MX6_DIO3 */
 261 +       status = "disabled";
 262 +};
 263 +
 264 +&uart1 {
 265 +       pinctrl-names = "default";
 266 +       pinctrl-0 = <&pinctrl_uart1>;
 267 +       status = "okay";
 268 +};
 269 +
 270 +&uart2 {
 271 +       pinctrl-names = "default";
 272 +       pinctrl-0 = <&pinctrl_uart2>;
 273 +       status = "okay";
 274 +};
 275 +
 276 +&uart3 {
 277 +       pinctrl-names = "default";
 278 +       pinctrl-0 = <&pinctrl_uart3>;
 279 +       status = "okay";
 280 +};
 281 +
 282 +&uart5 {
 283 +       pinctrl-names = "default";
 284 +       pinctrl-0 = <&pinctrl_uart5>;
 285 +       status = "okay";
 286 +};
 287 +
 288 +&usbotg {
 289 +       pinctrl-names = "default";
 290 +       pinctrl-0 = <&pinctrl_usbotg>;
 291 +       disable-over-current;
 292 +       status = "okay";
 293 +};
 294 +
 295 +&usbh1 {
 296 +       status = "okay";
 297 +};
 298 +
 299 +&wdog1 {
 300 +       pinctrl-names = "default";
 301 +       pinctrl-0 = <&pinctrl_wdog>;
 302 +       fsl,ext-reset-output;
 303 +};
 304 +
 305 +&iomuxc {
 306 +       pinctrl_enet: enetgrp {
 307 +               fsl,pins = <
 308 +                       MX6QDL_PAD_RGMII_RXC__RGMII_RXC         0x1b030
 309 +                       MX6QDL_PAD_RGMII_RD0__RGMII_RD0         0x1b030
 310 +                       MX6QDL_PAD_RGMII_RD1__RGMII_RD1         0x1b030
 311 +                       MX6QDL_PAD_RGMII_RD2__RGMII_RD2         0x1b030
 312 +                       MX6QDL_PAD_RGMII_RD3__RGMII_RD3         0x1b030
 313 +                       MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL   0x1b030
 314 +                       MX6QDL_PAD_RGMII_TXC__RGMII_TXC         0x1b030
 315 +                       MX6QDL_PAD_RGMII_TD0__RGMII_TD0         0x1b030
 316 +                       MX6QDL_PAD_RGMII_TD1__RGMII_TD1         0x1b030
 317 +                       MX6QDL_PAD_RGMII_TD2__RGMII_TD2         0x1b030
 318 +                       MX6QDL_PAD_RGMII_TD3__RGMII_TD3         0x1b030
 319 +                       MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL   0x1b030
 320 +                       MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK    0x1b0b0
 321 +                       MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x1b0b0
 322 +                       MX6QDL_PAD_ENET_MDC__ENET_MDC           0x1b0b0
 323 +                       MX6QDL_PAD_GPIO_16__ENET_REF_CLK        0x4001b0a8
 324 +                       MX6QDL_PAD_ENET_TXD0__GPIO1_IO30        0x1b0b0
 325 +               >;
 326 +       };
 327 +
 328 +       pinctrl_gpio_leds: gpioledsgrp {
 329 +               fsl,pins = <
 330 +                       MX6QDL_PAD_KEY_COL0__GPIO4_IO06         0x1b0b0
 331 +                       MX6QDL_PAD_KEY_ROW0__GPIO4_IO07         0x1b0b0
 332 +               >;
 333 +       };
 334 +
 335 +       pinctrl_gpmi_nand: gpminandgrp {
 336 +               fsl,pins = <
 337 +                       MX6QDL_PAD_NANDF_CLE__NAND_CLE          0xb0b1
 338 +                       MX6QDL_PAD_NANDF_ALE__NAND_ALE          0xb0b1
 339 +                       MX6QDL_PAD_NANDF_WP_B__NAND_WP_B        0xb0b1
 340 +                       MX6QDL_PAD_NANDF_RB0__NAND_READY_B      0xb000
 341 +                       MX6QDL_PAD_NANDF_CS0__NAND_CE0_B        0xb0b1
 342 +                       MX6QDL_PAD_SD4_CMD__NAND_RE_B           0xb0b1
 343 +                       MX6QDL_PAD_SD4_CLK__NAND_WE_B           0xb0b1
 344 +                       MX6QDL_PAD_NANDF_D0__NAND_DATA00        0xb0b1
 345 +                       MX6QDL_PAD_NANDF_D1__NAND_DATA01        0xb0b1
 346 +                       MX6QDL_PAD_NANDF_D2__NAND_DATA02        0xb0b1
 347 +                       MX6QDL_PAD_NANDF_D3__NAND_DATA03        0xb0b1
 348 +                       MX6QDL_PAD_NANDF_D4__NAND_DATA04        0xb0b1
 349 +                       MX6QDL_PAD_NANDF_D5__NAND_DATA05        0xb0b1
 350 +                       MX6QDL_PAD_NANDF_D6__NAND_DATA06        0xb0b1
 351 +                       MX6QDL_PAD_NANDF_D7__NAND_DATA07        0xb0b1
 352 +               >;
 353 +       };
 354 +
 355 +       pinctrl_i2c1: i2c1grp {
 356 +               fsl,pins = <
 357 +                       MX6QDL_PAD_EIM_D21__I2C1_SCL            0x4001b8b1
 358 +                       MX6QDL_PAD_EIM_D28__I2C1_SDA            0x4001b8b1
 359 +                       MX6QDL_PAD_GPIO_4__GPIO1_IO04           0x0001b0b0
 360 +               >;
 361 +       };
 362 +
 363 +       pinctrl_i2c2: i2c2grp {
 364 +               fsl,pins = <
 365 +                       MX6QDL_PAD_KEY_COL3__I2C2_SCL           0x4001b8b1
 366 +                       MX6QDL_PAD_KEY_ROW3__I2C2_SDA           0x4001b8b1
 367 +               >;
 368 +       };
 369 +
 370 +       pinctrl_i2c3: i2c3grp {
 371 +               fsl,pins = <
 372 +                       MX6QDL_PAD_GPIO_3__I2C3_SCL             0x4001b8b1
 373 +                       MX6QDL_PAD_GPIO_6__I2C3_SDA             0x4001b8b1
 374 +               >;
 375 +       };
 376 +
 377 +       pinctrl_pcie: pciegrp {
 378 +               fsl,pins = <
 379 +                       MX6QDL_PAD_GPIO_0__GPIO1_IO00           0x1b0b0
 380 +               >;
 381 +       };
 382 +
 383 +       pinctrl_pps: ppsgrp {
 384 +               fsl,pins = <
 385 +                       MX6QDL_PAD_SD3_DAT5__GPIO7_IO00         0x1b0b1
 386 +               >;
 387 +       };
 388 +
 389 +       pinctrl_pwm2: pwm2grp {
 390 +               fsl,pins = <
 391 +                       MX6QDL_PAD_SD1_DAT2__PWM2_OUT           0x1b0b1
 392 +               >;
 393 +       };
 394 +
 395 +       pinctrl_pwm3: pwm3grp {
 396 +               fsl,pins = <
 397 +                       MX6QDL_PAD_SD1_DAT1__PWM3_OUT           0x1b0b1
 398 +               >;
 399 +       };
 400 +
 401 +       pinctrl_pwm4: pwm4grp {
 402 +               fsl,pins = <
 403 +                       MX6QDL_PAD_SD1_CMD__PWM4_OUT            0x1b0b1
 404 +               >;
 405 +       };
 406 +
 407 +       pinctrl_uart1: uart1grp {
 408 +               fsl,pins = <
 409 +                       MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA      0x1b0b1
 410 +                       MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA      0x1b0b1
 411 +               >;
 412 +       };
 413 +
 414 +       pinctrl_uart2: uart2grp {
 415 +               fsl,pins = <
 416 +                       MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA      0x1b0b1
 417 +                       MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA      0x1b0b1
 418 +               >;
 419 +       };
 420 +
 421 +       pinctrl_uart3: uart3grp {
 422 +               fsl,pins = <
 423 +                       MX6QDL_PAD_EIM_D24__UART3_TX_DATA       0x1b0b1
 424 +                       MX6QDL_PAD_EIM_D25__UART3_RX_DATA       0x1b0b1
 425 +               >;
 426 +       };
 427 +
 428 +       pinctrl_uart5: uart5grp {
 429 +               fsl,pins = <
 430 +                       MX6QDL_PAD_KEY_COL1__UART5_TX_DATA      0x1b0b1
 431 +                       MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA      0x1b0b1
 432 +               >;
 433 +       };
 434 +
 435 +       pinctrl_usbotg: usbotggrp {
 436 +               fsl,pins = <
 437 +                       MX6QDL_PAD_GPIO_1__USB_OTG_ID           0x17059
 438 +               >;
 439 +       };
 440 +
 441 +       pinctrl_wdog: wdoggrp {
 442 +               fsl,pins = <
 443 +                       MX6QDL_PAD_DISP0_DAT8__WDOG1_B          0x1b0b0
 444 +               >;
 445 +       };
 446 +};
 447 --
 448 2.7.4
 449