target/linux/imx6/patches-4.19/004-ARM-dts-imx-Add-GW5912-board-support.patch

   1 From 9a820b55817011f53771e6bfebae5fe059f0a534 Mon Sep 17 00:00:00 2001
   2 From: Robert Jones <rjones@gateworks.com>
   3 Date: Wed, 8 Jan 2020 07:44:24 -0800
   4 Subject: [PATCH 4/4] ARM: dts: imx: Add GW5912 board support
   5
   6 The Gateworks GW5912 is an IMX6 SoC based single board computer with:
   7  - IMX6Q or IMX6DL
   8  - 32bit DDR3 DRAM
   9  - GbE RJ45 front-panel
  10  - 4x miniPCIe socket with PCI Gen2, USB2
  11  - 1x miniPCIe socket with PCI Gen2, USB2, mSATA
  12  - 1x miniPCIe socket with PCI Gen2, USB2, mezzanine
  13  - 10V to 60V DC input barrel jack
  14  - 3axis accelerometer (lis2de12)
  15  - GPS (ublox ZOE-M8Q)
  16  - bi-color front-panel LED
  17  - 256MB NAND boot device
  18  - nanoSIM/microSD socket (with UHS-I support)
  19  - user pushbutton
  20  - Gateworks System Controller (hwmon, pushbutton controller, EEPROM)
  21  - CAN Bus transceiver (mcp2562)
  22  - RS232 transceiver (1x UART with flow-control or 2x UART (build option)
  23  - off-board SPI connector (1x chip-select)
  24
  25 Signed-off-by: Robert Jones <rjones@gateworks.com>
  26 Reviewed-by: Tim Harvey <tharvey@gateworks.com>
  27 Signed-off-by: Shawn Guo <shawnguo@kernel.org>
  28 ---
  29  arch/arm/boot/dts/Makefile            |   2 +
  30  arch/arm/boot/dts/imx6dl-gw5912.dts   |  13 +
  31  arch/arm/boot/dts/imx6q-gw5912.dts    |  13 +
  32  arch/arm/boot/dts/imx6qdl-gw5912.dtsi | 461 ++++++++++++++++++++++++++++++++++
  33  4 files changed, 489 insertions(+)
  34  create mode 100644 arch/arm/boot/dts/imx6dl-gw5912.dts
  35  create mode 100644 arch/arm/boot/dts/imx6q-gw5912.dts
  36  create mode 100644 arch/arm/boot/dts/imx6qdl-gw5912.dtsi
  37
  38 diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
  39 index 5b059fc..1a32a7d 100644
  40 --- a/arch/arm/boot/dts/Makefile
  41 +++ b/arch/arm/boot/dts/Makefile
  42 @@ -424,6 +424,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
  43         imx6dl-gw5904.dtb \
  44         imx6dl-gw5907.dtb \
  45         imx6dl-gw5910.dtb \
  46 +       imx6dl-gw5912.dtb \
  47         imx6dl-gw5913.dtb \
  48         imx6dl-hummingboard.dtb \
  49         imx6dl-hummingboard-emmc-som-v15.dtb \
  50 @@ -498,6 +499,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
  51         imx6q-gw5904.dtb \
  52         imx6q-gw5907.dtb \
  53         imx6q-gw5910.dtb \
  54 +       imx6q-gw5912.dtb \
  55         imx6q-gw5913.dtb \
  56         imx6q-h100.dtb \
  57         imx6q-hummingboard.dtb \
  58 diff --git a/arch/arm/boot/dts/imx6dl-gw5912.dts b/arch/arm/boot/dts/imx6dl-gw5912.dts
  59 new file mode 100644
  60 index 00000000..5260e01
  61 --- /dev/null
  62 +++ b/arch/arm/boot/dts/imx6dl-gw5912.dts
  63 @@ -0,0 +1,13 @@
  64 +// SPDX-License-Identifier: GPL-2.0
  65 +/*
  66 + * Copyright 2019 Gateworks Corporation
  67 + */
  68 +
  69 +/dts-v1/;
  70 +#include "imx6dl.dtsi"
  71 +#include "imx6qdl-gw5912.dtsi"
  72 +
  73 +/ {
  74 +       model = "Gateworks Ventana i.MX6 DualLite/Solo GW5912";
  75 +       compatible = "gw,imx6dl-gw5912", "gw,ventana", "fsl,imx6dl";
  76 +};
  77 diff --git a/arch/arm/boot/dts/imx6q-gw5912.dts b/arch/arm/boot/dts/imx6q-gw5912.dts
  78 new file mode 100644
  79 index 00000000..4dcbd94
  80 --- /dev/null
  81 +++ b/arch/arm/boot/dts/imx6q-gw5912.dts
  82 @@ -0,0 +1,13 @@
  83 +// SPDX-License-Identifier: GPL-2.0
  84 +/*
  85 + * Copyright 2019 Gateworks Corporation
  86 + */
  87 +
  88 +/dts-v1/;
  89 +#include "imx6q.dtsi"
  90 +#include "imx6qdl-gw5912.dtsi"
  91 +
  92 +/ {
  93 +       model = "Gateworks Ventana i.MX6 Dual/Quad GW5912";
  94 +       compatible = "gw,imx6q-gw5912", "gw,ventana", "fsl,imx6q";
  95 +};
  96 diff --git a/arch/arm/boot/dts/imx6qdl-gw5912.dtsi b/arch/arm/boot/dts/imx6qdl-gw5912.dtsi
  97 new file mode 100644
  98 index 00000000..8c57fd2
  99 --- /dev/null
 100 +++ b/arch/arm/boot/dts/imx6qdl-gw5912.dtsi
 101 @@ -0,0 +1,461 @@
 102 +// SPDX-License-Identifier: GPL-2.0
 103 +/*
 104 + * Copyright 2019 Gateworks Corporation
 105 + */
 106 +
 107 +#include <dt-bindings/gpio/gpio.h>
 108 +
 109 +/ {
 110 +       /* these are used by bootloader for disabling nodes */
 111 +       aliases {
 112 +               led0 = &led0;
 113 +               led1 = &led1;
 114 +               led2 = &led2;
 115 +               nand = &gpmi;
 116 +               usb0 = &usbh1;
 117 +               usb1 = &usbotg;
 118 +       };
 119 +
 120 +       chosen {
 121 +               stdout-path = &uart2;
 122 +       };
 123 +
 124 +       leds {
 125 +               compatible = "gpio-leds";
 126 +               pinctrl-names = "default";
 127 +               pinctrl-0 = <&pinctrl_gpio_leds>;
 128 +
 129 +               led0: user1 {
 130 +                       label = "user1";
 131 +                       gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
 132 +                       default-state = "on";
 133 +                       linux,default-trigger = "heartbeat";
 134 +               };
 135 +
 136 +               led1: user2 {
 137 +                       label = "user2";
 138 +                       gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
 139 +                       default-state = "off";
 140 +               };
 141 +
 142 +               led2: user3 {
 143 +                       label = "user3";
 144 +                       gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */
 145 +                       default-state = "off";
 146 +               };
 147 +       };
 148 +
 149 +       memory@10000000 {
 150 +               device_type = "memory";
 151 +               reg = <0x10000000 0x40000000>;
 152 +       };
 153 +
 154 +       pps {
 155 +               compatible = "pps-gpio";
 156 +               pinctrl-names = "default";
 157 +               pinctrl-0 = <&pinctrl_pps>;
 158 +               gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
 159 +       };
 160 +
 161 +       reg_3p3v: regulator-3p3v {
 162 +               compatible = "regulator-fixed";
 163 +               regulator-name = "3P3V";
 164 +               regulator-min-microvolt = <3300000>;
 165 +               regulator-max-microvolt = <3300000>;
 166 +               regulator-always-on;
 167 +       };
 168 +
 169 +       reg_usb_vbus: regulator-5p0v {
 170 +               compatible = "regulator-fixed";
 171 +               regulator-name = "usb_vbus";
 172 +               regulator-min-microvolt = <5000000>;
 173 +               regulator-max-microvolt = <5000000>;
 174 +               regulator-always-on;
 175 +       };
 176 +};
 177 +
 178 +&can1 {
 179 +       pinctrl-names = "default";
 180 +       pinctrl-0 = <&pinctrl_flexcan1>;
 181 +       status = "okay";
 182 +};
 183 +
 184 +&ecspi2 {
 185 +       cs-gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>;
 186 +       pinctrl-names = "default";
 187 +       pinctrl-0 = <&pinctrl_ecspi2>;
 188 +       status = "okay";
 189 +};
 190 +
 191 +&fec {
 192 +       pinctrl-names = "default";
 193 +       pinctrl-0 = <&pinctrl_enet>;
 194 +       phy-mode = "rgmii-id";
 195 +       status = "okay";
 196 +};
 197 +
 198 +&gpmi {
 199 +       pinctrl-names = "default";
 200 +       pinctrl-0 = <&pinctrl_gpmi_nand>;
 201 +       status = "okay";
 202 +};
 203 +
 204 +&i2c1 {
 205 +       clock-frequency = <100000>;
 206 +       pinctrl-names = "default";
 207 +       pinctrl-0 = <&pinctrl_i2c1>;
 208 +       status = "okay";
 209 +
 210 +       gpio@23 {
 211 +               compatible = "nxp,pca9555";
 212 +               reg = <0x23>;
 213 +               gpio-controller;
 214 +               #gpio-cells = <2>;
 215 +       };
 216 +
 217 +       eeprom@50 {
 218 +               compatible = "atmel,24c02";
 219 +               reg = <0x50>;
 220 +               pagesize = <16>;
 221 +       };
 222 +
 223 +       eeprom@51 {
 224 +               compatible = "atmel,24c02";
 225 +               reg = <0x51>;
 226 +               pagesize = <16>;
 227 +       };
 228 +
 229 +       eeprom@52 {
 230 +               compatible = "atmel,24c02";
 231 +               reg = <0x52>;
 232 +               pagesize = <16>;
 233 +       };
 234 +
 235 +       eeprom@53 {
 236 +               compatible = "atmel,24c02";
 237 +               reg = <0x53>;
 238 +               pagesize = <16>;
 239 +       };
 240 +
 241 +       rtc@68 {
 242 +               compatible = "dallas,ds1672";
 243 +               reg = <0x68>;
 244 +       };
 245 +};
 246 +
 247 +&i2c2 {
 248 +       clock-frequency = <100000>;
 249 +       pinctrl-names = "default";
 250 +       pinctrl-0 = <&pinctrl_i2c2>;
 251 +       status = "okay";
 252 +};
 253 +
 254 +&i2c3 {
 255 +       clock-frequency = <100000>;
 256 +       pinctrl-names = "default";
 257 +       pinctrl-0 = <&pinctrl_i2c3>;
 258 +       status = "okay";
 259 +
 260 +       accel@19 {
 261 +               pinctrl-names = "default";
 262 +               pinctrl-0 = <&pinctrl_accel>;
 263 +               compatible = "st,lis2de12";
 264 +               reg = <0x19>;
 265 +               st,drdy-int-pin = <1>;
 266 +               interrupt-parent = <&gpio7>;
 267 +               interrupts = <13 0>;
 268 +               interrupt-names = "INT1";
 269 +       };
 270 +};
 271 +
 272 +&pcie {
 273 +       pinctrl-names = "default";
 274 +       pinctrl-0 = <&pinctrl_pcie>;
 275 +       reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>;
 276 +       status = "okay";
 277 +};
 278 +
 279 +&pwm1 {
 280 +       pinctrl-names = "default";
 281 +       pinctrl-0 = <&pinctrl_pwm1>; /* MX6_DIO0 */
 282 +       status = "disabled";
 283 +};
 284 +
 285 +&pwm2 {
 286 +       pinctrl-names = "default";
 287 +       pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
 288 +       status = "disabled";
 289 +};
 290 +
 291 +&pwm3 {
 292 +       pinctrl-names = "default";
 293 +       pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
 294 +       status = "disabled";
 295 +};
 296 +
 297 +&pwm4 {
 298 +       pinctrl-names = "default";
 299 +       pinctrl-0 = <&pinctrl_pwm4>; /* MX6_DIO3 */
 300 +       status = "disabled";
 301 +};
 302 +
 303 +&uart1 {
 304 +       pinctrl-names = "default";
 305 +       pinctrl-0 = <&pinctrl_uart1>;
 306 +       rts-gpios = <&gpio7 12 GPIO_ACTIVE_HIGH>;
 307 +       status = "okay";
 308 +};
 309 +
 310 +&uart2 {
 311 +       pinctrl-names = "default";
 312 +       pinctrl-0 = <&pinctrl_uart2>;
 313 +       status = "okay";
 314 +};
 315 +
 316 +&uart5 {
 317 +       pinctrl-names = "default";
 318 +       pinctrl-0 = <&pinctrl_uart5>;
 319 +       status = "okay";
 320 +};
 321 +
 322 +&usbotg {
 323 +       vbus-supply = <&reg_usb_vbus>;
 324 +       pinctrl-names = "default";
 325 +       pinctrl-0 = <&pinctrl_usbotg>;
 326 +       disable-over-current;
 327 +       dr_mode = "host";
 328 +       status = "okay";
 329 +};
 330 +
 331 +&usbh1 {
 332 +       vbus-supply = <&reg_usb_vbus>;
 333 +       status = "okay";
 334 +};
 335 +
 336 +&usdhc3 {
 337 +       pinctrl-names = "default", "state_100mhz", "state_200mhz";
 338 +       pinctrl-0 = <&pinctrl_usdhc3>;
 339 +       pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
 340 +       pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
 341 +       cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
 342 +       vmmc-supply = <&reg_3p3v>;
 343 +       no-1-8-v; /* firmware will remove if board revision supports */
 344 +       status = "okay";
 345 +};
 346 +
 347 +&wdog1 {
 348 +       status = "disabled";
 349 +};
 350 +
 351 +&wdog2 {
 352 +       pinctrl-names = "default";
 353 +       pinctrl-0 = <&pinctrl_wdog>;
 354 +       fsl,ext-reset-output;
 355 +       status = "okay";
 356 +};
 357 +
 358 +&iomuxc {
 359 +       pinctrl_accel: accelmuxgrp {
 360 +               fsl,pins = <
 361 +                       MX6QDL_PAD_GPIO_18__GPIO7_IO13          0x1b0b1
 362 +               >;
 363 +       };
 364 +
 365 +       pinctrl_enet: enetgrp {
 366 +               fsl,pins = <
 367 +                       MX6QDL_PAD_RGMII_RXC__RGMII_RXC         0x1b030
 368 +                       MX6QDL_PAD_RGMII_RD0__RGMII_RD0         0x1b030
 369 +                       MX6QDL_PAD_RGMII_RD1__RGMII_RD1         0x1b030
 370 +                       MX6QDL_PAD_RGMII_RD2__RGMII_RD2         0x1b030
 371 +                       MX6QDL_PAD_RGMII_RD3__RGMII_RD3         0x1b030
 372 +                       MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL   0x1b030
 373 +                       MX6QDL_PAD_RGMII_TXC__RGMII_TXC         0x1b030
 374 +                       MX6QDL_PAD_RGMII_TD0__RGMII_TD0         0x1b030
 375 +                       MX6QDL_PAD_RGMII_TD1__RGMII_TD1         0x1b030
 376 +                       MX6QDL_PAD_RGMII_TD2__RGMII_TD2         0x1b030
 377 +                       MX6QDL_PAD_RGMII_TD3__RGMII_TD3         0x1b030
 378 +                       MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL   0x1b030
 379 +                       MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK    0x1b0b0
 380 +                       MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x1b0b0
 381 +                       MX6QDL_PAD_ENET_MDC__ENET_MDC           0x1b0b0
 382 +               >;
 383 +       };
 384 +
 385 +       pinctrl_ecspi2: escpi2grp {
 386 +               fsl,pins = <
 387 +                       MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1
 388 +                       MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1
 389 +                       MX6QDL_PAD_EIM_OE__ECSPI2_MISO  0x100b1
 390 +                       MX6QDL_PAD_EIM_RW__GPIO2_IO26   0x100b1
 391 +               >;
 392 +       };
 393 +
 394 +       pinctrl_flexcan1: flexcan1grp {
 395 +               fsl,pins = <
 396 +                       MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX        0x1b0b1
 397 +                       MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX        0x1b0b1
 398 +                       MX6QDL_PAD_GPIO_2__GPIO1_IO02           0x4001b0b0
 399 +               >;
 400 +       };
 401 +
 402 +       pinctrl_gpio_leds: gpioledsgrp {
 403 +               fsl,pins = <
 404 +                       MX6QDL_PAD_KEY_COL0__GPIO4_IO06         0x1b0b0
 405 +                       MX6QDL_PAD_KEY_ROW0__GPIO4_IO07         0x1b0b0
 406 +                       MX6QDL_PAD_KEY_ROW4__GPIO4_IO15         0x1b0b0
 407 +               >;
 408 +       };
 409 +
 410 +       pinctrl_gpmi_nand: gpminandgrp {
 411 +               fsl,pins = <
 412 +                       MX6QDL_PAD_NANDF_CLE__NAND_CLE          0xb0b1
 413 +                       MX6QDL_PAD_NANDF_ALE__NAND_ALE          0xb0b1
 414 +                       MX6QDL_PAD_NANDF_WP_B__NAND_WP_B        0xb0b1
 415 +                       MX6QDL_PAD_NANDF_RB0__NAND_READY_B      0xb000
 416 +                       MX6QDL_PAD_NANDF_CS0__NAND_CE0_B        0xb0b1
 417 +                       MX6QDL_PAD_SD4_CMD__NAND_RE_B           0xb0b1
 418 +                       MX6QDL_PAD_SD4_CLK__NAND_WE_B           0xb0b1
 419 +                       MX6QDL_PAD_NANDF_D0__NAND_DATA00        0xb0b1
 420 +                       MX6QDL_PAD_NANDF_D1__NAND_DATA01        0xb0b1
 421 +                       MX6QDL_PAD_NANDF_D2__NAND_DATA02        0xb0b1
 422 +                       MX6QDL_PAD_NANDF_D3__NAND_DATA03        0xb0b1
 423 +                       MX6QDL_PAD_NANDF_D4__NAND_DATA04        0xb0b1
 424 +                       MX6QDL_PAD_NANDF_D5__NAND_DATA05        0xb0b1
 425 +                       MX6QDL_PAD_NANDF_D6__NAND_DATA06        0xb0b1
 426 +                       MX6QDL_PAD_NANDF_D7__NAND_DATA07        0xb0b1
 427 +               >;
 428 +       };
 429 +
 430 +       pinctrl_i2c1: i2c1grp {
 431 +               fsl,pins = <
 432 +                       MX6QDL_PAD_EIM_D21__I2C1_SCL            0x4001b8b1
 433 +                       MX6QDL_PAD_EIM_D28__I2C1_SDA            0x4001b8b1
 434 +                       MX6QDL_PAD_GPIO_4__GPIO1_IO04           0x0001b0b0
 435 +               >;
 436 +       };
 437 +
 438 +       pinctrl_i2c2: i2c2grp {
 439 +               fsl,pins = <
 440 +                       MX6QDL_PAD_KEY_COL3__I2C2_SCL           0x4001b8b1
 441 +                       MX6QDL_PAD_KEY_ROW3__I2C2_SDA           0x4001b8b1
 442 +               >;
 443 +       };
 444 +
 445 +       pinctrl_i2c3: i2c3grp {
 446 +               fsl,pins = <
 447 +                       MX6QDL_PAD_GPIO_3__I2C3_SCL             0x4001b8b1
 448 +                       MX6QDL_PAD_GPIO_6__I2C3_SDA             0x4001b8b1
 449 +               >;
 450 +       };
 451 +
 452 +       pinctrl_pcie: pciegrp {
 453 +               fsl,pins = <
 454 +                       MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28       0x1b0b0
 455 +                       MX6QDL_PAD_ENET_TXD1__GPIO1_IO29        0x1b0b0
 456 +               >;
 457 +       };
 458 +
 459 +       pinctrl_pps: ppsgrp {
 460 +               fsl,pins = <
 461 +                       MX6QDL_PAD_GPIO_5__GPIO1_IO05           0x1b0b1
 462 +               >;
 463 +       };
 464 +
 465 +       pinctrl_pwm1: pwm1grp {
 466 +               fsl,pins = <
 467 +                       MX6QDL_PAD_GPIO_9__PWM1_OUT             0x1b0b1
 468 +               >;
 469 +       };
 470 +
 471 +       pinctrl_pwm2: pwm2grp {
 472 +               fsl,pins = <
 473 +                       MX6QDL_PAD_SD1_DAT2__PWM2_OUT           0x1b0b1
 474 +               >;
 475 +       };
 476 +
 477 +       pinctrl_pwm3: pwm3grp {
 478 +               fsl,pins = <
 479 +                       MX6QDL_PAD_SD4_DAT1__PWM3_OUT           0x1b0b1
 480 +               >;
 481 +       };
 482 +
 483 +       pinctrl_pwm4: pwm4grp {
 484 +               fsl,pins = <
 485 +                       MX6QDL_PAD_SD4_DAT2__PWM4_OUT           0x1b0b1
 486 +               >;
 487 +       };
 488 +
 489 +       pinctrl_uart1: uart1grp {
 490 +               fsl,pins = <
 491 +                       MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA      0x1b0b1
 492 +                       MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA      0x1b0b1
 493 +                       MX6QDL_PAD_GPIO_17__GPIO7_IO12          0x4001b0b1
 494 +               >;
 495 +       };
 496 +
 497 +       pinctrl_uart2: uart2grp {
 498 +               fsl,pins = <
 499 +                       MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA      0x1b0b1
 500 +                       MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA      0x1b0b1
 501 +                       MX6QDL_PAD_SD4_DAT3__GPIO2_IO11         0x4001b0b1
 502 +               >;
 503 +       };
 504 +
 505 +       pinctrl_uart5: uart5grp {
 506 +               fsl,pins = <
 507 +                       MX6QDL_PAD_KEY_COL1__UART5_TX_DATA      0x1b0b1
 508 +                       MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA      0x1b0b1
 509 +               >;
 510 +       };
 511 +
 512 +       pinctrl_usbotg: usbotggrp {
 513 +               fsl,pins = <
 514 +                       MX6QDL_PAD_GPIO_1__USB_OTG_ID           0x13059
 515 +               >;
 516 +       };
 517 +
 518 +       pinctrl_usdhc3: usdhc3grp {
 519 +               fsl,pins = <
 520 +                       MX6QDL_PAD_SD3_CMD__SD3_CMD             0x17059
 521 +                       MX6QDL_PAD_SD3_CLK__SD3_CLK             0x10059
 522 +                       MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x17059
 523 +                       MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x17059
 524 +                       MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x17059
 525 +                       MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x17059
 526 +                       MX6QDL_PAD_SD3_DAT5__GPIO7_IO00         0x17059 /* CD */
 527 +                       MX6QDL_PAD_NANDF_CS1__SD3_VSELECT       0x17059
 528 +               >;
 529 +       };
 530 +
 531 +       pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
 532 +               fsl,pins = <
 533 +                       MX6QDL_PAD_SD3_CMD__SD3_CMD             0x170b9
 534 +                       MX6QDL_PAD_SD3_CLK__SD3_CLK             0x100b9
 535 +                       MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x170b9
 536 +                       MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x170b9
 537 +                       MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x170b9
 538 +                       MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x170b9
 539 +                       MX6QDL_PAD_SD3_DAT5__GPIO7_IO00         0x170b9 /* CD */
 540 +                       MX6QDL_PAD_NANDF_CS1__SD3_VSELECT       0x170b9
 541 +               >;
 542 +       };
 543 +
 544 +       pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
 545 +               fsl,pins = <
 546 +                       MX6QDL_PAD_SD3_CMD__SD3_CMD             0x170f9
 547 +                       MX6QDL_PAD_SD3_CLK__SD3_CLK             0x100f9
 548 +                       MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x170f9
 549 +                       MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x170f9
 550 +                       MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x170f9
 551 +                       MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x170f9
 552 +                       MX6QDL_PAD_SD3_DAT5__GPIO7_IO00         0x170f9 /* CD */
 553 +                       MX6QDL_PAD_NANDF_CS1__SD3_VSELECT       0x170f9
 554 +               >;
 555 +       };
 556 +
 557 +       pinctrl_wdog: wdoggrp {
 558 +               fsl,pins = <
 559 +                       MX6QDL_PAD_SD1_DAT3__WDOG2_B            0x1b0b0
 560 +               >;
 561 +       };
 562 +};
 563 --
 564 2.7.4
 565