1 --- a/arch/arm/boot/dts/imx6dl.dtsi
2 +++ b/arch/arm/boot/dts/imx6dl.dtsi
8 + pinctrl_gpmi_nand_1: gpmi-nand-1 {
10 + MX6DL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
11 + MX6DL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
12 + MX6DL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
13 + MX6DL_PAD_NANDF_RB0__NAND_READY_B 0xb000
14 + MX6DL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
15 + MX6DL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
16 + MX6DL_PAD_NANDF_CS2__NAND_CE2_B 0xb0b1
17 + MX6DL_PAD_NANDF_CS3__NAND_CE3_B 0xb0b1
18 + MX6DL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
19 + MX6DL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
20 + MX6DL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
21 + MX6DL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
22 + MX6DL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
23 + MX6DL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
24 + MX6DL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
25 + MX6DL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
26 + MX6DL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
27 + MX6DL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
28 + MX6DL_PAD_SD4_DAT0__NAND_DQS 0x00b1
33 + pinctrl_gpmi_nand_2: gpmi-nand-2 {
35 + MX6DL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
36 + MX6DL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
37 + MX6DL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
38 + MX6DL_PAD_NANDF_RB0__NAND_READY_B 0xb000
39 + MX6DL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
40 + MX6DL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
41 + MX6DL_PAD_NANDF_CS2__NAND_CE2_B 0xb0b1
42 + MX6DL_PAD_NANDF_CS3__NAND_CE3_B 0xb0b1
43 + MX6DL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
44 + MX6DL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
45 + MX6DL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
46 + MX6DL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
47 + MX6DL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
48 + MX6DL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
49 + MX6DL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
50 + MX6DL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
51 + MX6DL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
52 + MX6DL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
58 + pinctrl_i2c1_1: i2c1grp-1 {
60 + MX6DL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
61 + MX6DL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
67 + pinctrl_i2c2_1: i2c2grp-1 {
69 + MX6DL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
70 + MX6DL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1
73 + pinctrl_i2c2_2: i2c2grp-2 {
75 + MX6DL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
76 + MX6DL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
82 + pinctrl_i2c3_1: i2c3grp-1 {
84 + MX6DL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1
85 + MX6DL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
88 + pinctrl_i2c3_2: i2c3grp-2 {
90 + MX6DL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
91 + MX6DL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
97 pinctrl_uart1_1: uart1grp-1 {
100 MX6DL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
103 + pinctrl_uart1_2: uart1grp-2 {
105 + MX6DL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
106 + MX6DL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
112 + pinctrl_uart2_1: uart2grp-1 {
114 + MX6DL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
115 + MX6DL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
118 + pinctrl_uart2_2: uart2grp-2 {
120 + MX6DL_PAD_SD4_DAT7__UART2_RX_DATA 0x1b0b1
121 + MX6DL_PAD_SD4_DAT4__UART2_TX_DATA 0x1b0b1
127 + pinctrl_uart3_1: uart3grp-1 {
129 + MX6DL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
130 + MX6DL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
142 + pinctrl_uart5_1: uart5grp-1 {
144 + MX6DL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
145 + MX6DL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
151 pinctrl_usbotg_2: usbotggrp-2 {
152 --- a/arch/arm/boot/dts/Makefile
153 +++ b/arch/arm/boot/dts/Makefile
154 @@ -119,6 +119,7 @@ dtb-$(CONFIG_ARCH_MXC) += \
158 + imx6dl-gw51xx.dtb \
159 imx6q-sabreauto.dtb \
160 imx6q-sabrelite.dtb \