1 --- a/arch/arm/boot/dts/Makefile
2 +++ b/arch/arm/boot/dts/Makefile
3 @@ -117,6 +117,7 @@ dtb-$(CONFIG_ARCH_MXC) += \
11 --- a/arch/arm/boot/dts/imx6q.dtsi
12 +++ b/arch/arm/boot/dts/imx6q.dtsi
14 MX6Q_PAD_CSI0_DAT6__AUD3_TXFS 0x80000000
18 + pinctrl_audmux_3: audmux-3 {
20 + MX6Q_PAD_DISP0_DAT19__AUD5_RXD 0x80000000
21 + MX6Q_PAD_EIM_D25__AUD5_RXC 0x80000000
22 + MX6Q_PAD_DISP0_DAT18__AUD5_TXFS 0x80000000
29 MX6Q_PAD_EIM_D16__I2C2_SDA 0x4001b8b1
32 + pinctrl_i2c2_2: i2c2grp-2 {
34 + MX6Q_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
35 + MX6Q_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
42 MX6Q_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
45 + pinctrl_i2c3_2: i2c3grp-2 {
47 + MX6Q_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
48 + MX6Q_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
55 MX6Q_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
58 + pinctrl_uart1_2: uart1grp-2 {
60 + MX6Q_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
61 + MX6Q_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
68 MX6Q_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
71 + pinctrl_uart2_2: uart2grp-2 {
73 + MX6Q_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
74 + MX6Q_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
80 + pinctrl_uart3_1: uart3grp-1 {
82 + MX6Q_PAD_SD4_CMD__UART3_TX_DATA 0x1b0b1
83 + MX6Q_PAD_SD4_CLK__UART3_RX_DATA 0x1b0b1
95 + pinctrl_uart5_1: uart5grp-1 {
97 + MX6Q_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
98 + MX6Q_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
104 pinctrl_usbotg_1: usbotggrp-1 {
105 --- a/arch/arm/mach-imx/mach-imx6q.c
106 +++ b/arch/arm/mach-imx/mach-imx6q.c
108 #include <linux/of_irq.h>
109 #include <linux/of_platform.h>
110 #include <linux/opp.h>
111 +#include <linux/pci.h>
112 #include <linux/phy.h>
113 #include <linux/regmap.h>
114 #include <linux/micrel_phy.h>
115 @@ -145,6 +146,65 @@ static void __init imx6q_sabrelite_init(
116 imx6q_sabrelite_cko1_setup();
120 + * fixup for PEX 8909 bridge to configure GPIO1-7 as output High
121 + * as they are used for slots1-7 PERST#
123 +static void mx6_ventana_pciesw_early_fixup(struct pci_dev *dev)
127 + if (!of_machine_is_compatible("gw,ventana"))
130 + if (dev->devfn != 0)
133 + pci_read_config_dword(dev, 0x62c, &dw);
134 + dw |= 0xaaa8; // GPIO1-7 outputs
135 + pci_write_config_dword(dev, 0x62c, dw);
137 + pci_read_config_dword(dev, 0x644, &dw);
138 + dw |= 0xfe; // GPIO1-7 output high
139 + pci_write_config_dword(dev, 0x644, dw);
141 +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8609,
142 + mx6_ventana_pciesw_early_fixup);
145 + * configure PCIe core clock and PCIe ref clock
147 + * TODO: disable CLK1 output and use CLK2 input from si52147 as PCIe ref
149 +static void __init imx6q_ventana_pcie_setup(void)
151 + struct clk *axi_sel, *axi, *ref;
153 + axi_sel = clk_get_sys(NULL, "pcie_axi_sel");
154 + axi = clk_get_sys(NULL, "axi");
155 + ref = clk_get_sys(NULL, "pcie_ref_125m");
156 + if (IS_ERR(axi_sel) || IS_ERR(axi) || IS_ERR(ref)) {
157 + pr_err("pcie setup failed - can't get clocks\n");
160 + clk_set_parent(axi_sel, axi);
161 + clk_prepare_enable(ref);
164 + if (!IS_ERR(axi_sel))
172 +static void __init imx6q_ventana_init(void)
174 + imx6q_ventana_pcie_setup();
175 + imx6q_sabrelite_cko1_setup();
178 static void __init imx6q_1588_init(void)
181 @@ -163,6 +223,9 @@ static void __init imx6q_usb_init(void)
183 static void __init imx6q_init_machine(void)
185 + if (of_machine_is_compatible("gw,ventana"))
186 + imx6q_ventana_init();
188 if (of_machine_is_compatible("fsl,imx6q-sabrelite"))
189 imx6q_sabrelite_init();