2 * Synopsys Designware PCIe host controller driver
4 * Copyright (C) 2013 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
7 * Author: Jingoo Han <jg1.han@samsung.com>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 struct pcie_port_info {
19 phys_addr_t io_bus_addr;
20 phys_addr_t mem_bus_addr;
26 void __iomem *dbi_base;
28 void __iomem *va_cfg0_base;
30 void __iomem *va_cfg1_base;
37 struct pcie_port_info config;
40 struct pcie_host_ops *ops;
43 struct pcie_host_ops {
44 void (*readl_rc)(struct pcie_port *pp,
45 void __iomem *dbi_base, u32 *val);
46 void (*writel_rc)(struct pcie_port *pp,
47 u32 val, void __iomem *dbi_base);
48 int (*rd_own_conf)(struct pcie_port *pp, int where, int size, u32 *val);
49 int (*wr_own_conf)(struct pcie_port *pp, int where, int size, u32 val);
50 int (*link_up)(struct pcie_port *pp);
51 void (*host_init)(struct pcie_port *pp);
54 extern unsigned long global_io_offset;
56 int cfg_read(void __iomem *addr, int where, int size, u32 *val);
57 int cfg_write(void __iomem *addr, int where, int size, u32 val);
58 int dw_pcie_wr_own_conf(struct pcie_port *pp, int where, int size, u32 val);
59 int dw_pcie_rd_own_conf(struct pcie_port *pp, int where, int size, u32 *val);
60 int dw_pcie_link_up(struct pcie_port *pp);
61 void dw_pcie_setup_rc(struct pcie_port *pp);
62 int dw_pcie_host_init(struct pcie_port *pp);
63 int dw_pcie_setup(int nr, struct pci_sys_data *sys);
64 struct pci_bus *dw_pcie_scan_bus(int nr, struct pci_sys_data *sys);
65 int dw_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin);