2 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 * Copyright (C) 2004 Infineon IFAP DC COM CPE
19 * Copyright (C) 2007 Felix Fietkau <nbd@openwrt.org>
20 * Copyright (C) 2007 John Crispin <blogic@openwrt.org>
23 #include <linux/module.h>
24 #include <linux/errno.h>
25 #include <linux/signal.h>
26 #include <linux/sched.h>
27 #include <linux/interrupt.h>
28 #include <linux/tty.h>
29 #include <linux/tty_flip.h>
30 #include <linux/major.h>
31 #include <linux/string.h>
32 #include <linux/fcntl.h>
33 #include <linux/ptrace.h>
34 #include <linux/ioport.h>
36 #include <linux/slab.h>
37 #include <linux/init.h>
38 #include <linux/circ_buf.h>
39 #include <linux/serial.h>
40 #include <linux/serial_core.h>
41 #include <linux/console.h>
42 #include <linux/sysrq.h>
43 #include <linux/irq.h>
44 #include <linux/platform_device.h>
45 #include <asm/system.h>
47 #include <asm/uaccess.h>
48 #include <asm/bitops.h>
49 #include <asm/ifxmips/ifxmips.h>
50 #include <asm/ifxmips/ifxmips_irq.h>
51 #include <asm/ifxmips/ifxmips_serial.h>
53 #define PORT_IFXMIPSASC 111
55 #include <linux/serial_core.h>
57 #define UART_DUMMY_UER_RX 1
59 static void ifxmipsasc_tx_chars(struct uart_port *port);
60 extern void prom_printf(const char * fmt, ...);
61 static struct uart_port ifxmipsasc_port[2];
62 static struct uart_driver ifxmipsasc_reg;
63 extern unsigned int ifxmips_get_fpi_hz(void);
66 ifxmipsasc_stop_tx(struct uart_port *port)
72 ifxmipsasc_start_tx(struct uart_port *port)
75 local_irq_save(flags);
76 ifxmipsasc_tx_chars(port);
77 local_irq_restore(flags);
82 ifxmipsasc_stop_rx(struct uart_port *port)
84 ifxmips_w32(ASCWHBSTATE_CLRREN, port->membase + IFXMIPS_ASC_WHBSTATE);
88 ifxmipsasc_enable_ms(struct uart_port *port)
93 ifxmipsasc_rx_chars(struct uart_port *port)
95 struct tty_struct *tty = port->info->tty;
96 unsigned int ch = 0, rsr = 0, fifocnt;
98 fifocnt = ifxmips_r32(port->membase + IFXMIPS_ASC_FSTAT) & ASCFSTAT_RXFFLMASK;
101 u8 flag = TTY_NORMAL;
102 ch = ifxmips_r32(port->membase + IFXMIPS_ASC_RBUF);
103 rsr = (ifxmips_r32(port->membase + IFXMIPS_ASC_STATE) & ASCSTATE_ANY) | UART_DUMMY_UER_RX;
104 tty_flip_buffer_push(tty);
108 * Note that the error handling code is
109 * out of the main execution path
111 if(rsr & ASCSTATE_ANY)
113 if(rsr & ASCSTATE_PE)
115 port->icount.parity++;
116 ifxmips_w32(ifxmips_r32(port->membase + IFXMIPS_ASC_WHBSTATE) | ASCWHBSTATE_CLRPE, port->membase + IFXMIPS_ASC_WHBSTATE);
117 } else if(rsr & ASCSTATE_FE)
119 port->icount.frame++;
120 ifxmips_w32(ifxmips_r32(port->membase + IFXMIPS_ASC_WHBSTATE) | ASCWHBSTATE_CLRFE, port->membase + IFXMIPS_ASC_WHBSTATE);
122 if(rsr & ASCSTATE_ROE)
124 port->icount.overrun++;
125 ifxmips_w32(ifxmips_r32(port->membase + IFXMIPS_ASC_WHBSTATE) | ASCWHBSTATE_CLRROE, port->membase + IFXMIPS_ASC_WHBSTATE);
128 rsr &= port->read_status_mask;
130 if(rsr & ASCSTATE_PE)
132 else if(rsr & ASCSTATE_FE)
136 if((rsr & port->ignore_status_mask) == 0)
137 tty_insert_flip_char(tty, ch, flag);
139 if(rsr & ASCSTATE_ROE)
141 * Overrun is special, since it's reported
142 * immediately, and doesn't affect the current
145 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
148 tty_flip_buffer_push(tty);
154 ifxmipsasc_tx_chars(struct uart_port *port)
156 struct circ_buf *xmit = &port->info->xmit;
157 if(uart_tx_stopped(port))
159 ifxmipsasc_stop_tx(port);
163 while(((ifxmips_r32(port->membase + IFXMIPS_ASC_FSTAT) & ASCFSTAT_TXFFLMASK)
164 >> ASCFSTAT_TXFFLOFF) != IFXMIPSASC_TXFIFO_FULL)
168 ifxmips_w32(port->x_char, port->membase + IFXMIPS_ASC_TBUF);
174 if(uart_circ_empty(xmit))
177 ifxmips_w32(port->info->xmit.buf[port->info->xmit.tail], port->membase + IFXMIPS_ASC_TBUF);
178 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
182 if(uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
183 uart_write_wakeup(port);
187 ifxmipsasc_tx_int(int irq, void *_port)
189 struct uart_port *port = (struct uart_port*) _port;
190 ifxmips_w32(ASC_IRNCR_TIR, port->membase + IFXMIPS_ASC_IRNCR);
191 ifxmipsasc_start_tx(port);
192 ifxmips_mask_and_ack_irq(irq);
197 ifxmipsasc_er_int(int irq, void *_port)
199 struct uart_port *port = (struct uart_port*) _port;
200 /* clear any pending interrupts */
201 ifxmips_w32(ifxmips_r32(port->membase + IFXMIPS_ASC_WHBSTATE) | ASCWHBSTATE_CLRPE |
202 ASCWHBSTATE_CLRFE | ASCWHBSTATE_CLRROE, port->membase + IFXMIPS_ASC_WHBSTATE);
207 ifxmipsasc_rx_int(int irq, void *_port)
209 struct uart_port *port = (struct uart_port*)_port;
210 ifxmips_w32(ASC_IRNCR_RIR, port->membase + IFXMIPS_ASC_IRNCR);
211 ifxmipsasc_rx_chars((struct uart_port*)port);
212 ifxmips_mask_and_ack_irq(irq);
217 ifxmipsasc_tx_empty(struct uart_port *port)
220 status = ifxmips_r32(port->membase + IFXMIPS_ASC_FSTAT) & ASCFSTAT_TXFFLMASK;
221 return status ? 0 : TIOCSER_TEMT;
225 ifxmipsasc_get_mctrl(struct uart_port *port)
227 return TIOCM_CTS | TIOCM_CAR | TIOCM_DSR;
231 ifxmipsasc_set_mctrl(struct uart_port *port, u_int mctrl)
236 ifxmipsasc_break_ctl(struct uart_port *port, int break_state)
241 ifxmipsasc_startup(struct uart_port *port)
246 port->uartclk = ifxmips_get_fpi_hz();
248 ifxmips_w32(ifxmips_r32(port->membase + IFXMIPS_ASC_CLC) & ~IFXMIPS_ASC_CLC_DISS, port->membase + IFXMIPS_ASC_CLC);
249 ifxmips_w32(((ifxmips_r32(port->membase + IFXMIPS_ASC_CLC) & ~ASCCLC_RMCMASK)) | (1 << ASCCLC_RMCOFFSET), port->membase + IFXMIPS_ASC_CLC);
250 ifxmips_w32(0, port->membase + IFXMIPS_ASC_PISEL);
251 ifxmips_w32(((IFXMIPSASC_TXFIFO_FL << ASCTXFCON_TXFITLOFF) & ASCTXFCON_TXFITLMASK) | ASCTXFCON_TXFEN | ASCTXFCON_TXFFLU, port->membase + IFXMIPS_ASC_TXFCON);
252 ifxmips_w32(((IFXMIPSASC_RXFIFO_FL << ASCRXFCON_RXFITLOFF) & ASCRXFCON_RXFITLMASK) | ASCRXFCON_RXFEN | ASCRXFCON_RXFFLU, port->membase + IFXMIPS_ASC_RXFCON);
254 ifxmips_w32(ifxmips_r32(port->membase + IFXMIPS_ASC_CON) | ASCCON_M_8ASYNC | ASCCON_FEN | ASCCON_TOEN | ASCCON_ROEN, port->membase + IFXMIPS_ASC_CON);
256 local_irq_save(flags);
258 retval = request_irq(port->irq, ifxmipsasc_tx_int, IRQF_DISABLED, "asc_tx", port);
261 printk("failed to request ifxmipsasc_tx_int\n");
265 retval = request_irq(port->irq + 2, ifxmipsasc_rx_int, IRQF_DISABLED, "asc_rx", port);
268 printk("failed to request ifxmipsasc_rx_int\n");
272 retval = request_irq(port->irq + 3, ifxmipsasc_er_int, IRQF_DISABLED, "asc_er", port);
275 printk("failed to request ifxmipsasc_er_int\n");
279 ifxmips_w32(ASC_IRNREN_RX_BUF | ASC_IRNREN_TX_BUF | ASC_IRNREN_ERR | ASC_IRNREN_TX, port->membase + IFXMIPS_ASC_IRNREN);
281 local_irq_restore(flags);
285 free_irq(port->irq + 2, port);
287 free_irq(port->irq, port);
288 local_irq_restore(flags);
293 ifxmipsasc_shutdown(struct uart_port *port)
295 free_irq(port->irq, port);
296 free_irq(port->irq + 2, port);
297 free_irq(port->irq + 3, port);
299 ifxmips_w32(0, port->membase + IFXMIPS_ASC_CON);
300 ifxmips_w32(ifxmips_r32(port->membase + IFXMIPS_ASC_RXFCON) | ASCRXFCON_RXFFLU, port->membase + IFXMIPS_ASC_RXFCON);
301 ifxmips_w32(ifxmips_r32(port->membase + IFXMIPS_ASC_RXFCON) & ~ASCRXFCON_RXFEN, port->membase + IFXMIPS_ASC_RXFCON);
302 ifxmips_w32(ifxmips_r32(port->membase + IFXMIPS_ASC_TXFCON) | ASCTXFCON_TXFFLU, port->membase + IFXMIPS_ASC_TXFCON);
303 ifxmips_w32(ifxmips_r32(port->membase + IFXMIPS_ASC_TXFCON) & ~ASCTXFCON_TXFEN, port->membase + IFXMIPS_ASC_TXFCON);
306 static void ifxmipsasc_set_termios(struct uart_port *port, struct ktermios *new, struct ktermios *old)
312 unsigned int con = 0;
315 cflag = new->c_cflag;
316 iflag = new->c_iflag;
318 switch(cflag & CSIZE)
321 con = ASCCON_M_7ASYNC;
327 con = ASCCON_M_8ASYNC;
336 if(!(cflag & PARODD))
342 port->read_status_mask = ASCSTATE_ROE;
344 port->read_status_mask |= ASCSTATE_FE | ASCSTATE_PE;
346 port->ignore_status_mask = 0;
348 port->ignore_status_mask |= ASCSTATE_FE | ASCSTATE_PE;
353 * If we're ignoring parity and break indicators,
354 * ignore overruns too (for real raw support).
357 port->ignore_status_mask |= ASCSTATE_ROE;
360 if((cflag & CREAD) == 0)
361 port->ignore_status_mask |= UART_DUMMY_UER_RX;
363 /* set error signals - framing, parity and overrun, enable receiver */
364 con |= ASCCON_FEN | ASCCON_TOEN | ASCCON_ROEN;
366 local_irq_save(flags);
369 ifxmips_w32(ifxmips_r32(port->membase + IFXMIPS_ASC_CON) | con, port->membase + IFXMIPS_ASC_CON);
371 /* Set baud rate - take a divider of 2 into account */
372 baud = uart_get_baud_rate(port, new, old, 0, port->uartclk / 16);
373 quot = uart_get_divisor(port, baud);
376 /* disable the baudrate generator */
377 ifxmips_w32(ifxmips_r32(port->membase + IFXMIPS_ASC_CON) & ~ASCCON_R, port->membase + IFXMIPS_ASC_CON);
379 /* make sure the fractional divider is off */
380 ifxmips_w32(ifxmips_r32(port->membase + IFXMIPS_ASC_CON) & ~ASCCON_FDE, port->membase + IFXMIPS_ASC_CON);
382 /* set up to use divisor of 2 */
383 ifxmips_w32(ifxmips_r32(port->membase + IFXMIPS_ASC_CON) & ~ASCCON_BRS, port->membase + IFXMIPS_ASC_CON);
385 /* now we can write the new baudrate into the register */
386 ifxmips_w32(quot, port->membase + IFXMIPS_ASC_BG);
388 /* turn the baudrate generator back on */
389 ifxmips_w32(ifxmips_r32(port->membase + IFXMIPS_ASC_CON) | ASCCON_R, port->membase + IFXMIPS_ASC_CON);
392 ifxmips_w32(ASCWHBSTATE_SETREN, port->membase + IFXMIPS_ASC_WHBSTATE);
394 local_irq_restore(flags);
398 ifxmipsasc_type(struct uart_port *port)
400 if(port->type == PORT_IFXMIPSASC)
402 if(port->membase == IFXMIPS_ASC_BASE_ADDR)
412 ifxmipsasc_release_port(struct uart_port *port)
417 ifxmipsasc_request_port(struct uart_port *port)
423 ifxmipsasc_config_port(struct uart_port *port, int flags)
425 if(flags & UART_CONFIG_TYPE)
427 port->type = PORT_IFXMIPSASC;
428 ifxmipsasc_request_port(port);
433 ifxmipsasc_verify_port(struct uart_port *port, struct serial_struct *ser)
436 if(ser->type != PORT_UNKNOWN && ser->type != PORT_IFXMIPSASC)
438 if(ser->irq < 0 || ser->irq >= NR_IRQS)
440 if(ser->baud_base < 9600)
445 static struct uart_ops ifxmipsasc_pops =
447 .tx_empty = ifxmipsasc_tx_empty,
448 .set_mctrl = ifxmipsasc_set_mctrl,
449 .get_mctrl = ifxmipsasc_get_mctrl,
450 .stop_tx = ifxmipsasc_stop_tx,
451 .start_tx = ifxmipsasc_start_tx,
452 .stop_rx = ifxmipsasc_stop_rx,
453 .enable_ms = ifxmipsasc_enable_ms,
454 .break_ctl = ifxmipsasc_break_ctl,
455 .startup = ifxmipsasc_startup,
456 .shutdown = ifxmipsasc_shutdown,
457 .set_termios = ifxmipsasc_set_termios,
458 .type = ifxmipsasc_type,
459 .release_port = ifxmipsasc_release_port,
460 .request_port = ifxmipsasc_request_port,
461 .config_port = ifxmipsasc_config_port,
462 .verify_port = ifxmipsasc_verify_port,
465 static struct uart_port ifxmipsasc_port[2] =
468 membase: (void *)IFXMIPS_ASC_BASE_ADDR,
469 mapbase: IFXMIPS_ASC_BASE_ADDR,
470 iotype: SERIAL_IO_MEM,
471 irq: IFXMIPSASC_TIR(0),
474 type: PORT_IFXMIPSASC,
475 ops: &ifxmipsasc_pops,
476 flags: ASYNC_BOOT_AUTOCONF,
479 membase: (void *)(IFXMIPS_ASC_BASE_ADDR + IFXMIPS_ASC_BASE_DIFF),
480 mapbase: IFXMIPS_ASC_BASE_ADDR + IFXMIPS_ASC_BASE_DIFF,
481 iotype: SERIAL_IO_MEM,
482 irq: IFXMIPSASC_TIR(1),
485 type: PORT_IFXMIPSASC,
486 ops: &ifxmipsasc_pops,
487 flags: ASYNC_BOOT_AUTOCONF,
493 ifxmipsasc_console_write(struct console *co, const char *s, u_int count)
495 int port = co->index;
498 local_irq_save(flags);
499 for(i = 0; i < count; i++)
502 fifocnt = (ifxmips_r32((u32*)(IFXMIPS_ASC_BASE_ADDR + (port * IFXMIPS_ASC_BASE_DIFF) + IFXMIPS_ASC_FSTAT)) & ASCFSTAT_TXFFLMASK)
503 >> ASCFSTAT_TXFFLOFF;
504 } while(fifocnt == IFXMIPSASC_TXFIFO_FULL);
511 ifxmips_w32('\r', (u32*)(IFXMIPS_ASC_BASE_ADDR + (port * IFXMIPS_ASC_BASE_DIFF) + IFXMIPS_ASC_TBUF));
513 fifocnt = (ifxmips_r32((u32*)(IFXMIPS_ASC_BASE_ADDR + (port * IFXMIPS_ASC_BASE_DIFF) + IFXMIPS_ASC_FSTAT)) & ASCFSTAT_TXFFLMASK)
514 >> ASCFSTAT_TXFFLOFF;
515 } while(fifocnt == IFXMIPSASC_TXFIFO_FULL);
517 ifxmips_w32(s[i], (u32*)(IFXMIPS_ASC_BASE_ADDR + (port * IFXMIPS_ASC_BASE_DIFF) + IFXMIPS_ASC_TBUF));
520 local_irq_restore(flags);
524 ifxmipsasc_console_setup(struct console *co, char *options)
526 int port = co->index;
531 ifxmipsasc_port[port].uartclk = ifxmips_get_fpi_hz();
532 ifxmipsasc_port[port].type = PORT_IFXMIPSASC;
534 uart_parse_options(options, &baud, &parity, &bits, &flow);
535 return uart_set_options(&ifxmipsasc_port[port], co, baud, parity, bits, flow);
538 static struct console ifxmipsasc_console[2] =
542 write: ifxmipsasc_console_write,
543 device: uart_console_device,
544 setup: ifxmipsasc_console_setup,
545 flags: CON_PRINTBUFFER,
547 data: &ifxmipsasc_reg,
550 write: ifxmipsasc_console_write,
551 device: uart_console_device,
552 setup: ifxmipsasc_console_setup,
553 flags: CON_PRINTBUFFER,
555 data: &ifxmipsasc_reg,
560 ifxmipsasc_console_init(void)
562 register_console(&ifxmipsasc_console[0]);
563 register_console(&ifxmipsasc_console[1]);
566 console_initcall(ifxmipsasc_console_init);
568 static struct uart_driver ifxmipsasc_reg =
570 .owner = THIS_MODULE,
571 .driver_name = "serial",
576 .cons = &ifxmipsasc_console[1],
580 ifxmipsasc_init(void)
583 uart_register_driver(&ifxmipsasc_reg);
584 ret = uart_add_one_port(&ifxmipsasc_reg, &ifxmipsasc_port[0]);
585 ret = uart_add_one_port(&ifxmipsasc_reg, &ifxmipsasc_port[1]);
590 ifxmipsasc_exit(void)
592 uart_unregister_driver(&ifxmipsasc_reg);
595 module_init(ifxmipsasc_init);
596 module_exit(ifxmipsasc_exit);
598 MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
599 MODULE_DESCRIPTION("MIPS IFXMips serial port driver");
600 MODULE_LICENSE("GPL");