2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License as published by
4 * the Free Software Foundation; either version 2 of the License, or
5 * (at your option) any later version.
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
12 * You should have received a copy of the GNU General Public License
13 * along with this program; if not, write to the Free Software
14 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
16 * Copyright (C) 2007 Xu Liang, infineon
17 * Copyright (C) 2008 John Crispin <blogic@openwrt.org>
20 #include <linux/kernel.h>
21 #include <linux/module.h>
22 #include <linux/version.h>
23 #include <linux/types.h>
25 #include <linux/miscdevice.h>
26 #include <linux/init.h>
27 #include <asm/uaccess.h>
28 #include <asm/unistd.h>
30 #include <asm/div64.h>
31 #include <linux/errno.h>
32 #include <asm/ifxmips/ifxmips.h>
34 #define FIX_FOR_36M_CRYSTAL 1
35 #define BASIC_INPUT_CLOCK_FREQUENCY_1 35328000
36 #define BASIC_INPUT_CLOCK_FREQUENCY_2 36000000
38 #define BASIS_INPUT_CRYSTAL_USB 12000000
40 #define GET_BITS(x, msb, lsb) (((x) & ((1 << ((msb) + 1)) - 1)) >> (lsb))
41 #define SET_BITS(x, msb, lsb, value) (((x) & ~(((1 << ((msb) + 1)) - 1) ^ ((1 << (lsb)) - 1))) | (((value) & ((1 << (1 + (msb) - (lsb))) - 1)) << (lsb)))
43 #define CGU_PLL0_PHASE_DIVIDER_ENABLE (*IFXMIPS_CGU_PLL0_CFG & (1 << 31))
44 #define CGU_PLL0_BYPASS (*IFXMIPS_CGU_PLL0_CFG & (1 << 30))
45 #define CGU_PLL0_SRC (*IFXMIPS_CGU_PLL0_CFG & (1 << 29))
46 #define CGU_PLL0_CFG_DSMSEL (*IFXMIPS_CGU_PLL0_CFG & (1 << 28))
47 #define CGU_PLL0_CFG_FRAC_EN (*IFXMIPS_CGU_PLL0_CFG & (1 << 27))
48 #define CGU_PLL0_CFG_PLLK GET_BITS(*IFXMIPS_CGU_PLL0_CFG, 26, 17)
49 #define CGU_PLL0_CFG_PLLN GET_BITS(*IFXMIPS_CGU_PLL0_CFG, 12, 6)
50 #define CGU_PLL0_CFG_PLLM GET_BITS(*IFXMIPS_CGU_PLL0_CFG, 5, 2)
51 #define CGU_PLL1_SRC (*IFXMIPS_CGU_PLL1_CFG & (1 << 31))
52 #define CGU_PLL1_BYPASS (*IFXMIPS_CGU_PLL1_CFG & (1 << 30))
53 #define CGU_PLL1_CFG_DSMSEL (*IFXMIPS_CGU_PLL1_CFG & (1 << 28))
54 #define CGU_PLL1_CFG_FRAC_EN (*IFXMIPS_CGU_PLL1_CFG & (1 << 27))
55 #define CGU_PLL1_CFG_PLLK GET_BITS(*IFXMIPS_CGU_PLL1_CFG, 26, 17)
56 #define CGU_PLL1_CFG_PLLN GET_BITS(*IFXMIPS_CGU_PLL1_CFG, 12, 6)
57 #define CGU_PLL1_CFG_PLLM GET_BITS(*IFXMIPS_CGU_PLL1_CFG, 5, 2)
58 #define CGU_PLL2_PHASE_DIVIDER_ENABLE (*IFXMIPS_CGU_PLL2_CFG & (1 << 20))
59 #define CGU_PLL2_BYPASS (*IFXMIPS_CGU_PLL2_CFG & (1 << 19))
60 #define CGU_PLL2_SRC GET_BITS(*IFXMIPS_CGU_PLL2_CFG, 18, 17)
61 #define CGU_PLL2_CFG_INPUT_DIV GET_BITS(*IFXMIPS_CGU_PLL2_CFG, 16, 13)
62 #define CGU_PLL2_CFG_PLLN GET_BITS(*IFXMIPS_CGU_PLL2_CFG, 12, 6)
63 #define CGU_PLL2_CFG_PLLM GET_BITS(*IFXMIPS_CGU_PLL2_CFG, 5, 2)
64 #define CGU_SYS_PPESEL GET_BITS(*IFXMIPS_CGU_SYS, 8, 7)
65 #define CGU_SYS_FPI_SEL (*IFXMIPS_CGU_SYS & (1 << 6))
66 #define CGU_SYS_CPU1SEL GET_BITS(*IFXMIPS_CGU_SYS, 5, 4)
67 #define CGU_SYS_CPU0SEL GET_BITS(*IFXMIPS_CGU_SYS, 3, 2)
68 #define CGU_SYS_DDR_SEL GET_BITS(*IFXMIPS_CGU_SYS, 1, 0)
69 #define CGU_IF_CLK_PCI_CLK GET_BITS(*IFXMIPS_CGU_IF_CLK, 23, 20)
70 #define CGU_IF_CLK_USBSEL GET_BITS(*IFXMIPS_CGU_IF_CLK, 5, 4)
71 #define CGU_IF_CLK_MIISEL GET_BITS(*IFXMIPS_CGU_IF_CLK, 1, 0)
73 static unsigned int cgu_get_pll0_fdiv(void);
75 static inline unsigned int
76 get_input_clock(int pll)
82 return BASIS_INPUT_CRYSTAL_USB;
83 else if(CGU_PLL0_PHASE_DIVIDER_ENABLE)
84 return BASIC_INPUT_CLOCK_FREQUENCY_1;
86 return BASIC_INPUT_CLOCK_FREQUENCY_2;
89 return BASIS_INPUT_CRYSTAL_USB;
90 else if(CGU_PLL0_PHASE_DIVIDER_ENABLE)
91 return BASIC_INPUT_CLOCK_FREQUENCY_1;
93 return BASIC_INPUT_CLOCK_FREQUENCY_2;
98 return cgu_get_pll0_fdiv();
100 return CGU_PLL2_PHASE_DIVIDER_ENABLE ? BASIC_INPUT_CLOCK_FREQUENCY_1 : BASIC_INPUT_CLOCK_FREQUENCY_2;
102 return BASIS_INPUT_CRYSTAL_USB;
109 static inline unsigned int
110 cal_dsm(int pll, unsigned int num, unsigned int den)
112 u64 res, clock = get_input_clock(pll);
119 static inline unsigned int
120 mash_dsm(int pll, unsigned int M, unsigned int N, unsigned int K)
122 unsigned int num = ((N + 1) << 10) + K;
123 unsigned int den = (M + 1) << 10;
125 return cal_dsm(pll, num, den);
128 static inline unsigned int
129 ssff_dsm_1(int pll, unsigned int M, unsigned int N, unsigned int K)
131 unsigned int num = ((N + 1) << 11) + K + 512;
132 unsigned int den = (M + 1) << 11;
134 return cal_dsm(pll, num, den);
137 static inline unsigned int
138 ssff_dsm_2(int pll, unsigned int M, unsigned int N, unsigned int K)
140 unsigned int num = K >= 512 ?
141 ((N + 1) << 12) + K - 512 : ((N + 1) << 12) + K + 3584;
142 unsigned int den = (M + 1) << 12;
144 return cal_dsm(pll, num, den);
147 static inline unsigned int
148 dsm(int pll, unsigned int M, unsigned int N, unsigned int K,
149 unsigned int dsmsel, unsigned int phase_div_en)
152 return mash_dsm(pll, M, N, K);
153 else if(!phase_div_en)
154 return mash_dsm(pll, M, N, K);
156 return ssff_dsm_2(pll, M, N, K);
159 static inline unsigned int
160 cgu_get_pll0_fosc(void)
163 return get_input_clock(0);
165 return !CGU_PLL0_CFG_FRAC_EN
166 ? dsm(0, CGU_PLL0_CFG_PLLM, CGU_PLL0_CFG_PLLN, 0, CGU_PLL0_CFG_DSMSEL,
167 CGU_PLL0_PHASE_DIVIDER_ENABLE)
168 : dsm(0, CGU_PLL0_CFG_PLLM, CGU_PLL0_CFG_PLLN, CGU_PLL0_CFG_PLLK,
169 CGU_PLL0_CFG_DSMSEL, CGU_PLL0_PHASE_DIVIDER_ENABLE);
172 static inline unsigned int
173 cgu_get_pll0_fps(int phase)
175 register unsigned int fps = cgu_get_pll0_fosc();
181 fps = ((fps << 2) + 2) / 5;
185 fps = ((fps << 1) + 1) / 3;
192 cgu_get_pll0_fdiv(void)
194 register unsigned int div = CGU_PLL2_CFG_INPUT_DIV + 1;
196 return (cgu_get_pll0_fosc() + (div >> 1)) / div;
199 static inline unsigned int
200 cgu_get_pll1_fosc(void)
203 return get_input_clock(1);
205 return !CGU_PLL1_CFG_FRAC_EN
206 ? dsm(1, CGU_PLL1_CFG_PLLM, CGU_PLL1_CFG_PLLN, 0, CGU_PLL1_CFG_DSMSEL, 0)
207 : dsm(1, CGU_PLL1_CFG_PLLM, CGU_PLL1_CFG_PLLN, CGU_PLL1_CFG_PLLK, CGU_PLL1_CFG_DSMSEL, 0);
210 static inline unsigned int
211 cgu_get_pll1_fps(void)
213 register unsigned int fps = cgu_get_pll1_fosc();
215 return ((fps << 1) + 1) / 3;
218 static inline unsigned int
219 cgu_get_pll1_fdiv(void)
221 return cgu_get_pll1_fosc();
224 static inline unsigned int
225 cgu_get_pll2_fosc(void)
227 u64 res, clock = get_input_clock(2);
229 if ( CGU_PLL2_BYPASS )
230 return get_input_clock(2);
232 res = (CGU_PLL2_CFG_PLLN + 1) * clock;
233 do_div(res, CGU_PLL2_CFG_PLLM + 1);
238 static inline unsigned int
239 cgu_get_pll2_fps(int phase)
241 register unsigned int fps = cgu_get_pll2_fosc();
247 fps = ((fps << 2) + 2) / 5; break;
250 fps = ((fps << 3) + 4) / 9;
256 static inline unsigned int
257 cgu_get_pll2_fdiv(void)
259 register unsigned int div = CGU_IF_CLK_PCI_CLK + 1;
260 return (cgu_get_pll2_fosc() + (div >> 1)) / div;
264 cgu_get_mips_clock(int cpu)
266 register unsigned int ret = cgu_get_pll0_fosc();
267 register unsigned int cpusel = cpu == 0 ? CGU_SYS_CPU0SEL : CGU_SYS_CPU1SEL;
274 switch(CGU_SYS_DDR_SEL)
278 return (ret + 1) / 2;
280 return (ret * 2 + 2) / 5;
282 return (ret + 1) / 3;
284 return (ret + 2) / 4;
289 cgu_get_cpu_clock(void)
291 return cgu_get_mips_clock(0);
295 cgu_get_io_region_clock(void)
297 register unsigned int ret = cgu_get_pll0_fosc();
299 switch(CGU_SYS_DDR_SEL)
303 return (ret + 1) / 2;
305 return (ret * 2 + 2) / 5;
307 return (ret + 1) / 3;
309 return (ret + 2) / 4;
314 cgu_get_fpi_bus_clock(int fpi)
316 register unsigned int ret = cgu_get_io_region_clock();
318 if((fpi == 2) && (CGU_SYS_FPI_SEL))
325 cgu_get_pp32_clock(void)
327 switch(CGU_SYS_PPESEL)
331 return cgu_get_pll2_fps(1);
333 return cgu_get_pll2_fps(2);
335 return (cgu_get_pll2_fps(1) + 1) >> 1;
337 return (cgu_get_pll2_fps(2) + 1) >> 1;
342 cgu_get_ethernet_clock(int mii)
344 switch(CGU_IF_CLK_MIISEL)
347 return (cgu_get_pll2_fosc() + 3) / 12;
349 return (cgu_get_pll2_fosc() + 3) / 6;
359 cgu_get_usb_clock(void)
361 switch(CGU_IF_CLK_USBSEL)
364 return (cgu_get_pll2_fosc() + 12) / 25;
376 cgu_get_clockout(int clkout)
378 unsigned int fosc1 = cgu_get_pll1_fosc();
379 unsigned int fosc2 = cgu_get_pll2_fosc();
381 if(clkout > 3 || clkout < 0)
384 switch(((unsigned int)clkout << 2) | GET_BITS(*IFXMIPS_CGU_IF_CLK, 15 - clkout * 2, 14 - clkout * 2))
386 case 0: /* 32.768KHz */
388 return (fosc1 + 6000) / 12000;
389 case 1: /* 1.536MHz */
390 return (fosc1 + 128) / 256;
392 return (fosc2 + 60) / 120;
396 return (fosc2 + 12) / 25;
398 return (cgu_get_pll2_fps(2) + 3) / 6;
400 return (cgu_get_pll2_fps(2) + 5) / 10;
402 return (cgu_get_pll2_fps(2) + 2) / 5;
405 return (fosc2 + 6) / 12;
408 return (fosc2 + 3) / 6;
410 return (fosc2 + 5) / 10;
412 return (fosc2 + 2) / 5;