2 * arch/mips/ifxmips/cgu.c
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
18 * Copyright (C) 2007 Xu Liang, infineon
20 * Rewrite of Infineon IFXMips code
21 * Copyright (C) 2008 John Crispin <blogic@openwrt.org>
25 #include <linux/kernel.h>
26 #include <linux/module.h>
27 #include <linux/version.h>
28 #include <linux/types.h>
30 #include <linux/miscdevice.h>
31 #include <linux/init.h>
32 #include <asm/uaccess.h>
33 #include <asm/unistd.h>
35 #include <asm/div64.h>
36 #include <linux/errno.h>
37 #include <asm/ifxmips/ifxmips.h>
39 #define FIX_FOR_36M_CRYSTAL 1
40 #define BASIC_INPUT_CLOCK_FREQUENCY_1 35328000
41 #define BASIC_INPUT_CLOCK_FREQUENCY_2 36000000
43 #define BASIS_INPUT_CRYSTAL_USB 12000000
45 #define GET_BITS(x, msb, lsb) (((x) & ((1 << ((msb) + 1)) - 1)) >> (lsb))
46 #define SET_BITS(x, msb, lsb, value) (((x) & ~(((1 << ((msb) + 1)) - 1) ^ ((1 << (lsb)) - 1))) | (((value) & ((1 << (1 + (msb) - (lsb))) - 1)) << (lsb)))
48 #define CGU_PLL0_PHASE_DIVIDER_ENABLE (*IFXMIPS_CGU_PLL0_CFG & (1 << 31))
49 #define CGU_PLL0_BYPASS (*IFXMIPS_CGU_PLL0_CFG & (1 << 30))
50 #define CGU_PLL0_SRC (*IFXMIPS_CGU_PLL0_CFG & (1 << 29))
51 #define CGU_PLL0_CFG_DSMSEL (*IFXMIPS_CGU_PLL0_CFG & (1 << 28))
52 #define CGU_PLL0_CFG_FRAC_EN (*IFXMIPS_CGU_PLL0_CFG & (1 << 27))
53 #define CGU_PLL0_CFG_PLLK GET_BITS(*IFXMIPS_CGU_PLL0_CFG, 26, 17)
54 #define CGU_PLL0_CFG_PLLN GET_BITS(*IFXMIPS_CGU_PLL0_CFG, 12, 6)
55 #define CGU_PLL0_CFG_PLLM GET_BITS(*IFXMIPS_CGU_PLL0_CFG, 5, 2)
56 #define CGU_PLL1_SRC (*IFXMIPS_CGU_PLL1_CFG & (1 << 31))
57 #define CGU_PLL1_BYPASS (*IFXMIPS_CGU_PLL1_CFG & (1 << 30))
58 #define CGU_PLL1_CFG_DSMSEL (*IFXMIPS_CGU_PLL1_CFG & (1 << 28))
59 #define CGU_PLL1_CFG_FRAC_EN (*IFXMIPS_CGU_PLL1_CFG & (1 << 27))
60 #define CGU_PLL1_CFG_PLLK GET_BITS(*IFXMIPS_CGU_PLL1_CFG, 26, 17)
61 #define CGU_PLL1_CFG_PLLN GET_BITS(*IFXMIPS_CGU_PLL1_CFG, 12, 6)
62 #define CGU_PLL1_CFG_PLLM GET_BITS(*IFXMIPS_CGU_PLL1_CFG, 5, 2)
63 #define CGU_PLL2_PHASE_DIVIDER_ENABLE (*IFXMIPS_CGU_PLL2_CFG & (1 << 20))
64 #define CGU_PLL2_BYPASS (*IFXMIPS_CGU_PLL2_CFG & (1 << 19))
65 #define CGU_PLL2_SRC GET_BITS(*IFXMIPS_CGU_PLL2_CFG, 18, 17)
66 #define CGU_PLL2_CFG_INPUT_DIV GET_BITS(*IFXMIPS_CGU_PLL2_CFG, 16, 13)
67 #define CGU_PLL2_CFG_PLLN GET_BITS(*IFXMIPS_CGU_PLL2_CFG, 12, 6)
68 #define CGU_PLL2_CFG_PLLM GET_BITS(*IFXMIPS_CGU_PLL2_CFG, 5, 2)
69 #define CGU_SYS_PPESEL GET_BITS(*IFXMIPS_CGU_SYS, 8, 7)
70 #define CGU_SYS_FPI_SEL (*IFXMIPS_CGU_SYS & (1 << 6))
71 #define CGU_SYS_CPU1SEL GET_BITS(*IFXMIPS_CGU_SYS, 5, 4)
72 #define CGU_SYS_CPU0SEL GET_BITS(*IFXMIPS_CGU_SYS, 3, 2)
73 #define CGU_SYS_DDR_SEL GET_BITS(*IFXMIPS_CGU_SYS, 1, 0)
74 #define CGU_IF_CLK_PCI_CLK GET_BITS(*IFXMIPS_CGU_IF_CLK, 23, 20)
75 #define CGU_IF_CLK_USBSEL GET_BITS(*IFXMIPS_CGU_IF_CLK, 5, 4)
76 #define CGU_IF_CLK_MIISEL GET_BITS(*IFXMIPS_CGU_IF_CLK, 1, 0)
78 static u32 cgu_get_pll0_fdiv(void);
80 static inline u32 get_input_clock(int pll)
86 return BASIS_INPUT_CRYSTAL_USB;
87 else if(CGU_PLL0_PHASE_DIVIDER_ENABLE)
88 return BASIC_INPUT_CLOCK_FREQUENCY_1;
90 return BASIC_INPUT_CLOCK_FREQUENCY_2;
93 return BASIS_INPUT_CRYSTAL_USB;
94 else if(CGU_PLL0_PHASE_DIVIDER_ENABLE)
95 return BASIC_INPUT_CLOCK_FREQUENCY_1;
97 return BASIC_INPUT_CLOCK_FREQUENCY_2;
102 return cgu_get_pll0_fdiv();
104 return CGU_PLL2_PHASE_DIVIDER_ENABLE ? BASIC_INPUT_CLOCK_FREQUENCY_1 : BASIC_INPUT_CLOCK_FREQUENCY_2;
106 return BASIS_INPUT_CRYSTAL_USB;
114 cal_dsm(int pll, u32 num, u32 den)
116 u64 res, clock = get_input_clock(pll);
124 mash_dsm(int pll, u32 M, u32 N, u32 K)
126 u32 num = ((N + 1) << 10) + K;
127 u32 den = (M + 1) << 10;
129 return cal_dsm(pll, num, den);
132 static inline u32 ssff_dsm_1(int pll, u32 M, u32 N, u32 K)
134 u32 num = ((N + 1) << 11) + K + 512;
135 u32 den = (M + 1) << 11;
137 return cal_dsm(pll, num, den);
140 static inline u32 ssff_dsm_2(int pll, u32 M, u32 N, u32 K)
142 u32 num = K >= 512 ? ((N + 1) << 12) + K - 512 : ((N + 1) << 12) + K + 3584;
143 u32 den = (M + 1) << 12;
145 return cal_dsm(pll, num, den);
148 static inline u32 dsm(int pll, u32 M, u32 N, u32 K, u32 dsmsel, u32 phase_div_en)
151 return mash_dsm(pll, M, N, K);
152 else if ( !phase_div_en )
153 return mash_dsm(pll, M, N, K);
155 return ssff_dsm_2(pll, M, N, K);
158 static inline u32 cgu_get_pll0_fosc(void)
161 return get_input_clock(0);
163 return !CGU_PLL0_CFG_FRAC_EN
164 ? dsm(0, CGU_PLL0_CFG_PLLM, CGU_PLL0_CFG_PLLN, 0, CGU_PLL0_CFG_DSMSEL, CGU_PLL0_PHASE_DIVIDER_ENABLE)
165 : dsm(0, CGU_PLL0_CFG_PLLM, CGU_PLL0_CFG_PLLN, CGU_PLL0_CFG_PLLK, CGU_PLL0_CFG_DSMSEL, CGU_PLL0_PHASE_DIVIDER_ENABLE);
168 static inline u32 cgu_get_pll0_fps(int phase)
170 register u32 fps = cgu_get_pll0_fosc();
176 fps = ((fps << 2) + 2) / 5;
180 fps = ((fps << 1) + 1) / 3;
186 static u32 cgu_get_pll0_fdiv(void)
188 register u32 div = CGU_PLL2_CFG_INPUT_DIV + 1;
190 return (cgu_get_pll0_fosc() + (div >> 1)) / div;
193 static inline u32 cgu_get_pll1_fosc(void)
196 return get_input_clock(1);
198 return !CGU_PLL1_CFG_FRAC_EN
199 ? dsm(1, CGU_PLL1_CFG_PLLM, CGU_PLL1_CFG_PLLN, 0, CGU_PLL1_CFG_DSMSEL, 0)
200 : dsm(1, CGU_PLL1_CFG_PLLM, CGU_PLL1_CFG_PLLN, CGU_PLL1_CFG_PLLK, CGU_PLL1_CFG_DSMSEL, 0);
203 static inline u32 cgu_get_pll1_fps(void)
205 register u32 fps = cgu_get_pll1_fosc();
207 return ((fps << 1) + 1) / 3;
210 static inline u32 cgu_get_pll1_fdiv(void)
212 return cgu_get_pll1_fosc();
215 static inline u32 cgu_get_pll2_fosc(void)
217 u64 res, clock = get_input_clock(2);
219 if ( CGU_PLL2_BYPASS )
220 return get_input_clock(2);
222 res = (CGU_PLL2_CFG_PLLN + 1) * clock;
223 do_div(res, CGU_PLL2_CFG_PLLM + 1);
228 static inline u32 cgu_get_pll2_fps(int phase)
230 register u32 fps = cgu_get_pll2_fosc();
236 fps = ((fps << 2) + 2) / 5; break;
239 fps = ((fps << 3) + 4) / 9;
245 static inline u32 cgu_get_pll2_fdiv(void)
247 register u32 div = CGU_IF_CLK_PCI_CLK + 1;
248 return (cgu_get_pll2_fosc() + (div >> 1)) / div;
251 u32 cgu_get_mips_clock(int cpu)
253 register u32 ret = cgu_get_pll0_fosc();
254 register u32 cpusel = cpu == 0 ? CGU_SYS_CPU0SEL : CGU_SYS_CPU1SEL;
258 else if ( cpusel == 2 )
261 switch ( CGU_SYS_DDR_SEL )
265 return (ret + 1) / 2;
267 return (ret * 2 + 2) / 5;
269 return (ret + 1) / 3;
271 return (ret + 2) / 4;
275 u32 cgu_get_cpu_clock(void)
277 return cgu_get_mips_clock(0);
280 u32 cgu_get_io_region_clock(void)
282 register u32 ret = cgu_get_pll0_fosc();
284 switch ( CGU_SYS_DDR_SEL )
288 return (ret + 1) / 2;
290 return (ret * 2 + 2) / 5;
292 return (ret + 1) / 3;
294 return (ret + 2) / 4;
298 u32 cgu_get_fpi_bus_clock(int fpi)
300 register u32 ret = cgu_get_io_region_clock();
302 if((fpi == 2) && (CGU_SYS_FPI_SEL))
308 u32 cgu_get_pp32_clock(void)
310 switch ( CGU_SYS_PPESEL )
314 return cgu_get_pll2_fps(1);
316 return cgu_get_pll2_fps(2);
318 return (cgu_get_pll2_fps(1) + 1) >> 1;
320 return (cgu_get_pll2_fps(2) + 1) >> 1;
324 u32 cgu_get_ethernet_clock(int mii)
326 switch ( CGU_IF_CLK_MIISEL )
329 return (cgu_get_pll2_fosc() + 3) / 12;
331 return (cgu_get_pll2_fosc() + 3) / 6;
340 u32 cgu_get_usb_clock(void)
342 switch ( CGU_IF_CLK_USBSEL )
345 return (cgu_get_pll2_fosc() + 12) / 25;
356 u32 cgu_get_clockout(int clkout)
358 u32 fosc1 = cgu_get_pll1_fosc();
359 u32 fosc2 = cgu_get_pll2_fosc();
361 if ( clkout > 3 || clkout < 0 )
364 switch ( ((u32)clkout << 2) | GET_BITS(*IFXMIPS_CGU_IF_CLK, 15 - clkout * 2, 14 - clkout * 2) )
366 case 0: /* 32.768KHz */
368 return (fosc1 + 6000) / 12000;
369 case 1: /* 1.536MHz */
370 return (fosc1 + 128) / 256;
372 return (fosc2 + 60) / 120;
376 return (fosc2 + 12) / 25;
378 return (cgu_get_pll2_fps(2) + 3) / 6;
380 return (cgu_get_pll2_fps(2) + 5) / 10;
382 return (cgu_get_pll2_fps(2) + 2) / 5;
385 return (fosc2 + 6) / 12;
388 return (fosc2 + 3) / 6;
390 return (fosc2 + 5) / 10;
392 return (fosc2 + 2) / 5;