2 * Sonics Silicon Backplane
3 * Broadcom ChipCommon core driver
5 * Copyright 2005, Broadcom Corporation
6 * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de>
8 * Licensed under the GNU/GPL. See COPYING for details.
11 #include <linux/ssb/ssb.h>
12 #include <linux/ssb/ssb_regs.h>
13 #include <linux/pci.h>
15 #include "ssb_private.h"
21 SSB_CHIPCO_CLKSRC_PCI,
22 /* Crystal slow clock oscillator */
23 SSB_CHIPCO_CLKSRC_XTALOS,
24 /* Low power oscillator */
25 SSB_CHIPCO_CLKSRC_LOPWROS,
29 static inline u32 chipco_read32(struct ssb_chipcommon *cc,
32 return ssb_read32(cc->dev, offset);
35 static inline void chipco_write32(struct ssb_chipcommon *cc,
39 ssb_write32(cc->dev, offset, value);
42 void ssb_chipco_set_clockmode(struct ssb_chipcommon *cc,
43 enum ssb_clkmode mode)
45 struct ssb_device *ccdev = cc->dev;
52 /* chipcommon cores prior to rev6 don't support dynamic clock control */
53 if (ccdev->id.revision < 6)
55 /* chipcommon cores rev10 are a whole new ball game */
56 if (ccdev->id.revision >= 10)
58 if (!(cc->capabilities & SSB_CHIPCO_CAP_PCTL))
62 case SSB_CLKMODE_SLOW:
63 tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
64 tmp |= SSB_CHIPCO_SLOWCLKCTL_FSLOW;
65 chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
67 case SSB_CLKMODE_FAST:
68 ssb_pci_xtal(bus, SSB_GPIO_XTAL, 1); /* Force crystal on */
69 tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
70 tmp &= ~SSB_CHIPCO_SLOWCLKCTL_FSLOW;
71 tmp |= SSB_CHIPCO_SLOWCLKCTL_IPLL;
72 chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
74 case SSB_CLKMODE_DYNAMIC:
75 tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
76 tmp &= ~SSB_CHIPCO_SLOWCLKCTL_FSLOW;
77 tmp &= ~SSB_CHIPCO_SLOWCLKCTL_IPLL;
78 tmp &= ~SSB_CHIPCO_SLOWCLKCTL_ENXTAL;
79 if ((tmp & SSB_CHIPCO_SLOWCLKCTL_SRC) != SSB_CHIPCO_SLOWCLKCTL_SRC_XTAL)
80 tmp |= SSB_CHIPCO_SLOWCLKCTL_ENXTAL;
81 chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
83 /* for dynamic control, we have to release our xtal_pu "force on" */
84 if (tmp & SSB_CHIPCO_SLOWCLKCTL_ENXTAL)
85 ssb_pci_xtal(bus, SSB_GPIO_XTAL, 0);
92 /* Get the Slow Clock Source */
93 static int chipco_pctl_get_slowclksrc(struct ssb_chipcommon *cc)
95 struct ssb_bus *bus = cc->dev->bus;
98 if (cc->dev->id.revision < 6) {
99 if (bus->bustype == SSB_BUSTYPE_SSB ||
100 bus->bustype == SSB_BUSTYPE_PCMCIA)
101 return SSB_CHIPCO_CLKSRC_XTALOS;
102 if (bus->bustype == SSB_BUSTYPE_PCI) {
103 pci_read_config_dword(bus->host_pci, SSB_GPIO_OUT, &tmp);
105 return SSB_CHIPCO_CLKSRC_PCI;
106 return SSB_CHIPCO_CLKSRC_XTALOS;
109 if (cc->dev->id.revision < 10) {
110 tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
113 return SSB_CHIPCO_CLKSRC_LOPWROS;
115 return SSB_CHIPCO_CLKSRC_XTALOS;
117 return SSB_CHIPCO_CLKSRC_PCI;
120 return SSB_CHIPCO_CLKSRC_XTALOS;
123 /* Get maximum or minimum (depending on get_max flag) slowclock frequency. */
124 static int chipco_pctl_clockfreqlimit(struct ssb_chipcommon *cc, int get_max)
131 clocksrc = chipco_pctl_get_slowclksrc(cc);
132 if (cc->dev->id.revision < 6) {
134 case SSB_CHIPCO_CLKSRC_PCI:
137 case SSB_CHIPCO_CLKSRC_XTALOS:
144 } else if (cc->dev->id.revision < 10) {
146 case SSB_CHIPCO_CLKSRC_LOPWROS:
149 case SSB_CHIPCO_CLKSRC_XTALOS:
150 case SSB_CHIPCO_CLKSRC_PCI:
151 tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
152 divisor = (tmp >> 16) + 1;
160 tmp = chipco_read32(cc, SSB_CHIPCO_SYSCLKCTL);
161 divisor = (tmp >> 16) + 1;
166 case SSB_CHIPCO_CLKSRC_LOPWROS:
172 case SSB_CHIPCO_CLKSRC_XTALOS:
178 case SSB_CHIPCO_CLKSRC_PCI:
193 static void chipco_powercontrol_init(struct ssb_chipcommon *cc)
195 struct ssb_bus *bus = cc->dev->bus;
197 if (bus->chip_id == 0x4321) {
198 if (bus->chip_rev == 0)
199 chipco_write32(cc, SSB_CHIPCO_CHIPCTL, 0x3A4);
200 else if (bus->chip_rev == 1)
201 chipco_write32(cc, SSB_CHIPCO_CHIPCTL, 0xA4);
204 if (!(cc->capabilities & SSB_CHIPCO_CAP_PCTL))
207 if (cc->dev->id.revision >= 10) {
208 /* Set Idle Power clock rate to 1Mhz */
209 chipco_write32(cc, SSB_CHIPCO_SYSCLKCTL,
210 (chipco_read32(cc, SSB_CHIPCO_SYSCLKCTL) &
211 0x0000FFFF) | 0x00040000);
215 maxfreq = chipco_pctl_clockfreqlimit(cc, 1);
216 chipco_write32(cc, SSB_CHIPCO_PLLONDELAY,
217 (maxfreq * 150 + 999999) / 1000000);
218 chipco_write32(cc, SSB_CHIPCO_FREFSELDELAY,
219 (maxfreq * 15 + 999999) / 1000000);
223 static void calc_fast_powerup_delay(struct ssb_chipcommon *cc)
225 struct ssb_bus *bus = cc->dev->bus;
230 if (bus->bustype != SSB_BUSTYPE_PCI)
232 if (!(cc->capabilities & SSB_CHIPCO_CAP_PCTL))
235 minfreq = chipco_pctl_clockfreqlimit(cc, 0);
236 pll_on_delay = chipco_read32(cc, SSB_CHIPCO_PLLONDELAY);
237 tmp = (((pll_on_delay + 2) * 1000000) + (minfreq - 1)) / minfreq;
238 assert((tmp & ~0xFFFF) == 0);
240 cc->fast_pwrup_delay = tmp;
243 void ssb_chipcommon_init(struct ssb_chipcommon *cc)
246 return; /* We don't have a ChipCommon */
247 chipco_powercontrol_init(cc);
248 ssb_chipco_set_clockmode(cc, SSB_CLKMODE_FAST);
249 calc_fast_powerup_delay(cc);
252 void ssb_chipco_suspend(struct ssb_chipcommon *cc, pm_message_t state)
256 ssb_chipco_set_clockmode(cc, SSB_CLKMODE_SLOW);
259 void ssb_chipco_resume(struct ssb_chipcommon *cc)
263 chipco_powercontrol_init(cc);
264 ssb_chipco_set_clockmode(cc, SSB_CLKMODE_FAST);
267 void ssb_chipco_get_clockcontrol(struct ssb_chipcommon *cc,
268 u32 *plltype, u32 *n, u32 *m)
270 *n = chipco_read32(cc, SSB_CHIPCO_CLOCK_N);
271 *plltype = (cc->capabilities & SSB_CHIPCO_CAP_PLLT);
273 case SSB_PLLTYPE_6: /* 100/200 or 120/240 only */
274 *m = chipco_read32(cc, SSB_CHIPCO_CLOCK_MIPS);
276 case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */
277 if (cc->dev->bus->chip_id != 0x5365) {
278 *m = chipco_read32(cc, SSB_CHIPCO_CLOCK_M2);
283 *m = chipco_read32(cc, SSB_CHIPCO_CLOCK_SB);
287 void ssb_chipco_timing_init(struct ssb_chipcommon *cc,
290 struct ssb_device *dev = cc->dev;
291 struct ssb_bus *bus = dev->bus;
294 /* set register for external IO to control LED. */
295 chipco_write32(cc, SSB_CHIPCO_PROG_CFG, 0x11);
296 tmp = DIV_ROUND_UP(10, ns) << SSB_PROG_WCNT_3_SHIFT; /* Waitcount-3 = 10ns */
297 tmp |= DIV_ROUND_UP(40, ns) << SSB_PROG_WCNT_1_SHIFT; /* Waitcount-1 = 40ns */
298 tmp |= DIV_ROUND_UP(240, ns); /* Waitcount-0 = 240ns */
299 chipco_write32(cc, SSB_CHIPCO_PROG_WAITCNT, tmp); /* 0x01020a0c for a 100Mhz clock */
301 /* Set timing for the flash */
302 tmp = DIV_ROUND_UP(10, ns) << SSB_FLASH_WCNT_3_SHIFT; /* Waitcount-3 = 10nS */
303 tmp |= DIV_ROUND_UP(10, ns) << SSB_FLASH_WCNT_1_SHIFT; /* Waitcount-1 = 10nS */
304 tmp |= DIV_ROUND_UP(120, ns); /* Waitcount-0 = 120nS */
305 if ((bus->chip_id == 0x5365) ||
306 (dev->id.revision < 9))
307 chipco_write32(cc, SSB_CHIPCO_FLASH_WAITCNT, tmp);
308 if ((bus->chip_id == 0x5365) ||
309 (dev->id.revision < 9) ||
310 ((bus->chip_id == 0x5350) && (bus->chip_rev == 0)))
311 chipco_write32(cc, SSB_CHIPCO_PCMCIA_MEMWAIT, tmp);
313 if (bus->chip_id == 0x5350) {
315 tmp = DIV_ROUND_UP(10, ns) << SSB_PROG_WCNT_3_SHIFT; /* Waitcount-3 = 10ns */
316 tmp |= DIV_ROUND_UP(20, ns) << SSB_PROG_WCNT_2_SHIFT; /* Waitcount-2 = 20ns */
317 tmp |= DIV_ROUND_UP(100, ns) << SSB_PROG_WCNT_1_SHIFT; /* Waitcount-1 = 100ns */
318 tmp |= DIV_ROUND_UP(120, ns); /* Waitcount-0 = 120ns */
319 chipco_write32(cc, SSB_CHIPCO_PROG_WAITCNT, tmp); /* 0x01020a0c for a 100Mhz clock */
324 #ifdef CONFIG_SSB_SERIAL
325 int ssb_chipco_serial_init(struct ssb_chipcommon *cc,
326 struct ssb_serial_port *ports)
328 struct ssb_bus *bus = cc->dev->bus;
335 plltype = (cc->capabilities & SSB_CHIPCO_CAP_PLLT);
336 irq = ssb_mips_irq(cc->dev);
338 if (plltype == SSB_PLLTYPE_1) {
340 baud_base = ssb_calc_clock_rate(plltype,
341 chipco_read32(cc, SSB_CHIPCO_CLOCK_N),
342 chipco_read32(cc, SSB_CHIPCO_CLOCK_M2));
345 if (cc->dev->id.revision >= 11) {
346 /* Fixed ALP clock */
347 baud_base = 20000000;
349 /* Set the override bit so we don't divide it */
350 chipco_write32(cc, SSB_CHIPCO_CORECTL,
351 SSB_CHIPCO_CORECTL_UARTCLK0);
352 } else if (cc->dev->id.revision >= 3) {
353 /* Internal backplane clock */
354 baud_base = ssb_clockspeed(bus);
355 div = 2; /* Minimum divisor */
356 chipco_write32(cc, SSB_CHIPCO_CLKDIV,
357 (chipco_read32(cc, SSB_CHIPCO_CLKDIV)
358 & ~SSB_CHIPCO_CLKDIV_UART) | div);
360 /* Fixed internal backplane clock */
361 baud_base = 88000000;
365 /* Clock source depends on strapping if UartClkOverride is unset */
366 if ((cc->dev->id.revision > 0) &&
367 !(chipco_read32(cc, SSB_CHIPCO_CORECTL) & SSB_CHIPCO_CORECTL_UARTCLK0)) {
368 if ((cc->capabilities & SSB_CHIPCO_CAP_UARTCLK) ==
369 SSB_CHIPCO_CAP_UARTCLK_INT) {
370 /* Internal divided backplane clock */
373 /* Assume external clock of 1.8432 MHz */
379 /* Determine the registers of the UARTs */
380 n = (cc->capabilities & SSB_CHIPCO_CAP_NRUART);
381 for (i = 0; i < n; i++) {
382 void __iomem *cc_mmio;
383 void __iomem *uart_regs;
385 cc_mmio = cc->dev->bus->mmio + (cc->dev->core_index * SSB_CORE_SIZE);
386 uart_regs = cc_mmio + SSB_CHIPCO_UART0_DATA;
387 /* Offset changed at after rev 0 */
388 if (cc->dev->id.revision == 0)
389 uart_regs += (i * 8);
391 uart_regs += (i * 256);
394 ports[i].regs = uart_regs;
396 ports[i].baud_base = baud_base;
397 ports[i].reg_shift = 0;
402 #endif /* CONFIG_SSB_SERIAL */