2 * rtl8306.c: RTL8306S switch driver
4 * Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 as published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
17 #include <linux/module.h>
18 #include <linux/init.h>
19 #include <linux/list.h>
20 #include <linux/if_ether.h>
21 #include <linux/skbuff.h>
22 #include <linux/netdevice.h>
23 #include <linux/netlink.h>
24 #include <net/genetlink.h>
25 #include <linux/switch.h>
26 #include <linux/delay.h>
27 #include <linux/phy.h>
32 #define RTL8306_REG_PAGE 16
33 #define RTL8306_REG_PAGE_LO (1 << 15)
34 #define RTL8306_REG_PAGE_HI (1 << 1) /* inverted */
36 #define RTL8306_NUM_VLANS 16
37 #define RTL8306_NUM_PORTS 6
38 #define RTL8306_PORT_CPU 5
39 #define RTL8306_NUM_PAGES 4
40 #define RTL8306_NUM_REGS 32
42 #define RTL_NAME_S "RTL8306S"
43 #define RTL_NAME_SD "RTL8306SD"
44 #define RTL_NAME_SDM "RTL8306SDM"
45 #define RTL_NAME_UNKNOWN "RTL8306(unknown)"
47 #define RTL8306_MAGIC 0x8306
50 struct switch_dev dev;
55 char hwname[sizeof(RTL_NAME_UNKNOWN)];
57 /* temporary register saves for port operations */
63 #define to_rtl(_dev) container_of(_dev, struct rtl_priv, dev)
80 #define RTL_VLAN_REGOFS(name) \
81 (RTL_REG_VLAN1_##name - RTL_REG_VLAN0_##name)
83 #define RTL_PORT_REGOFS(name) \
84 (RTL_REG_PORT1_##name - RTL_REG_PORT0_##name)
86 #define RTL_PORT_REG(id, reg) \
87 (RTL_REG_PORT0_##reg + (id * RTL_PORT_REGOFS(reg)))
89 #define RTL_VLAN_REG(id, reg) \
90 (RTL_REG_VLAN0_##reg + (id * RTL_VLAN_REGOFS(reg)))
92 #define RTL_GLOBAL_REGATTR(reg) \
93 .id = RTL_REG_##reg, \
94 .type = SWITCH_TYPE_INT, \
96 .set = rtl_attr_set_int, \
97 .get = rtl_attr_get_int
99 #define RTL_PORT_REGATTR(reg) \
100 .id = RTL_REG_PORT0_##reg, \
101 .type = SWITCH_TYPE_INT, \
102 .ofs = RTL_PORT_REGOFS(reg), \
103 .set = rtl_attr_set_port_int, \
104 .get = rtl_attr_get_port_int
106 #define RTL_VLAN_REGATTR(reg) \
107 .id = RTL_REG_VLAN0_##reg, \
108 .type = SWITCH_TYPE_INT, \
109 .ofs = RTL_VLAN_REGOFS(reg), \
110 .set = rtl_attr_set_vlan_int, \
111 .get = rtl_attr_get_vlan_int
124 RTL_REG_TRUNK_PORTSEL,
130 RTL_REG_VLAN_TAG_ONLY,
131 RTL_REG_VLAN_TAG_AWARE,
132 #define RTL_VLAN_ENUM(id) \
133 RTL_REG_VLAN##id##_VID, \
134 RTL_REG_VLAN##id##_PORTMASK
151 #define RTL_PORT_ENUM(id) \
152 RTL_REG_PORT##id##_PVID, \
153 RTL_REG_PORT##id##_NULL_VID_REPLACE, \
154 RTL_REG_PORT##id##_NON_PVID_DISCARD, \
155 RTL_REG_PORT##id##_VID_INSERT, \
156 RTL_REG_PORT##id##_TAG_INSERT, \
157 RTL_REG_PORT##id##_LINK, \
158 RTL_REG_PORT##id##_SPEED, \
159 RTL_REG_PORT##id##_NWAY, \
160 RTL_REG_PORT##id##_DUPLEX, \
161 RTL_REG_PORT##id##_RXEN, \
162 RTL_REG_PORT##id##_TXEN
171 static const struct rtl_reg rtl_regs[] = {
172 [RTL_REG_CHIPID] = { 0, 4, 30, 16, 0, 0 },
173 [RTL_REG_CHIPVER] = { 0, 4, 31, 8, 0, 0 },
174 [RTL_REG_CHIPTYPE] = { 0, 4, 31, 2, 8, 0 },
176 /* CPU port number */
177 [RTL_REG_CPUPORT] = { 2, 4, 21, 3, 0, 0 },
178 /* Enable CPU port function */
179 [RTL_REG_EN_CPUPORT] = { 3, 2, 21, 1, 15, 1 },
180 /* Enable CPU port tag insertion */
181 [RTL_REG_EN_TAG_OUT] = { 3, 2, 21, 1, 12, 0 },
182 /* Enable CPU port tag removal */
183 [RTL_REG_EN_TAG_CLR] = { 3, 2, 21, 1, 11, 0 },
184 /* Enable CPU port tag checking */
185 [RTL_REG_EN_TAG_IN] = { 0, 4, 21, 1, 7, 0 },
186 [RTL_REG_EN_TRUNK] = { 0, 0, 19, 1, 11, 1 },
187 [RTL_REG_TRUNK_PORTSEL] = { 0, 0, 16, 1, 6, 1 },
188 [RTL_REG_RESET] = { 0, 0, 16, 1, 12, 0 },
190 [RTL_REG_TRAP_CPU] = { 3, 2, 22, 1, 6, 0 },
192 [RTL_REG_VLAN_TAG_ONLY] = { 0, 0, 16, 1, 8, 1 },
193 [RTL_REG_VLAN_FILTER] = { 0, 0, 16, 1, 9, 1 },
194 [RTL_REG_VLAN_TAG_AWARE] = { 0, 0, 16, 1, 10, 1 },
195 [RTL_REG_VLAN_ENABLE] = { 0, 0, 18, 1, 8, 1 },
197 #define RTL_VLAN_REGS(id, phy, page, regofs) \
198 [RTL_REG_VLAN##id##_VID] = { page, phy, 25 + regofs, 12, 0, 0 }, \
199 [RTL_REG_VLAN##id##_PORTMASK] = { page, phy, 24 + regofs, 6, 0, 0 }
200 RTL_VLAN_REGS( 0, 0, 0, 0),
201 RTL_VLAN_REGS( 1, 1, 0, 0),
202 RTL_VLAN_REGS( 2, 2, 0, 0),
203 RTL_VLAN_REGS( 3, 3, 0, 0),
204 RTL_VLAN_REGS( 4, 4, 0, 0),
205 RTL_VLAN_REGS( 5, 0, 1, 2),
206 RTL_VLAN_REGS( 6, 1, 1, 2),
207 RTL_VLAN_REGS( 7, 2, 1, 2),
208 RTL_VLAN_REGS( 8, 3, 1, 2),
209 RTL_VLAN_REGS( 9, 4, 1, 2),
210 RTL_VLAN_REGS(10, 0, 1, 4),
211 RTL_VLAN_REGS(11, 1, 1, 4),
212 RTL_VLAN_REGS(12, 2, 1, 4),
213 RTL_VLAN_REGS(13, 3, 1, 4),
214 RTL_VLAN_REGS(14, 4, 1, 4),
215 RTL_VLAN_REGS(15, 0, 1, 6),
217 #define REG_PORT_SETTING(port, phy) \
218 [RTL_REG_PORT##port##_SPEED] = { 0, phy, 0, 1, 13, 0 }, \
219 [RTL_REG_PORT##port##_NWAY] = { 0, phy, 0, 1, 12, 0 }, \
220 [RTL_REG_PORT##port##_DUPLEX] = { 0, phy, 0, 1, 8, 0 }, \
221 [RTL_REG_PORT##port##_TXEN] = { 0, phy, 24, 1, 11, 0 }, \
222 [RTL_REG_PORT##port##_RXEN] = { 0, phy, 24, 1, 10, 0 }, \
223 [RTL_REG_PORT##port##_LINK] = { 0, phy, 1, 1, 2, 0 }, \
224 [RTL_REG_PORT##port##_NULL_VID_REPLACE] = { 0, phy, 22, 1, 12, 0 }, \
225 [RTL_REG_PORT##port##_NON_PVID_DISCARD] = { 0, phy, 22, 1, 11, 0 }, \
226 [RTL_REG_PORT##port##_VID_INSERT] = { 0, phy, 22, 2, 9, 0 }, \
227 [RTL_REG_PORT##port##_TAG_INSERT] = { 0, phy, 22, 2, 0, 0 }
229 REG_PORT_SETTING(0, 0),
230 REG_PORT_SETTING(1, 1),
231 REG_PORT_SETTING(2, 2),
232 REG_PORT_SETTING(3, 3),
233 REG_PORT_SETTING(4, 4),
234 REG_PORT_SETTING(5, 6),
236 #define REG_PORT_PVID(phy, page, regofs) \
237 { page, phy, 24 + regofs, 4, 12, 0 }
238 [RTL_REG_PORT0_PVID] = REG_PORT_PVID(0, 0, 0),
239 [RTL_REG_PORT1_PVID] = REG_PORT_PVID(1, 0, 0),
240 [RTL_REG_PORT2_PVID] = REG_PORT_PVID(2, 0, 0),
241 [RTL_REG_PORT3_PVID] = REG_PORT_PVID(3, 0, 0),
242 [RTL_REG_PORT4_PVID] = REG_PORT_PVID(4, 0, 0),
243 [RTL_REG_PORT5_PVID] = REG_PORT_PVID(0, 1, 2),
247 /* IFXMIPS compat stuff - remove after PHY layer migration */
248 static struct switch_dev rtldev;
249 /* END IFXMIPS compat stuff */
253 rtl_set_page(struct rtl_priv *priv, unsigned int page)
255 struct mii_bus *bus = priv->bus;
258 if (priv->page == page)
261 BUG_ON(page > RTL8306_NUM_PAGES);
262 pgsel = bus->read(bus, 0, RTL8306_REG_PAGE);
263 pgsel &= ~(RTL8306_REG_PAGE_LO | RTL8306_REG_PAGE_HI);
265 pgsel |= RTL8306_REG_PAGE_LO;
266 if (!(page & (1 << 1))) /* bit is inverted */
267 pgsel |= RTL8306_REG_PAGE_HI;
268 bus->write(bus, 0, RTL8306_REG_PAGE, pgsel);
272 rtl_w16(struct switch_dev *dev, unsigned int page, unsigned int phy, unsigned int reg, u16 val)
274 struct rtl_priv *priv = to_rtl(dev);
275 struct mii_bus *bus = priv->bus;
277 rtl_set_page(priv, page);
278 bus->write(bus, phy, reg, val);
279 bus->read(bus, phy, reg); /* flush */
284 rtl_r16(struct switch_dev *dev, unsigned int page, unsigned int phy, unsigned int reg)
286 struct rtl_priv *priv = to_rtl(dev);
287 struct mii_bus *bus = priv->bus;
289 rtl_set_page(priv, page);
290 return bus->read(bus, phy, reg);
294 rtl_rmw(struct switch_dev *dev, unsigned int page, unsigned int phy, unsigned int reg, u16 mask, u16 val)
296 struct rtl_priv *priv = to_rtl(dev);
297 struct mii_bus *bus = priv->bus;
300 rtl_set_page(priv, page);
301 r = bus->read(bus, phy, reg);
304 bus->write(bus, phy, reg, r);
305 return bus->read(bus, phy, reg); /* flush */
310 rtl_get(struct switch_dev *dev, enum rtl_regidx s)
312 const struct rtl_reg *r = &rtl_regs[s];
315 BUG_ON(s >= ARRAY_SIZE(rtl_regs));
316 if (r->bits == 0) /* unimplemented */
319 val = rtl_r16(dev, r->page, r->phy, r->reg);
327 val &= (1 << r->bits) - 1;
333 rtl_set(struct switch_dev *dev, enum rtl_regidx s, unsigned int val)
335 const struct rtl_reg *r = &rtl_regs[s];
338 BUG_ON(s >= ARRAY_SIZE(rtl_regs));
340 if (r->bits == 0) /* unimplemented */
350 mask = (1 << r->bits) - 1;
354 return rtl_rmw(dev, r->page, r->phy, r->reg, mask, val);
358 rtl_phy_save(struct switch_dev *dev, int port)
360 struct rtl_priv *priv = to_rtl(dev);
362 priv->tmp_nway = rtl_get(dev, RTL_PORT_REG(port, NWAY));
363 priv->tmp_speed = rtl_get(dev, RTL_PORT_REG(port, SPEED));
364 priv->tmp_duplex = rtl_get(dev, RTL_PORT_REG(port, DUPLEX));
368 rtl_phy_restore(struct switch_dev *dev, int port)
370 struct rtl_priv *priv = to_rtl(dev);
372 rtl_set(dev, RTL_PORT_REG(port, NWAY), priv->tmp_nway);
373 rtl_set(dev, RTL_PORT_REG(port, SPEED), priv->tmp_speed);
374 rtl_set(dev, RTL_PORT_REG(port, DUPLEX), priv->tmp_duplex);
378 rtl_port_set_enable(struct switch_dev *dev, int port, int enabled)
380 rtl_set(dev, RTL_PORT_REG(port, RXEN), enabled);
381 rtl_set(dev, RTL_PORT_REG(port, TXEN), enabled);
385 rtl_hw_apply(struct switch_dev *dev)
388 int trunk_en, trunk_psel;
390 rtl_phy_save(dev, 5);
392 /* disable rx/tx from PHYs */
393 for (i = 0; i < RTL8306_NUM_PORTS - 1; i++) {
394 rtl_port_set_enable(dev, i, 0);
397 /* save trunking status */
398 trunk_en = rtl_get(dev, RTL_REG_EN_TRUNK);
399 trunk_psel = rtl_get(dev, RTL_REG_TRUNK_PORTSEL);
401 /* trunk port 3 and 4
402 * XXX: Big WTF, but RealTek seems to do it */
403 rtl_set(dev, RTL_REG_EN_TRUNK, 1);
404 rtl_set(dev, RTL_REG_TRUNK_PORTSEL, 1);
406 /* execute the software reset */
407 rtl_set(dev, RTL_REG_RESET, 1);
409 /* wait for the reset to complete,
410 * but don't wait for too long */
411 for (i = 0; i < 10; i++) {
412 if (rtl_get(dev, RTL_REG_RESET) == 0)
418 /* enable rx/tx from PHYs */
419 for (i = 0; i < RTL8306_NUM_PORTS - 1; i++) {
420 rtl_port_set_enable(dev, i, 1);
423 /* restore trunking settings */
424 rtl_set(dev, RTL_REG_EN_TRUNK, trunk_en);
425 rtl_set(dev, RTL_REG_TRUNK_PORTSEL, trunk_psel);
427 rtl_phy_restore(dev, 5);
433 rtl_hw_init(struct switch_dev *dev)
435 struct rtl_priv *priv = to_rtl(dev);
436 int cpu_mask = 1 << dev->cpu_port;
439 rtl_set(dev, RTL_REG_VLAN_ENABLE, 0);
440 rtl_set(dev, RTL_REG_VLAN_FILTER, 0);
441 rtl_set(dev, RTL_REG_EN_TRUNK, 0);
442 rtl_set(dev, RTL_REG_TRUNK_PORTSEL, 0);
444 /* initialize cpu port settings */
446 rtl_set(dev, RTL_REG_CPUPORT, dev->cpu_port);
447 rtl_set(dev, RTL_REG_EN_CPUPORT, 1);
449 rtl_set(dev, RTL_REG_CPUPORT, 7);
450 rtl_set(dev, RTL_REG_EN_CPUPORT, 0);
452 rtl_set(dev, RTL_REG_EN_TAG_OUT, 0);
453 rtl_set(dev, RTL_REG_EN_TAG_IN, 0);
454 rtl_set(dev, RTL_REG_EN_TAG_CLR, 0);
456 /* reset all vlans */
457 for (i = 0; i < RTL8306_NUM_VLANS; i++) {
458 rtl_set(dev, RTL_VLAN_REG(i, VID), i);
459 rtl_set(dev, RTL_VLAN_REG(i, PORTMASK), 0);
462 /* default to port isolation */
463 for (i = 0; i < RTL8306_NUM_PORTS; i++) {
466 if ((1 << i) == cpu_mask)
467 mask = ((1 << RTL8306_NUM_PORTS) - 1) & ~cpu_mask; /* all bits set */
469 mask = cpu_mask | (1 << i);
471 rtl_set(dev, RTL_VLAN_REG(i, PORTMASK), mask);
472 rtl_set(dev, RTL_PORT_REG(i, PVID), i);
473 rtl_set(dev, RTL_PORT_REG(i, NULL_VID_REPLACE), 1);
474 rtl_set(dev, RTL_PORT_REG(i, VID_INSERT), 1);
475 rtl_set(dev, RTL_PORT_REG(i, TAG_INSERT), 3);
482 rtl_set_use_cpuport(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val)
484 struct rtl_priv *priv = to_rtl(dev);
485 priv->do_cpu = val->value.i;
491 rtl_get_use_cpuport(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val)
493 struct rtl_priv *priv = to_rtl(dev);
494 val->value.i = priv->do_cpu;
499 rtl_set_cpuport(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val)
501 dev->cpu_port = val->value.i;
507 rtl_get_cpuport(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val)
509 val->value.i = dev->cpu_port;
515 rtl_reset(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val)
522 rtl_attr_set_int(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val)
524 int idx = attr->id + (val->port_vlan * attr->ofs);
526 if (attr->id >= ARRAY_SIZE(rtl_regs))
529 if ((attr->max > 0) && (val->value.i > attr->max))
532 /* access to phy register 22 on port 4/5
533 * needs phy status save/restore */
534 if ((val->port_vlan > 3) &&
535 (rtl_regs[idx].reg == 22) &&
536 (rtl_regs[idx].page == 0)) {
538 rtl_phy_save(dev, val->port_vlan);
539 rtl_set(dev, idx, val->value.i);
540 rtl_phy_restore(dev, val->port_vlan);
542 rtl_set(dev, idx, val->value.i);
549 rtl_attr_get_int(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val)
551 int idx = attr->id + (val->port_vlan * attr->ofs);
553 if (idx >= ARRAY_SIZE(rtl_regs))
556 val->value.i = rtl_get(dev, idx);
561 rtl_attr_set_port_int(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val)
563 if (val->port_vlan >= RTL8306_NUM_PORTS)
566 return rtl_attr_set_int(dev, attr, val);
570 rtl_attr_get_port_int(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val)
572 if (val->port_vlan >= RTL8306_NUM_PORTS)
574 return rtl_attr_get_int(dev, attr, val);
578 rtl_attr_set_vlan_int(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val)
580 if (val->port_vlan >= dev->vlans)
583 return rtl_attr_set_int(dev, attr, val);
587 rtl_attr_get_vlan_int(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val)
589 if (val->port_vlan >= dev->vlans)
592 return rtl_attr_get_int(dev, attr, val);
596 rtl_get_ports(struct switch_dev *dev, struct switch_val *val)
598 unsigned int i, mask;
600 mask = rtl_get(dev, RTL_VLAN_REG(val->port_vlan, PORTMASK));
601 for (i = 0; i < RTL8306_NUM_PORTS; i++) {
602 struct switch_port *port;
604 if (!(mask & (1 << i)))
607 port = &val->value.ports[val->len];
617 rtl_set_vlan(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val)
619 struct rtl_priv *priv = to_rtl(dev);
620 int en = val->value.i;
623 rtl_set(dev, RTL_REG_EN_TAG_OUT, en && priv->do_cpu);
624 rtl_set(dev, RTL_REG_EN_TAG_IN, en && priv->do_cpu);
625 rtl_set(dev, RTL_REG_EN_TAG_CLR, en && priv->do_cpu);
626 rtl_set(dev, RTL_REG_VLAN_TAG_AWARE, en);
628 rtl_set(dev, RTL_REG_VLAN_FILTER, en);
630 for (i = 0; i < RTL8306_NUM_PORTS; i++) {
632 rtl_phy_save(dev, val->port_vlan);
633 rtl_set(dev, RTL_PORT_REG(i, NULL_VID_REPLACE), 1);
634 rtl_set(dev, RTL_PORT_REG(i, VID_INSERT), (en ? (i == dev->cpu_port ? 0 : 1) : 1));
635 rtl_set(dev, RTL_PORT_REG(i, TAG_INSERT), (en ? (i == dev->cpu_port ? 2 : 1) : 3));
637 rtl_phy_restore(dev, val->port_vlan);
639 rtl_set(dev, RTL_REG_VLAN_ENABLE, en);
645 rtl_get_vlan(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val)
647 return rtl_get(dev, RTL_REG_VLAN_ENABLE);
651 rtl_set_ports(struct switch_dev *dev, struct switch_val *val)
653 unsigned int mask = 0;
654 unsigned int oldmask;
657 for(i = 0; i < val->len; i++)
659 struct switch_port *port = &val->value.ports[i];
662 mask |= (1 << port->id);
664 if (port->id == dev->cpu_port)
667 if ((i == dev->cpu_port) ||
668 (port->flags & (1 << SWITCH_PORT_FLAG_TAGGED)))
671 /* fix up PVIDs for added ports */
673 rtl_set(dev, RTL_PORT_REG(port->id, PVID), val->port_vlan);
675 rtl_set(dev, RTL_PORT_REG(port->id, NON_PVID_DISCARD), (tagged ? 0 : 1));
676 rtl_set(dev, RTL_PORT_REG(port->id, VID_INSERT), (tagged ? 0 : 1));
677 rtl_set(dev, RTL_PORT_REG(port->id, TAG_INSERT), (tagged ? 2 : 1));
680 oldmask = rtl_get(dev, RTL_VLAN_REG(val->port_vlan, PORTMASK));
681 rtl_set(dev, RTL_VLAN_REG(val->port_vlan, PORTMASK), mask);
683 /* fix up PVIDs for removed ports, default to last vlan */
685 for (i = 0; i < RTL8306_NUM_PORTS; i++) {
686 if (!(oldmask & (1 << i)))
689 if (i == dev->cpu_port)
692 if (rtl_get(dev, RTL_PORT_REG(i, PVID)) == val->port_vlan)
693 rtl_set(dev, RTL_PORT_REG(i, PVID), dev->vlans - 1);
700 rtl8306_config_init(struct phy_device *pdev)
702 struct net_device *netdev = pdev->attached_dev;
703 struct rtl_priv *priv = pdev->priv;
704 struct switch_dev *dev = &priv->dev;
705 struct switch_val val;
706 unsigned int chipid, chipver, chiptype;
710 memcpy(&priv->dev, &rtldev, sizeof(struct switch_dev));
713 priv->bus = pdev->bus;
717 chipid = rtl_get(dev, RTL_REG_CHIPID);
718 chipver = rtl_get(dev, RTL_REG_CHIPVER);
719 chiptype = rtl_get(dev, RTL_REG_CHIPTYPE);
723 strncpy(priv->hwname, RTL_NAME_S, sizeof(priv->hwname));
724 priv->type = RTL_TYPE_S;
727 strncpy(priv->hwname, RTL_NAME_SD, sizeof(priv->hwname));
728 priv->type = RTL_TYPE_SD;
731 strncpy(priv->hwname, RTL_NAME_SDM, sizeof(priv->hwname));
732 priv->type = RTL_TYPE_SDM;
735 strncpy(priv->hwname, RTL_NAME_UNKNOWN, sizeof(priv->hwname));
739 dev->name = priv->hwname;
742 printk(KERN_INFO "Registering %s switch with Chip ID: 0x%04x, version: 0x%04x\n", priv->hwname, chipid, chipver);
744 err = register_switch(dev, netdev);
753 static struct switch_attr rtl_globals[] = {
755 .type = SWITCH_TYPE_INT,
757 .description = "Reset the switch",
761 .type = SWITCH_TYPE_INT,
762 .name = "enable_vlan",
763 .description = "Enable VLAN mode",
769 RTL_GLOBAL_REGATTR(EN_TRUNK),
771 .description = "Enable port trunking",
775 RTL_GLOBAL_REGATTR(TRUNK_PORTSEL),
777 .description = "Select ports for trunking (0: 0,1 - 1: 3,4)",
782 RTL_GLOBAL_REGATTR(VLAN_FILTER),
783 .name = "vlan_filter",
784 .description = "Filter incoming packets for allowed VLANS",
788 .type = SWITCH_TYPE_INT,
790 .description = "CPU Port",
791 .set = rtl_set_cpuport,
792 .get = rtl_get_cpuport,
793 .max = RTL8306_NUM_PORTS,
796 .type = SWITCH_TYPE_INT,
797 .name = "use_cpuport",
798 .description = "CPU Port handling flag",
799 .set = rtl_set_use_cpuport,
800 .get = rtl_get_use_cpuport,
801 .max = RTL8306_NUM_PORTS,
804 RTL_GLOBAL_REGATTR(TRAP_CPU),
806 .description = "VLAN trap to CPU",
810 RTL_GLOBAL_REGATTR(VLAN_TAG_AWARE),
811 .name = "vlan_tag_aware",
812 .description = "Enable VLAN tag awareness",
816 RTL_GLOBAL_REGATTR(VLAN_TAG_ONLY),
818 .description = "Only accept tagged packets",
823 static struct switch_attr rtl_port[] = {
825 RTL_PORT_REGATTR(PVID),
827 .description = "Port VLAN ID",
828 .max = RTL8306_NUM_VLANS - 1,
831 RTL_PORT_REGATTR(LINK),
833 .description = "get the current link state",
839 RTL_PORT_REGATTR(NULL_VID_REPLACE),
841 .description = "NULL VID gets replaced by port default vid",
845 RTL_PORT_REGATTR(NON_PVID_DISCARD),
846 .name = "non_pvid_discard",
847 .description = "discard packets with VID != PVID",
851 RTL_PORT_REGATTR(VID_INSERT),
852 .name = "vid_insert_remove",
853 .description = "how should the switch insert and remove vids ?",
857 RTL_PORT_REGATTR(TAG_INSERT),
858 .name = "tag_insert",
859 .description = "tag insertion handling",
864 RTL_PORT_REGATTR(SPEED),
866 .description = "current link speed",
870 RTL_PORT_REGATTR(NWAY),
872 .description = "enable autonegotiation",
877 static struct switch_attr rtl_vlan[] = {
879 RTL_VLAN_REGATTR(VID),
881 .description = "VLAN ID",
887 static struct switch_dev rtldev = {
888 .cpu_port = RTL8306_PORT_CPU,
889 .ports = RTL8306_NUM_PORTS,
890 .vlans = RTL8306_NUM_VLANS,
893 .n_attr = ARRAY_SIZE(rtl_globals),
897 .n_attr = ARRAY_SIZE(rtl_port),
901 .n_attr = ARRAY_SIZE(rtl_vlan),
904 .get_vlan_ports = rtl_get_ports,
905 .set_vlan_ports = rtl_set_ports,
906 .apply_config = rtl_hw_apply,
911 rtl8306_fixup(struct phy_device *pdev)
913 struct rtl_priv priv;
917 priv.bus = pdev->bus;
918 chipid = rtl_get(&priv.dev, RTL_REG_CHIPID);
919 if (chipid == 0x5988)
920 pdev->phy_id = RTL8306_MAGIC;
926 rtl8306_probe(struct phy_device *pdev)
928 struct rtl_priv *priv;
930 priv = kzalloc(sizeof(struct rtl_priv), GFP_KERNEL);
939 rtl8306_remove(struct phy_device *pdev)
941 struct rtl_priv *priv = pdev->priv;
942 unregister_switch(&priv->dev);
947 rtl8306_config_aneg(struct phy_device *pdev)
953 rtl8306_read_status(struct phy_device *pdev)
955 pdev->speed = SPEED_100;
956 pdev->duplex = DUPLEX_FULL;
957 pdev->state = PHY_UP;
963 static struct phy_driver rtl8306_driver = {
964 .name = "Realtek RTL8306S",
965 .phy_id = RTL8306_MAGIC,
966 .phy_id_mask = 0xffffffff,
967 .features = PHY_BASIC_FEATURES,
968 .probe = &rtl8306_probe,
969 .remove = &rtl8306_remove,
970 .config_init = &rtl8306_config_init,
971 .config_aneg = &rtl8306_config_aneg,
972 .read_status = &rtl8306_read_status,
973 .driver = { .owner = THIS_MODULE,},
980 phy_register_fixup_for_id(PHY_ANY_ID, rtl8306_fixup);
981 return phy_driver_register(&rtl8306_driver);
987 phy_driver_unregister(&rtl8306_driver);
990 module_init(rtl_init);
991 module_exit(rtl_exit);
992 MODULE_LICENSE("GPL");