1 --- a/drivers/bcma/Kconfig
2 +++ b/drivers/bcma/Kconfig
3 @@ -26,6 +26,7 @@ config BCMA_HOST_PCI_POSSIBLE
5 bool "Support for BCMA on PCI-host bus"
6 depends on BCMA_HOST_PCI_POSSIBLE
9 config BCMA_DRIVER_PCI_HOSTMODE
10 bool "Driver for PCI core working in hostmode"
11 --- a/drivers/bcma/bcma_private.h
12 +++ b/drivers/bcma/bcma_private.h
17 +bool bcma_wait_value(struct bcma_device *core, u16 reg, u32 mask, u32 value,
19 int bcma_bus_register(struct bcma_bus *bus);
20 void bcma_bus_unregister(struct bcma_bus *bus);
21 int __init bcma_bus_early_register(struct bcma_bus *bus,
22 --- a/drivers/bcma/core.c
23 +++ b/drivers/bcma/core.c
25 #include <linux/export.h>
26 #include <linux/bcma/bcma.h>
28 +static bool bcma_core_wait_value(struct bcma_device *core, u16 reg, u32 mask,
29 + u32 value, int timeout)
31 + unsigned long deadline = jiffies + timeout;
35 + val = bcma_aread32(core, reg);
36 + if ((val & mask) == value)
40 + } while (!time_after_eq(jiffies, deadline));
42 + bcma_warn(core->bus, "Timeout waiting for register 0x%04X!\n", reg);
47 bool bcma_core_is_enabled(struct bcma_device *core)
49 if ((bcma_aread32(core, BCMA_IOCTL) & (BCMA_IOCTL_CLK | BCMA_IOCTL_FGC))
50 @@ -25,13 +44,15 @@ void bcma_core_disable(struct bcma_devic
51 if (bcma_aread32(core, BCMA_RESET_CTL) & BCMA_RESET_CTL_RESET)
54 - bcma_awrite32(core, BCMA_IOCTL, flags);
55 - bcma_aread32(core, BCMA_IOCTL);
57 + bcma_core_wait_value(core, BCMA_RESET_ST, ~0, 0, 300);
59 bcma_awrite32(core, BCMA_RESET_CTL, BCMA_RESET_CTL_RESET);
60 bcma_aread32(core, BCMA_RESET_CTL);
63 + bcma_awrite32(core, BCMA_IOCTL, flags);
64 + bcma_aread32(core, BCMA_IOCTL);
67 EXPORT_SYMBOL_GPL(bcma_core_disable);
69 @@ -43,6 +64,7 @@ int bcma_core_enable(struct bcma_device
70 bcma_aread32(core, BCMA_IOCTL);
72 bcma_awrite32(core, BCMA_RESET_CTL, 0);
73 + bcma_aread32(core, BCMA_RESET_CTL);
76 bcma_awrite32(core, BCMA_IOCTL, (BCMA_IOCTL_CLK | flags));
77 @@ -104,7 +126,13 @@ void bcma_core_pll_ctl(struct bcma_devic
79 bcma_err(core->bus, "PLL enable timeout\n");
81 - bcma_warn(core->bus, "Disabling PLL not supported yet!\n");
83 + * Mask the PLL but don't wait for it to be disabled. PLL may be
84 + * shared between cores and will be still up if there is another
87 + bcma_mask32(core, BCMA_CLKCTLST, ~req);
88 + bcma_read32(core, BCMA_CLKCTLST);
91 EXPORT_SYMBOL_GPL(bcma_core_pll_ctl);
92 --- a/drivers/bcma/driver_chipcommon.c
93 +++ b/drivers/bcma/driver_chipcommon.c
94 @@ -25,13 +25,14 @@ static inline u32 bcma_cc_write32_masked
98 -static u32 bcma_chipco_get_alp_clock(struct bcma_drv_cc *cc)
99 +u32 bcma_chipco_get_alp_clock(struct bcma_drv_cc *cc)
101 if (cc->capabilities & BCMA_CC_CAP_PMU)
102 return bcma_pmu_get_alp_clock(cc);
106 +EXPORT_SYMBOL_GPL(bcma_chipco_get_alp_clock);
108 static u32 bcma_chipco_watchdog_get_max_timer(struct bcma_drv_cc *cc)
110 @@ -139,8 +140,15 @@ void bcma_core_chipcommon_init(struct bc
111 bcma_core_chipcommon_early_init(cc);
113 if (cc->core->id.rev >= 20) {
114 - bcma_cc_write32(cc, BCMA_CC_GPIOPULLUP, 0);
115 - bcma_cc_write32(cc, BCMA_CC_GPIOPULLDOWN, 0);
116 + u32 pullup = 0, pulldown = 0;
118 + if (cc->core->bus->chipinfo.id == BCMA_CHIP_ID_BCM43142) {
120 + pulldown = 0x20500;
123 + bcma_cc_write32(cc, BCMA_CC_GPIOPULLUP, pullup);
124 + bcma_cc_write32(cc, BCMA_CC_GPIOPULLDOWN, pulldown);
127 if (cc->capabilities & BCMA_CC_CAP_PMU)
128 @@ -213,6 +221,7 @@ u32 bcma_chipco_gpio_out(struct bcma_drv
132 +EXPORT_SYMBOL_GPL(bcma_chipco_gpio_out);
134 u32 bcma_chipco_gpio_outen(struct bcma_drv_cc *cc, u32 mask, u32 value)
136 @@ -225,6 +234,7 @@ u32 bcma_chipco_gpio_outen(struct bcma_d
140 +EXPORT_SYMBOL_GPL(bcma_chipco_gpio_outen);
143 * If the bit is set to 0, chipcommon controlls this GPIO,
144 --- a/drivers/bcma/driver_chipcommon_pmu.c
145 +++ b/drivers/bcma/driver_chipcommon_pmu.c
146 @@ -56,6 +56,109 @@ void bcma_chipco_regctl_maskset(struct b
148 EXPORT_SYMBOL_GPL(bcma_chipco_regctl_maskset);
150 +static u32 bcma_pmu_xtalfreq(struct bcma_drv_cc *cc)
152 + u32 ilp_ctl, alp_hz;
154 + if (!(bcma_cc_read32(cc, BCMA_CC_PMU_STAT) &
155 + BCMA_CC_PMU_STAT_EXT_LPO_AVAIL))
158 + bcma_cc_write32(cc, BCMA_CC_PMU_XTAL_FREQ,
159 + BIT(BCMA_CC_PMU_XTAL_FREQ_MEASURE_SHIFT));
160 + usleep_range(1000, 2000);
162 + ilp_ctl = bcma_cc_read32(cc, BCMA_CC_PMU_XTAL_FREQ);
163 + ilp_ctl &= BCMA_CC_PMU_XTAL_FREQ_ILPCTL_MASK;
165 + bcma_cc_write32(cc, BCMA_CC_PMU_XTAL_FREQ, 0);
167 + alp_hz = ilp_ctl * 32768 / 4;
168 + return (alp_hz + 50000) / 100000 * 100;
171 +static void bcma_pmu2_pll_init0(struct bcma_drv_cc *cc, u32 xtalfreq)
173 + struct bcma_bus *bus = cc->core->bus;
174 + u32 freq_tgt_target = 0, freq_tgt_current;
177 + switch (bus->chipinfo.id) {
178 + case BCMA_CHIP_ID_BCM43142:
179 + /* pmu2_xtaltab0_adfll_485 */
180 + switch (xtalfreq) {
182 + freq_tgt_target = 0x50D52;
185 + freq_tgt_target = 0x307FE;
188 + freq_tgt_target = 0x254EA;
191 + freq_tgt_target = 0x19EF8;
194 + freq_tgt_target = 0x12A75;
200 + if (!freq_tgt_target) {
201 + bcma_err(bus, "Unknown TGT frequency for xtalfreq %d\n",
206 + pll0 = bcma_chipco_pll_read(cc, BCMA_CC_PMU15_PLL_PLLCTL0);
207 + freq_tgt_current = (pll0 & BCMA_CC_PMU15_PLL_PC0_FREQTGT_MASK) >>
208 + BCMA_CC_PMU15_PLL_PC0_FREQTGT_SHIFT;
210 + if (freq_tgt_current == freq_tgt_target) {
211 + bcma_debug(bus, "Target TGT frequency already set\n");
216 + switch (bus->chipinfo.id) {
217 + case BCMA_CHIP_ID_BCM43142:
218 + mask = (u32)~(BCMA_RES_4314_HT_AVAIL |
219 + BCMA_RES_4314_MACPHY_CLK_AVAIL);
221 + bcma_cc_mask32(cc, BCMA_CC_PMU_MINRES_MSK, mask);
222 + bcma_cc_mask32(cc, BCMA_CC_PMU_MAXRES_MSK, mask);
223 + bcma_wait_value(cc->core, BCMA_CLKCTLST,
224 + BCMA_CLKCTLST_HAVEHT, 0, 20000);
228 + pll0 &= ~BCMA_CC_PMU15_PLL_PC0_FREQTGT_MASK;
229 + pll0 |= freq_tgt_target << BCMA_CC_PMU15_PLL_PC0_FREQTGT_SHIFT;
230 + bcma_chipco_pll_write(cc, BCMA_CC_PMU15_PLL_PLLCTL0, pll0);
233 + if (cc->pmu.rev >= 2)
234 + bcma_cc_set32(cc, BCMA_CC_PMU_CTL, BCMA_CC_PMU_CTL_PLL_UPD);
236 + /* TODO: Do we need to update OTP? */
239 +static void bcma_pmu_pll_init(struct bcma_drv_cc *cc)
241 + struct bcma_bus *bus = cc->core->bus;
242 + u32 xtalfreq = bcma_pmu_xtalfreq(cc);
244 + switch (bus->chipinfo.id) {
245 + case BCMA_CHIP_ID_BCM43142:
248 + bcma_pmu2_pll_init0(cc, xtalfreq);
253 static void bcma_pmu_resources_init(struct bcma_drv_cc *cc)
255 struct bcma_bus *bus = cc->core->bus;
256 @@ -66,6 +169,25 @@ static void bcma_pmu_resources_init(stru
260 + case BCMA_CHIP_ID_BCM43142:
261 + min_msk = BCMA_RES_4314_LPLDO_PU |
262 + BCMA_RES_4314_PMU_SLEEP_DIS |
263 + BCMA_RES_4314_PMU_BG_PU |
264 + BCMA_RES_4314_CBUCK_LPOM_PU |
265 + BCMA_RES_4314_CBUCK_PFM_PU |
266 + BCMA_RES_4314_CLDO_PU |
267 + BCMA_RES_4314_LPLDO2_LVM |
268 + BCMA_RES_4314_WL_PMU_PU |
269 + BCMA_RES_4314_LDO3P3_PU |
270 + BCMA_RES_4314_OTP_PU |
271 + BCMA_RES_4314_WL_PWRSW_PU |
272 + BCMA_RES_4314_LQ_AVAIL |
273 + BCMA_RES_4314_LOGIC_RET |
274 + BCMA_RES_4314_MEM_SLEEP |
275 + BCMA_RES_4314_MACPHY_RET |
276 + BCMA_RES_4314_WL_CORE_READY;
277 + max_msk = 0x3FFFFFFF;
280 bcma_debug(bus, "PMU resource config unknown or not needed for device 0x%04X\n",
282 @@ -165,6 +287,7 @@ void bcma_pmu_init(struct bcma_drv_cc *c
283 bcma_cc_set32(cc, BCMA_CC_PMU_CTL,
284 BCMA_CC_PMU_CTL_NOILPONW);
286 + bcma_pmu_pll_init(cc);
287 bcma_pmu_resources_init(cc);
288 bcma_pmu_workarounds(cc);
290 @@ -174,19 +297,35 @@ u32 bcma_pmu_get_alp_clock(struct bcma_d
291 struct bcma_bus *bus = cc->core->bus;
293 switch (bus->chipinfo.id) {
294 + case BCMA_CHIP_ID_BCM4313:
295 + case BCMA_CHIP_ID_BCM43224:
296 + case BCMA_CHIP_ID_BCM43225:
297 + case BCMA_CHIP_ID_BCM43227:
298 + case BCMA_CHIP_ID_BCM43228:
299 + case BCMA_CHIP_ID_BCM4331:
300 + case BCMA_CHIP_ID_BCM43421:
301 + case BCMA_CHIP_ID_BCM43428:
302 + case BCMA_CHIP_ID_BCM43431:
303 case BCMA_CHIP_ID_BCM4716:
304 - case BCMA_CHIP_ID_BCM4748:
305 case BCMA_CHIP_ID_BCM47162:
306 - case BCMA_CHIP_ID_BCM4313:
307 - case BCMA_CHIP_ID_BCM5357:
308 + case BCMA_CHIP_ID_BCM4748:
309 case BCMA_CHIP_ID_BCM4749:
310 + case BCMA_CHIP_ID_BCM5357:
311 case BCMA_CHIP_ID_BCM53572:
312 + case BCMA_CHIP_ID_BCM6362:
315 - case BCMA_CHIP_ID_BCM5356:
316 case BCMA_CHIP_ID_BCM4706:
317 + case BCMA_CHIP_ID_BCM5356:
320 + case BCMA_CHIP_ID_BCM43460:
321 + case BCMA_CHIP_ID_BCM4352:
322 + case BCMA_CHIP_ID_BCM4360:
323 + if (cc->status & BCMA_CC_CHIPST_4360_XTAL_40MZ)
324 + return 40000 * 1000;
326 + return 20000 * 1000;
328 bcma_warn(bus, "No ALP clock specified for %04X device, pmu rev. %d, using default %d Hz\n",
329 bus->chipinfo.id, cc->pmu.rev, BCMA_CC_PMU_ALP_CLOCK);
330 @@ -373,7 +512,7 @@ void bcma_pmu_spuravoid_pllupdate(struct
331 tmp |= (bcm5357_bcm43236_ndiv[spuravoid]) << BCMA_CC_PMU1_PLL0_PC2_NDIV_INT_SHIFT;
332 bcma_cc_write32(cc, BCMA_CC_PLLCTL_DATA, tmp);
335 + tmp = BCMA_CC_PMU_CTL_PLL_UPD;
338 case BCMA_CHIP_ID_BCM4331:
339 @@ -394,7 +533,7 @@ void bcma_pmu_spuravoid_pllupdate(struct
340 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
344 + tmp = BCMA_CC_PMU_CTL_PLL_UPD;
347 case BCMA_CHIP_ID_BCM43224:
348 @@ -427,7 +566,7 @@ void bcma_pmu_spuravoid_pllupdate(struct
349 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
353 + tmp = BCMA_CC_PMU_CTL_PLL_UPD;
356 case BCMA_CHIP_ID_BCM4716:
357 @@ -461,7 +600,7 @@ void bcma_pmu_spuravoid_pllupdate(struct
362 + tmp = BCMA_CC_PMU_CTL_PLL_UPD | BCMA_CC_PMU_CTL_NOILPONW;
365 case BCMA_CHIP_ID_BCM43227:
366 @@ -497,7 +636,7 @@ void bcma_pmu_spuravoid_pllupdate(struct
367 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
371 + tmp = BCMA_CC_PMU_CTL_PLL_UPD;
374 bcma_err(bus, "Unknown spuravoidance settings for chip 0x%04X, not changing PLL\n",
375 --- a/drivers/bcma/driver_chipcommon_sflash.c
376 +++ b/drivers/bcma/driver_chipcommon_sflash.c
377 @@ -30,7 +30,7 @@ struct bcma_sflash_tbl_e {
381 -static struct bcma_sflash_tbl_e bcma_sflash_st_tbl[] = {
382 +static const struct bcma_sflash_tbl_e bcma_sflash_st_tbl[] = {
383 { "M25P20", 0x11, 0x10000, 4, },
384 { "M25P40", 0x12, 0x10000, 8, },
386 @@ -41,7 +41,7 @@ static struct bcma_sflash_tbl_e bcma_sfl
390 -static struct bcma_sflash_tbl_e bcma_sflash_sst_tbl[] = {
391 +static const struct bcma_sflash_tbl_e bcma_sflash_sst_tbl[] = {
392 { "SST25WF512", 1, 0x1000, 16, },
393 { "SST25VF512", 0x48, 0x1000, 16, },
394 { "SST25WF010", 2, 0x1000, 32, },
395 @@ -59,7 +59,7 @@ static struct bcma_sflash_tbl_e bcma_sfl
399 -static struct bcma_sflash_tbl_e bcma_sflash_at_tbl[] = {
400 +static const struct bcma_sflash_tbl_e bcma_sflash_at_tbl[] = {
401 { "AT45DB011", 0xc, 256, 512, },
402 { "AT45DB021", 0x14, 256, 1024, },
403 { "AT45DB041", 0x1c, 256, 2048, },
404 @@ -89,7 +89,7 @@ int bcma_sflash_init(struct bcma_drv_cc
406 struct bcma_bus *bus = cc->core->bus;
407 struct bcma_sflash *sflash = &cc->sflash;
408 - struct bcma_sflash_tbl_e *e;
409 + const struct bcma_sflash_tbl_e *e;
412 switch (cc->capabilities & BCMA_CC_CAP_FLASHT) {
413 --- a/drivers/bcma/host_pci.c
414 +++ b/drivers/bcma/host_pci.c
415 @@ -275,6 +275,7 @@ static DEFINE_PCI_DEVICE_TABLE(bcma_pci_
416 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4357) },
417 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4358) },
418 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4359) },
419 + { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4365) },
420 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4727) },
423 --- a/drivers/bcma/main.c
424 +++ b/drivers/bcma/main.c
425 @@ -93,6 +93,25 @@ struct bcma_device *bcma_find_core_unit(
429 +bool bcma_wait_value(struct bcma_device *core, u16 reg, u32 mask, u32 value,
432 + unsigned long deadline = jiffies + timeout;
436 + val = bcma_read32(core, reg);
437 + if ((val & mask) == value)
441 + } while (!time_after_eq(jiffies, deadline));
443 + bcma_warn(core->bus, "Timeout waiting for register 0x%04X!\n", reg);
448 static void bcma_release_core_dev(struct device *dev)
450 struct bcma_device *core = container_of(dev, struct bcma_device, dev);
451 @@ -120,6 +139,11 @@ static int bcma_register_cores(struct bc
455 + /* Only first GMAC core on BCM4706 is connected and working */
456 + if (core->id.id == BCMA_CORE_4706_MAC_GBIT &&
457 + core->core_unit > 0)
460 core->dev.release = bcma_release_core_dev;
461 core->dev.bus = &bcma_bus_type;
462 dev_set_name(&core->dev, "bcma%d:%d", bus->num, dev_id);
463 --- a/drivers/bcma/scan.c
464 +++ b/drivers/bcma/scan.c
465 @@ -84,6 +84,8 @@ static const struct bcma_device_id_name
466 { BCMA_CORE_I2S, "I2S" },
467 { BCMA_CORE_SDR_DDR1_MEM_CTL, "SDR/DDR1 Memory Controller" },
468 { BCMA_CORE_SHIM, "SHIM" },
469 + { BCMA_CORE_PCIE2, "PCIe Gen2" },
470 + { BCMA_CORE_ARM_CR4, "ARM CR4" },
471 { BCMA_CORE_DEFAULT, "Default" },
474 @@ -137,19 +139,19 @@ static void bcma_scan_switch_core(struct
478 -static u32 bcma_erom_get_ent(struct bcma_bus *bus, u32 **eromptr)
479 +static u32 bcma_erom_get_ent(struct bcma_bus *bus, u32 __iomem **eromptr)
481 u32 ent = readl(*eromptr);
486 -static void bcma_erom_push_ent(u32 **eromptr)
487 +static void bcma_erom_push_ent(u32 __iomem **eromptr)
492 -static s32 bcma_erom_get_ci(struct bcma_bus *bus, u32 **eromptr)
493 +static s32 bcma_erom_get_ci(struct bcma_bus *bus, u32 __iomem **eromptr)
495 u32 ent = bcma_erom_get_ent(bus, eromptr);
496 if (!(ent & SCAN_ER_VALID))
497 @@ -159,14 +161,14 @@ static s32 bcma_erom_get_ci(struct bcma_
501 -static bool bcma_erom_is_end(struct bcma_bus *bus, u32 **eromptr)
502 +static bool bcma_erom_is_end(struct bcma_bus *bus, u32 __iomem **eromptr)
504 u32 ent = bcma_erom_get_ent(bus, eromptr);
505 bcma_erom_push_ent(eromptr);
506 return (ent == (SCAN_ER_TAG_END | SCAN_ER_VALID));
509 -static bool bcma_erom_is_bridge(struct bcma_bus *bus, u32 **eromptr)
510 +static bool bcma_erom_is_bridge(struct bcma_bus *bus, u32 __iomem **eromptr)
512 u32 ent = bcma_erom_get_ent(bus, eromptr);
513 bcma_erom_push_ent(eromptr);
514 @@ -175,7 +177,7 @@ static bool bcma_erom_is_bridge(struct b
515 ((ent & SCAN_ADDR_TYPE) == SCAN_ADDR_TYPE_BRIDGE));
518 -static void bcma_erom_skip_component(struct bcma_bus *bus, u32 **eromptr)
519 +static void bcma_erom_skip_component(struct bcma_bus *bus, u32 __iomem **eromptr)
523 @@ -189,7 +191,7 @@ static void bcma_erom_skip_component(str
524 bcma_erom_push_ent(eromptr);
527 -static s32 bcma_erom_get_mst_port(struct bcma_bus *bus, u32 **eromptr)
528 +static s32 bcma_erom_get_mst_port(struct bcma_bus *bus, u32 __iomem **eromptr)
530 u32 ent = bcma_erom_get_ent(bus, eromptr);
531 if (!(ent & SCAN_ER_VALID))
532 @@ -199,7 +201,7 @@ static s32 bcma_erom_get_mst_port(struct
536 -static s32 bcma_erom_get_addr_desc(struct bcma_bus *bus, u32 **eromptr,
537 +static s32 bcma_erom_get_addr_desc(struct bcma_bus *bus, u32 __iomem **eromptr,
540 u32 addrl, addrh, sizel, sizeh = 0;
541 --- a/drivers/bcma/sprom.c
542 +++ b/drivers/bcma/sprom.c
543 @@ -72,12 +72,12 @@ fail:
545 **************************************************/
547 -static void bcma_sprom_read(struct bcma_bus *bus, u16 offset, u16 *sprom)
548 +static void bcma_sprom_read(struct bcma_bus *bus, u16 offset, u16 *sprom,
552 - for (i = 0; i < SSB_SPROMSIZE_WORDS_R4; i++)
553 - sprom[i] = bcma_read16(bus->drv_cc.core,
555 + for (i = 0; i < words; i++)
556 + sprom[i] = bcma_read16(bus->drv_cc.core, offset + (i * 2));
559 /**************************************************
560 @@ -124,29 +124,29 @@ static inline u8 bcma_crc8(u8 crc, u8 da
561 return t[crc ^ data];
564 -static u8 bcma_sprom_crc(const u16 *sprom)
565 +static u8 bcma_sprom_crc(const u16 *sprom, size_t words)
570 - for (word = 0; word < SSB_SPROMSIZE_WORDS_R4 - 1; word++) {
571 + for (word = 0; word < words - 1; word++) {
572 crc = bcma_crc8(crc, sprom[word] & 0x00FF);
573 crc = bcma_crc8(crc, (sprom[word] & 0xFF00) >> 8);
575 - crc = bcma_crc8(crc, sprom[SSB_SPROMSIZE_WORDS_R4 - 1] & 0x00FF);
576 + crc = bcma_crc8(crc, sprom[words - 1] & 0x00FF);
582 -static int bcma_sprom_check_crc(const u16 *sprom)
583 +static int bcma_sprom_check_crc(const u16 *sprom, size_t words)
589 - crc = bcma_sprom_crc(sprom);
590 - tmp = sprom[SSB_SPROMSIZE_WORDS_R4 - 1] & SSB_SPROM_REVISION_CRC;
591 + crc = bcma_sprom_crc(sprom, words);
592 + tmp = sprom[words - 1] & SSB_SPROM_REVISION_CRC;
593 expected_crc = tmp >> SSB_SPROM_REVISION_CRC_SHIFT;
594 if (crc != expected_crc)
596 @@ -154,21 +154,25 @@ static int bcma_sprom_check_crc(const u1
600 -static int bcma_sprom_valid(const u16 *sprom)
601 +static int bcma_sprom_valid(struct bcma_bus *bus, const u16 *sprom,
607 - err = bcma_sprom_check_crc(sprom);
608 + err = bcma_sprom_check_crc(sprom, words);
612 - revision = sprom[SSB_SPROMSIZE_WORDS_R4 - 1] & SSB_SPROM_REVISION_REV;
613 - if (revision != 8 && revision != 9) {
614 + revision = sprom[words - 1] & SSB_SPROM_REVISION_REV;
615 + if (revision != 8 && revision != 9 && revision != 10) {
616 pr_err("Unsupported SPROM revision: %d\n", revision);
620 + bus->sprom.revision = revision;
621 + bcma_debug(bus, "Found SPROM revision %d\n", revision);
626 @@ -208,15 +212,13 @@ static void bcma_sprom_extract_r8(struct
627 BUILD_BUG_ON(ARRAY_SIZE(pwr_info_offset) !=
628 ARRAY_SIZE(bus->sprom.core_pwr_info));
630 - bus->sprom.revision = sprom[SSB_SPROMSIZE_WORDS_R4 - 1] &
631 - SSB_SPROM_REVISION_REV;
633 for (i = 0; i < 3; i++) {
634 v = sprom[SPOFF(SSB_SPROM8_IL0MAC) + i];
635 *(((__be16 *)bus->sprom.il0mac) + i) = cpu_to_be16(v);
638 SPEX(board_rev, SSB_SPROM8_BOARDREV, ~0, 0);
639 + SPEX(board_type, SSB_SPROM1_SPID, ~0, 0);
641 SPEX(txpid2g[0], SSB_SPROM4_TXPID2G01, SSB_SPROM4_TXPID2G0,
642 SSB_SPROM4_TXPID2G0_SHIFT);
643 @@ -501,7 +503,7 @@ static bool bcma_sprom_onchip_available(
644 case BCMA_CHIP_ID_BCM4331:
645 present = chip_status & BCMA_CC_CHIPST_4331_OTP_PRESENT;
648 + case BCMA_CHIP_ID_BCM43142:
649 case BCMA_CHIP_ID_BCM43224:
650 case BCMA_CHIP_ID_BCM43225:
651 /* for these chips OTP is always available */
652 @@ -549,7 +551,9 @@ int bcma_sprom_get(struct bcma_bus *bus)
654 u16 offset = BCMA_CC_SPROM;
657 + size_t sprom_sizes[] = { SSB_SPROMSIZE_WORDS_R4,
658 + SSB_SPROMSIZE_WORDS_R10, };
661 if (!bus->drv_cc.core)
663 @@ -578,32 +582,37 @@ int bcma_sprom_get(struct bcma_bus *bus)
667 - sprom = kcalloc(SSB_SPROMSIZE_WORDS_R4, sizeof(u16),
672 if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4331 ||
673 bus->chipinfo.id == BCMA_CHIP_ID_BCM43431)
674 bcma_chipco_bcm4331_ext_pa_lines_ctl(&bus->drv_cc, false);
676 bcma_debug(bus, "SPROM offset 0x%x\n", offset);
677 - bcma_sprom_read(bus, offset, sprom);
678 + for (i = 0; i < ARRAY_SIZE(sprom_sizes); i++) {
679 + size_t words = sprom_sizes[i];
681 + sprom = kcalloc(words, sizeof(u16), GFP_KERNEL);
685 + bcma_sprom_read(bus, offset, sprom, words);
686 + err = bcma_sprom_valid(bus, sprom, words);
693 if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4331 ||
694 bus->chipinfo.id == BCMA_CHIP_ID_BCM43431)
695 bcma_chipco_bcm4331_ext_pa_lines_ctl(&bus->drv_cc, true);
697 - err = bcma_sprom_valid(sprom);
699 - bcma_warn(bus, "invalid sprom read from the PCIe card, try to use fallback sprom\n");
700 + bcma_warn(bus, "Invalid SPROM read from the PCIe card, trying to use fallback SPROM\n");
701 err = bcma_fill_sprom_with_fallback(bus, &bus->sprom);
704 + bcma_sprom_extract_r8(bus, sprom);
708 - bcma_sprom_extract_r8(bus, sprom);
714 --- a/include/linux/bcma/bcma.h
715 +++ b/include/linux/bcma/bcma.h
716 @@ -134,12 +134,17 @@ struct bcma_host_ops {
717 #define BCMA_CORE_I2S 0x834
718 #define BCMA_CORE_SDR_DDR1_MEM_CTL 0x835 /* SDR/DDR1 memory controller core */
719 #define BCMA_CORE_SHIM 0x837 /* SHIM component in ubus/6362 */
720 +#define BCMA_CORE_PHY_AC 0x83B
721 +#define BCMA_CORE_PCIE2 0x83C /* PCI Express Gen2 */
722 +#define BCMA_CORE_USB30_DEV 0x83D
723 +#define BCMA_CORE_ARM_CR4 0x83E
724 #define BCMA_CORE_DEFAULT 0xFFF
726 #define BCMA_MAX_NR_CORES 16
728 /* Chip IDs of PCIe devices */
729 #define BCMA_CHIP_ID_BCM4313 0x4313
730 +#define BCMA_CHIP_ID_BCM43142 43142
731 #define BCMA_CHIP_ID_BCM43224 43224
732 #define BCMA_PKG_ID_BCM43224_FAB_CSM 0x8
733 #define BCMA_PKG_ID_BCM43224_FAB_SMIC 0xa
734 @@ -173,6 +178,60 @@ struct bcma_host_ops {
735 #define BCMA_CHIP_ID_BCM53572 53572
736 #define BCMA_PKG_ID_BCM47188 9
738 +/* Board types (on PCI usually equals to the subsystem dev id) */
740 +#define BCMA_BOARD_TYPE_BCM94313BU 0X050F
741 +#define BCMA_BOARD_TYPE_BCM94313HM 0X0510
742 +#define BCMA_BOARD_TYPE_BCM94313EPA 0X0511
743 +#define BCMA_BOARD_TYPE_BCM94313HMG 0X051C
745 +#define BCMA_BOARD_TYPE_BCM94716NR2 0X04CD
747 +#define BCMA_BOARD_TYPE_BCM943224X21 0X056E
748 +#define BCMA_BOARD_TYPE_BCM943224X21_FCC 0X00D1
749 +#define BCMA_BOARD_TYPE_BCM943224X21B 0X00E9
750 +#define BCMA_BOARD_TYPE_BCM943224M93 0X008B
751 +#define BCMA_BOARD_TYPE_BCM943224M93A 0X0090
752 +#define BCMA_BOARD_TYPE_BCM943224X16 0X0093
753 +#define BCMA_BOARD_TYPE_BCM94322X9 0X008D
754 +#define BCMA_BOARD_TYPE_BCM94322M35E 0X008E
756 +#define BCMA_BOARD_TYPE_BCM943228BU8 0X0540
757 +#define BCMA_BOARD_TYPE_BCM943228BU9 0X0541
758 +#define BCMA_BOARD_TYPE_BCM943228BU 0X0542
759 +#define BCMA_BOARD_TYPE_BCM943227HM4L 0X0543
760 +#define BCMA_BOARD_TYPE_BCM943227HMB 0X0544
761 +#define BCMA_BOARD_TYPE_BCM943228HM4L 0X0545
762 +#define BCMA_BOARD_TYPE_BCM943228SD 0X0573
764 +#define BCMA_BOARD_TYPE_BCM94331X19 0X00D6
765 +#define BCMA_BOARD_TYPE_BCM94331X28 0X00E4
766 +#define BCMA_BOARD_TYPE_BCM94331X28B 0X010E
767 +#define BCMA_BOARD_TYPE_BCM94331PCIEBT3AX 0X00E4
768 +#define BCMA_BOARD_TYPE_BCM94331X12_2G 0X00EC
769 +#define BCMA_BOARD_TYPE_BCM94331X12_5G 0X00ED
770 +#define BCMA_BOARD_TYPE_BCM94331X29B 0X00EF
771 +#define BCMA_BOARD_TYPE_BCM94331CSAX 0X00EF
772 +#define BCMA_BOARD_TYPE_BCM94331X19C 0X00F5
773 +#define BCMA_BOARD_TYPE_BCM94331X33 0X00F4
774 +#define BCMA_BOARD_TYPE_BCM94331BU 0X0523
775 +#define BCMA_BOARD_TYPE_BCM94331S9BU 0X0524
776 +#define BCMA_BOARD_TYPE_BCM94331MC 0X0525
777 +#define BCMA_BOARD_TYPE_BCM94331MCI 0X0526
778 +#define BCMA_BOARD_TYPE_BCM94331PCIEBT4 0X0527
779 +#define BCMA_BOARD_TYPE_BCM94331HM 0X0574
780 +#define BCMA_BOARD_TYPE_BCM94331PCIEDUAL 0X059B
781 +#define BCMA_BOARD_TYPE_BCM94331MCH5 0X05A9
782 +#define BCMA_BOARD_TYPE_BCM94331CS 0X05C6
783 +#define BCMA_BOARD_TYPE_BCM94331CD 0X05DA
785 +#define BCMA_BOARD_TYPE_BCM953572BU 0X058D
786 +#define BCMA_BOARD_TYPE_BCM953572NR2 0X058E
787 +#define BCMA_BOARD_TYPE_BCM947188NR2 0X058F
788 +#define BCMA_BOARD_TYPE_BCM953572SDRNR2 0X0590
790 +#define BCMA_BOARD_TYPE_BCM943142HM 0X05E0
793 struct bcma_bus *bus;
794 struct bcma_device_id id;
795 --- a/include/linux/bcma/bcma_driver_chipcommon.h
796 +++ b/include/linux/bcma/bcma_driver_chipcommon.h
798 #define BCMA_CC_CHIPST_4706_MIPS_BENDIAN BIT(3) /* 0: little, 1: big endian */
799 #define BCMA_CC_CHIPST_4706_PCIE1_DISABLE BIT(5) /* PCIE1 enable strap pin */
800 #define BCMA_CC_CHIPST_5357_NAND_BOOT BIT(4) /* NAND boot, valid for CC rev 38 and/or BCM5357 */
801 +#define BCMA_CC_CHIPST_4360_XTAL_40MZ 0x00000001
802 #define BCMA_CC_JCMD 0x0030 /* Rev >= 10 only */
803 #define BCMA_CC_JCMD_START 0x80000000
804 #define BCMA_CC_JCMD_BUSY 0x80000000
806 #define BCMA_CC_PMU_CTL 0x0600 /* PMU control */
807 #define BCMA_CC_PMU_CTL_ILP_DIV 0xFFFF0000 /* ILP div mask */
808 #define BCMA_CC_PMU_CTL_ILP_DIV_SHIFT 16
809 +#define BCMA_CC_PMU_CTL_RES 0x00006000 /* reset control mask */
810 +#define BCMA_CC_PMU_CTL_RES_SHIFT 13
811 +#define BCMA_CC_PMU_CTL_RES_RELOAD 0x2 /* reload POR values */
812 #define BCMA_CC_PMU_CTL_PLL_UPD 0x00000400
813 #define BCMA_CC_PMU_CTL_NOILPONW 0x00000200 /* No ILP on wait */
814 #define BCMA_CC_PMU_CTL_HTREQEN 0x00000100 /* HT req enable */
816 #define BCMA_CC_PMU_CAP 0x0604 /* PMU capabilities */
817 #define BCMA_CC_PMU_CAP_REVISION 0x000000FF /* Revision mask */
818 #define BCMA_CC_PMU_STAT 0x0608 /* PMU status */
819 +#define BCMA_CC_PMU_STAT_EXT_LPO_AVAIL 0x00000100
820 +#define BCMA_CC_PMU_STAT_WDRESET 0x00000080
821 #define BCMA_CC_PMU_STAT_INTPEND 0x00000040 /* Interrupt pending */
822 #define BCMA_CC_PMU_STAT_SBCLKST 0x00000030 /* Backplane clock status? */
823 #define BCMA_CC_PMU_STAT_HAVEALP 0x00000008 /* ALP available */
825 #define BCMA_CC_REGCTL_DATA 0x065C
826 #define BCMA_CC_PLLCTL_ADDR 0x0660
827 #define BCMA_CC_PLLCTL_DATA 0x0664
828 +#define BCMA_CC_PMU_STRAPOPT 0x0668 /* (corerev >= 28) */
829 +#define BCMA_CC_PMU_XTAL_FREQ 0x066C /* (pmurev >= 10) */
830 +#define BCMA_CC_PMU_XTAL_FREQ_ILPCTL_MASK 0x00001FFF
831 +#define BCMA_CC_PMU_XTAL_FREQ_MEASURE_MASK 0x80000000
832 +#define BCMA_CC_PMU_XTAL_FREQ_MEASURE_SHIFT 31
833 #define BCMA_CC_SPROM 0x0800 /* SPROM beginning */
834 /* NAND flash MLC controller registers (corerev >= 38) */
835 #define BCMA_CC_NAND_REVISION 0x0C00
837 #define BCMA_CC_PMU6_4706_PROC_NDIV_MODE_MASK 0x00000007
838 #define BCMA_CC_PMU6_4706_PROC_NDIV_MODE_SHIFT 0
841 +#define BCMA_CC_PMU15_PLL_PLLCTL0 0
842 +#define BCMA_CC_PMU15_PLL_PC0_CLKSEL_MASK 0x00000003
843 +#define BCMA_CC_PMU15_PLL_PC0_CLKSEL_SHIFT 0
844 +#define BCMA_CC_PMU15_PLL_PC0_FREQTGT_MASK 0x003FFFFC
845 +#define BCMA_CC_PMU15_PLL_PC0_FREQTGT_SHIFT 2
846 +#define BCMA_CC_PMU15_PLL_PC0_PRESCALE_MASK 0x00C00000
847 +#define BCMA_CC_PMU15_PLL_PC0_PRESCALE_SHIFT 22
848 +#define BCMA_CC_PMU15_PLL_PC0_KPCTRL_MASK 0x07000000
849 +#define BCMA_CC_PMU15_PLL_PC0_KPCTRL_SHIFT 24
850 +#define BCMA_CC_PMU15_PLL_PC0_FCNTCTRL_MASK 0x38000000
851 +#define BCMA_CC_PMU15_PLL_PC0_FCNTCTRL_SHIFT 27
852 +#define BCMA_CC_PMU15_PLL_PC0_FDCMODE_MASK 0x40000000
853 +#define BCMA_CC_PMU15_PLL_PC0_FDCMODE_SHIFT 30
854 +#define BCMA_CC_PMU15_PLL_PC0_CTRLBIAS_MASK 0x80000000
855 +#define BCMA_CC_PMU15_PLL_PC0_CTRLBIAS_SHIFT 31
857 /* ALP clock on pre-PMU chips */
858 #define BCMA_CC_PMU_ALP_CLOCK 20000000
859 /* HT clock for systems with PMU-enabled chipcommon */
861 #define BCMA_CHIPCTL_5357_I2S_PINS_ENABLE BIT(18)
862 #define BCMA_CHIPCTL_5357_I2CSPI_PINS_ENABLE BIT(19)
864 +#define BCMA_RES_4314_LPLDO_PU BIT(0)
865 +#define BCMA_RES_4314_PMU_SLEEP_DIS BIT(1)
866 +#define BCMA_RES_4314_PMU_BG_PU BIT(2)
867 +#define BCMA_RES_4314_CBUCK_LPOM_PU BIT(3)
868 +#define BCMA_RES_4314_CBUCK_PFM_PU BIT(4)
869 +#define BCMA_RES_4314_CLDO_PU BIT(5)
870 +#define BCMA_RES_4314_LPLDO2_LVM BIT(6)
871 +#define BCMA_RES_4314_WL_PMU_PU BIT(7)
872 +#define BCMA_RES_4314_LNLDO_PU BIT(8)
873 +#define BCMA_RES_4314_LDO3P3_PU BIT(9)
874 +#define BCMA_RES_4314_OTP_PU BIT(10)
875 +#define BCMA_RES_4314_XTAL_PU BIT(11)
876 +#define BCMA_RES_4314_WL_PWRSW_PU BIT(12)
877 +#define BCMA_RES_4314_LQ_AVAIL BIT(13)
878 +#define BCMA_RES_4314_LOGIC_RET BIT(14)
879 +#define BCMA_RES_4314_MEM_SLEEP BIT(15)
880 +#define BCMA_RES_4314_MACPHY_RET BIT(16)
881 +#define BCMA_RES_4314_WL_CORE_READY BIT(17)
882 +#define BCMA_RES_4314_ILP_REQ BIT(18)
883 +#define BCMA_RES_4314_ALP_AVAIL BIT(19)
884 +#define BCMA_RES_4314_MISC_PWRSW_PU BIT(20)
885 +#define BCMA_RES_4314_SYNTH_PWRSW_PU BIT(21)
886 +#define BCMA_RES_4314_RX_PWRSW_PU BIT(22)
887 +#define BCMA_RES_4314_RADIO_PU BIT(23)
888 +#define BCMA_RES_4314_VCO_LDO_PU BIT(24)
889 +#define BCMA_RES_4314_AFE_LDO_PU BIT(25)
890 +#define BCMA_RES_4314_RX_LDO_PU BIT(26)
891 +#define BCMA_RES_4314_TX_LDO_PU BIT(27)
892 +#define BCMA_RES_4314_HT_AVAIL BIT(28)
893 +#define BCMA_RES_4314_MACPHY_CLK_AVAIL BIT(29)
895 /* Data for the PMU, if available.
896 * Check availability with ((struct bcma_chipcommon)->capabilities & BCMA_CC_CAP_PMU)
898 @@ -607,6 +666,8 @@ void bcma_chipco_bcm4331_ext_pa_lines_ct
900 extern u32 bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc, u32 ticks);
902 +extern u32 bcma_chipco_get_alp_clock(struct bcma_drv_cc *cc);
904 void bcma_chipco_irq_mask(struct bcma_drv_cc *cc, u32 mask, u32 value);
906 u32 bcma_chipco_irq_status(struct bcma_drv_cc *cc, u32 mask);
907 --- a/include/linux/bcma/bcma_regs.h
908 +++ b/include/linux/bcma/bcma_regs.h
910 #define BCMA_IOST_BIST_DONE 0x8000
911 #define BCMA_RESET_CTL 0x0800
912 #define BCMA_RESET_CTL_RESET 0x0001
913 +#define BCMA_RESET_ST 0x0804
915 /* BCMA PCI config space registers. */
916 #define BCMA_PCI_PMCSR 0x44