1 --- a/arch/mips/bcm47xx/serial.c
2 +++ b/arch/mips/bcm47xx/serial.c
3 @@ -62,7 +62,7 @@ static int __init uart8250_init_bcma(voi
5 p->mapbase = (unsigned int) bcma_port->regs;
6 p->membase = (void *) bcma_port->regs;
7 - p->irq = bcma_port->irq + 2;
8 + p->irq = bcma_port->irq;
9 p->uartclk = bcma_port->baud_base;
10 p->regshift = bcma_port->reg_shift;
12 --- a/drivers/bcma/Kconfig
13 +++ b/drivers/bcma/Kconfig
14 @@ -26,6 +26,7 @@ config BCMA_HOST_PCI_POSSIBLE
16 bool "Support for BCMA on PCI-host bus"
17 depends on BCMA_HOST_PCI_POSSIBLE
20 config BCMA_DRIVER_PCI_HOSTMODE
21 bool "Driver for PCI core working in hostmode"
22 @@ -48,12 +49,12 @@ config BCMA_DRIVER_MIPS
26 - depends on BCMA_DRIVER_MIPS && BROKEN
27 + depends on BCMA_DRIVER_MIPS
32 - depends on BCMA_DRIVER_MIPS && BROKEN
33 + depends on BCMA_DRIVER_MIPS
36 config BCMA_DRIVER_GMAC_CMN
37 @@ -65,6 +66,14 @@ config BCMA_DRIVER_GMAC_CMN
41 +config BCMA_DRIVER_GPIO
42 + bool "BCMA GPIO driver"
43 + depends on BCMA && GPIOLIB
45 + Driver to provide access to the GPIO pins of the bcma bus.
52 --- a/drivers/bcma/Makefile
53 +++ b/drivers/bcma/Makefile
54 @@ -6,6 +6,7 @@ bcma-y += driver_pci.o
55 bcma-$(CONFIG_BCMA_DRIVER_PCI_HOSTMODE) += driver_pci_host.o
56 bcma-$(CONFIG_BCMA_DRIVER_MIPS) += driver_mips.o
57 bcma-$(CONFIG_BCMA_DRIVER_GMAC_CMN) += driver_gmac_cmn.o
58 +bcma-$(CONFIG_BCMA_DRIVER_GPIO) += driver_gpio.o
59 bcma-$(CONFIG_BCMA_HOST_PCI) += host_pci.o
60 bcma-$(CONFIG_BCMA_HOST_SOC) += host_soc.o
61 obj-$(CONFIG_BCMA) += bcma.o
62 --- a/drivers/bcma/bcma_private.h
63 +++ b/drivers/bcma/bcma_private.h
68 +bool bcma_wait_value(struct bcma_device *core, u16 reg, u32 mask, u32 value,
70 int __devinit bcma_bus_register(struct bcma_bus *bus);
71 void bcma_bus_unregister(struct bcma_bus *bus);
72 int __init bcma_bus_early_register(struct bcma_bus *bus,
73 @@ -31,6 +33,8 @@ int __init bcma_bus_early_register(struc
74 int bcma_bus_suspend(struct bcma_bus *bus);
75 int bcma_bus_resume(struct bcma_bus *bus);
77 +struct bcma_device *bcma_find_core_unit(struct bcma_bus *bus, u16 coreid,
81 int bcma_bus_scan(struct bcma_bus *bus);
82 @@ -45,15 +49,17 @@ int bcma_sprom_get(struct bcma_bus *bus)
83 /* driver_chipcommon.c */
84 #ifdef CONFIG_BCMA_DRIVER_MIPS
85 void bcma_chipco_serial_init(struct bcma_drv_cc *cc);
86 +extern struct platform_device bcma_pflash_dev;
87 #endif /* CONFIG_BCMA_DRIVER_MIPS */
89 /* driver_chipcommon_pmu.c */
90 -u32 bcma_pmu_alp_clock(struct bcma_drv_cc *cc);
91 -u32 bcma_pmu_get_clockcpu(struct bcma_drv_cc *cc);
92 +u32 bcma_pmu_get_alp_clock(struct bcma_drv_cc *cc);
93 +u32 bcma_pmu_get_cpu_clock(struct bcma_drv_cc *cc);
95 #ifdef CONFIG_BCMA_SFLASH
96 /* driver_chipcommon_sflash.c */
97 int bcma_sflash_init(struct bcma_drv_cc *cc);
98 +extern struct platform_device bcma_sflash_dev;
100 static inline int bcma_sflash_init(struct bcma_drv_cc *cc)
102 @@ -65,6 +71,7 @@ static inline int bcma_sflash_init(struc
103 #ifdef CONFIG_BCMA_NFLASH
104 /* driver_chipcommon_nflash.c */
105 int bcma_nflash_init(struct bcma_drv_cc *cc);
106 +extern struct platform_device bcma_nflash_dev;
108 static inline int bcma_nflash_init(struct bcma_drv_cc *cc)
110 @@ -82,9 +89,26 @@ extern void __exit bcma_host_pci_exit(vo
112 u32 bcma_pcie_read(struct bcma_drv_pci *pc, u32 address);
114 +extern int bcma_chipco_watchdog_register(struct bcma_drv_cc *cc);
116 #ifdef CONFIG_BCMA_DRIVER_PCI_HOSTMODE
117 bool __devinit bcma_core_pci_is_in_hostmode(struct bcma_drv_pci *pc);
118 void __devinit bcma_core_pci_hostmode_init(struct bcma_drv_pci *pc);
119 #endif /* CONFIG_BCMA_DRIVER_PCI_HOSTMODE */
121 +#ifdef CONFIG_BCMA_DRIVER_GPIO
123 +int bcma_gpio_init(struct bcma_drv_cc *cc);
124 +int bcma_gpio_unregister(struct bcma_drv_cc *cc);
126 +static inline int bcma_gpio_init(struct bcma_drv_cc *cc)
130 +static inline int bcma_gpio_unregister(struct bcma_drv_cc *cc)
134 +#endif /* CONFIG_BCMA_DRIVER_GPIO */
137 --- a/drivers/bcma/core.c
138 +++ b/drivers/bcma/core.c
140 #include <linux/export.h>
141 #include <linux/bcma/bcma.h>
143 +static bool bcma_core_wait_value(struct bcma_device *core, u16 reg, u32 mask,
144 + u32 value, int timeout)
146 + unsigned long deadline = jiffies + timeout;
150 + val = bcma_aread32(core, reg);
151 + if ((val & mask) == value)
155 + } while (!time_after_eq(jiffies, deadline));
157 + bcma_warn(core->bus, "Timeout waiting for register 0x%04X!\n", reg);
162 bool bcma_core_is_enabled(struct bcma_device *core)
164 if ((bcma_aread32(core, BCMA_IOCTL) & (BCMA_IOCTL_CLK | BCMA_IOCTL_FGC))
165 @@ -25,13 +44,15 @@ void bcma_core_disable(struct bcma_devic
166 if (bcma_aread32(core, BCMA_RESET_CTL) & BCMA_RESET_CTL_RESET)
169 - bcma_awrite32(core, BCMA_IOCTL, flags);
170 - bcma_aread32(core, BCMA_IOCTL);
172 + bcma_core_wait_value(core, BCMA_RESET_ST, ~0, 0, 300);
174 bcma_awrite32(core, BCMA_RESET_CTL, BCMA_RESET_CTL_RESET);
175 bcma_aread32(core, BCMA_RESET_CTL);
178 + bcma_awrite32(core, BCMA_IOCTL, flags);
179 + bcma_aread32(core, BCMA_IOCTL);
182 EXPORT_SYMBOL_GPL(bcma_core_disable);
184 @@ -43,6 +64,7 @@ int bcma_core_enable(struct bcma_device
185 bcma_aread32(core, BCMA_IOCTL);
187 bcma_awrite32(core, BCMA_RESET_CTL, 0);
188 + bcma_aread32(core, BCMA_RESET_CTL);
191 bcma_awrite32(core, BCMA_IOCTL, (BCMA_IOCTL_CLK | flags));
192 @@ -65,7 +87,7 @@ void bcma_core_set_clockmode(struct bcma
194 case BCMA_CLKMODE_FAST:
195 bcma_set32(core, BCMA_CLKCTLST, BCMA_CLKCTLST_FORCEHT);
197 + usleep_range(64, 300);
198 for (i = 0; i < 1500; i++) {
199 if (bcma_read32(core, BCMA_CLKCTLST) &
200 BCMA_CLKCTLST_HAVEHT) {
201 @@ -104,7 +126,13 @@ void bcma_core_pll_ctl(struct bcma_devic
203 bcma_err(core->bus, "PLL enable timeout\n");
205 - bcma_warn(core->bus, "Disabling PLL not supported yet!\n");
207 + * Mask the PLL but don't wait for it to be disabled. PLL may be
208 + * shared between cores and will be still up if there is another
211 + bcma_mask32(core, BCMA_CLKCTLST, ~req);
212 + bcma_read32(core, BCMA_CLKCTLST);
215 EXPORT_SYMBOL_GPL(bcma_core_pll_ctl);
216 --- a/drivers/bcma/driver_chipcommon.c
217 +++ b/drivers/bcma/driver_chipcommon.c
220 * Copyright 2005, Broadcom Corporation
221 * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
222 + * Copyright 2012, Hauke Mehrtens <hauke@hauke-m.de>
224 * Licensed under the GNU/GPL. See COPYING for details.
227 #include "bcma_private.h"
228 +#include <linux/bcm47xx_wdt.h>
229 #include <linux/export.h>
230 +#include <linux/platform_device.h>
231 #include <linux/bcma/bcma.h>
233 static inline u32 bcma_cc_write32_masked(struct bcma_drv_cc *cc, u16 offset,
234 @@ -22,23 +25,130 @@ static inline u32 bcma_cc_write32_masked
238 -void bcma_core_chipcommon_init(struct bcma_drv_cc *cc)
239 +u32 bcma_chipco_get_alp_clock(struct bcma_drv_cc *cc)
242 - u32 leddc_off = 90;
243 + if (cc->capabilities & BCMA_CC_CAP_PMU)
244 + return bcma_pmu_get_alp_clock(cc);
246 - if (cc->setup_done)
249 +EXPORT_SYMBOL_GPL(bcma_chipco_get_alp_clock);
251 +static u32 bcma_chipco_watchdog_get_max_timer(struct bcma_drv_cc *cc)
253 + struct bcma_bus *bus = cc->core->bus;
256 + if (cc->capabilities & BCMA_CC_CAP_PMU) {
257 + if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4706)
259 + else if (cc->core->id.rev < 26)
262 + nb = (cc->core->id.rev >= 37) ? 32 : 24;
269 + return (1 << nb) - 1;
272 +static u32 bcma_chipco_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt,
275 + struct bcma_drv_cc *cc = bcm47xx_wdt_get_drvdata(wdt);
277 + return bcma_chipco_watchdog_timer_set(cc, ticks);
280 +static u32 bcma_chipco_watchdog_timer_set_ms_wdt(struct bcm47xx_wdt *wdt,
283 + struct bcma_drv_cc *cc = bcm47xx_wdt_get_drvdata(wdt);
286 + ticks = bcma_chipco_watchdog_timer_set(cc, cc->ticks_per_ms * ms);
287 + return ticks / cc->ticks_per_ms;
290 +static int bcma_chipco_watchdog_ticks_per_ms(struct bcma_drv_cc *cc)
292 + struct bcma_bus *bus = cc->core->bus;
294 + if (cc->capabilities & BCMA_CC_CAP_PMU) {
295 + if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4706)
296 + /* 4706 CC and PMU watchdogs are clocked at 1/4 of ALP clock */
297 + return bcma_chipco_get_alp_clock(cc) / 4000;
299 + /* based on 32KHz ILP clock */
302 + return bcma_chipco_get_alp_clock(cc) / 1000;
306 +int bcma_chipco_watchdog_register(struct bcma_drv_cc *cc)
308 + struct bcm47xx_wdt wdt = {};
309 + struct platform_device *pdev;
311 + wdt.driver_data = cc;
312 + wdt.timer_set = bcma_chipco_watchdog_timer_set_wdt;
313 + wdt.timer_set_ms = bcma_chipco_watchdog_timer_set_ms_wdt;
314 + wdt.max_timer_ms = bcma_chipco_watchdog_get_max_timer(cc) / cc->ticks_per_ms;
316 + pdev = platform_device_register_data(NULL, "bcm47xx-wdt",
317 + cc->core->bus->num, &wdt,
320 + return PTR_ERR(pdev);
322 + cc->watchdog = pdev;
327 +void bcma_core_chipcommon_early_init(struct bcma_drv_cc *cc)
329 + if (cc->early_setup_done)
332 + spin_lock_init(&cc->gpio_lock);
334 if (cc->core->id.rev >= 11)
335 cc->status = bcma_cc_read32(cc, BCMA_CC_CHIPSTAT);
336 cc->capabilities = bcma_cc_read32(cc, BCMA_CC_CAP);
337 if (cc->core->id.rev >= 35)
338 cc->capabilities_ext = bcma_cc_read32(cc, BCMA_CC_CAP_EXT);
340 + if (cc->capabilities & BCMA_CC_CAP_PMU)
341 + bcma_pmu_early_init(cc);
343 + cc->early_setup_done = true;
346 +void bcma_core_chipcommon_init(struct bcma_drv_cc *cc)
349 + u32 leddc_off = 90;
351 + if (cc->setup_done)
354 + bcma_core_chipcommon_early_init(cc);
356 if (cc->core->id.rev >= 20) {
357 - bcma_cc_write32(cc, BCMA_CC_GPIOPULLUP, 0);
358 - bcma_cc_write32(cc, BCMA_CC_GPIOPULLDOWN, 0);
359 + u32 pullup = 0, pulldown = 0;
361 + if (cc->core->bus->chipinfo.id == BCMA_CHIP_ID_BCM43142) {
363 + pulldown = 0x20500;
366 + bcma_cc_write32(cc, BCMA_CC_GPIOPULLUP, pullup);
367 + bcma_cc_write32(cc, BCMA_CC_GPIOPULLDOWN, pulldown);
370 if (cc->capabilities & BCMA_CC_CAP_PMU)
371 @@ -56,15 +166,33 @@ void bcma_core_chipcommon_init(struct bc
372 ((leddc_on << BCMA_CC_GPIOTIMER_ONTIME_SHIFT) |
373 (leddc_off << BCMA_CC_GPIOTIMER_OFFTIME_SHIFT)));
375 + cc->ticks_per_ms = bcma_chipco_watchdog_ticks_per_ms(cc);
377 cc->setup_done = true;
380 /* Set chip watchdog reset timer to fire in 'ticks' backplane cycles */
381 -void bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc, u32 ticks)
382 +u32 bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc, u32 ticks)
385 - bcma_cc_write32(cc, BCMA_CC_WATCHDOG, ticks);
387 + enum bcma_clkmode clkmode;
389 + maxt = bcma_chipco_watchdog_get_max_timer(cc);
390 + if (cc->capabilities & BCMA_CC_CAP_PMU) {
393 + else if (ticks > maxt)
395 + bcma_cc_write32(cc, BCMA_CC_PMU_WATCHDOG, ticks);
397 + clkmode = ticks ? BCMA_CLKMODE_FAST : BCMA_CLKMODE_DYNAMIC;
398 + bcma_core_set_clockmode(cc->core, clkmode);
402 + bcma_cc_write32(cc, BCMA_CC_WATCHDOG, ticks);
407 void bcma_chipco_irq_mask(struct bcma_drv_cc *cc, u32 mask, u32 value)
408 @@ -84,28 +212,99 @@ u32 bcma_chipco_gpio_in(struct bcma_drv_
410 u32 bcma_chipco_gpio_out(struct bcma_drv_cc *cc, u32 mask, u32 value)
412 - return bcma_cc_write32_masked(cc, BCMA_CC_GPIOOUT, mask, value);
413 + unsigned long flags;
416 + spin_lock_irqsave(&cc->gpio_lock, flags);
417 + res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOOUT, mask, value);
418 + spin_unlock_irqrestore(&cc->gpio_lock, flags);
422 +EXPORT_SYMBOL_GPL(bcma_chipco_gpio_out);
424 u32 bcma_chipco_gpio_outen(struct bcma_drv_cc *cc, u32 mask, u32 value)
426 - return bcma_cc_write32_masked(cc, BCMA_CC_GPIOOUTEN, mask, value);
427 + unsigned long flags;
430 + spin_lock_irqsave(&cc->gpio_lock, flags);
431 + res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOOUTEN, mask, value);
432 + spin_unlock_irqrestore(&cc->gpio_lock, flags);
436 +EXPORT_SYMBOL_GPL(bcma_chipco_gpio_outen);
439 + * If the bit is set to 0, chipcommon controlls this GPIO,
440 + * if the bit is set to 1, it is used by some part of the chip and not our code.
442 u32 bcma_chipco_gpio_control(struct bcma_drv_cc *cc, u32 mask, u32 value)
444 - return bcma_cc_write32_masked(cc, BCMA_CC_GPIOCTL, mask, value);
445 + unsigned long flags;
448 + spin_lock_irqsave(&cc->gpio_lock, flags);
449 + res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOCTL, mask, value);
450 + spin_unlock_irqrestore(&cc->gpio_lock, flags);
454 EXPORT_SYMBOL_GPL(bcma_chipco_gpio_control);
456 u32 bcma_chipco_gpio_intmask(struct bcma_drv_cc *cc, u32 mask, u32 value)
458 - return bcma_cc_write32_masked(cc, BCMA_CC_GPIOIRQ, mask, value);
459 + unsigned long flags;
462 + spin_lock_irqsave(&cc->gpio_lock, flags);
463 + res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOIRQ, mask, value);
464 + spin_unlock_irqrestore(&cc->gpio_lock, flags);
469 u32 bcma_chipco_gpio_polarity(struct bcma_drv_cc *cc, u32 mask, u32 value)
471 - return bcma_cc_write32_masked(cc, BCMA_CC_GPIOPOL, mask, value);
472 + unsigned long flags;
475 + spin_lock_irqsave(&cc->gpio_lock, flags);
476 + res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOPOL, mask, value);
477 + spin_unlock_irqrestore(&cc->gpio_lock, flags);
482 +u32 bcma_chipco_gpio_pullup(struct bcma_drv_cc *cc, u32 mask, u32 value)
484 + unsigned long flags;
487 + if (cc->core->id.rev < 20)
490 + spin_lock_irqsave(&cc->gpio_lock, flags);
491 + res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOPULLUP, mask, value);
492 + spin_unlock_irqrestore(&cc->gpio_lock, flags);
497 +u32 bcma_chipco_gpio_pulldown(struct bcma_drv_cc *cc, u32 mask, u32 value)
499 + unsigned long flags;
502 + if (cc->core->id.rev < 20)
505 + spin_lock_irqsave(&cc->gpio_lock, flags);
506 + res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOPULLDOWN, mask, value);
507 + spin_unlock_irqrestore(&cc->gpio_lock, flags);
512 #ifdef CONFIG_BCMA_DRIVER_MIPS
513 @@ -118,8 +317,7 @@ void bcma_chipco_serial_init(struct bcma
514 struct bcma_serial_port *ports = cc->serial_ports;
516 if (ccrev >= 11 && ccrev != 15) {
517 - /* Fixed ALP clock */
518 - baud_base = bcma_pmu_alp_clock(cc);
519 + baud_base = bcma_chipco_get_alp_clock(cc);
521 /* Turn off UART clock before switching clocksource. */
522 bcma_cc_write32(cc, BCMA_CC_CORECTL,
523 @@ -141,7 +339,7 @@ void bcma_chipco_serial_init(struct bcma
527 - irq = bcma_core_mips_irq(cc->core);
528 + irq = bcma_core_irq(cc->core);
530 /* Determine the registers of the UARTs */
531 cc->nr_serial_ports = (cc->capabilities & BCMA_CC_CAP_NRUART);
532 --- a/drivers/bcma/driver_chipcommon_nflash.c
533 +++ b/drivers/bcma/driver_chipcommon_nflash.c
535 * Licensed under the GNU/GPL. See COPYING for details.
538 +#include "bcma_private.h"
540 +#include <linux/platform_device.h>
541 #include <linux/bcma/bcma.h>
542 -#include <linux/bcma/bcma_driver_chipcommon.h>
543 -#include <linux/delay.h>
545 -#include "bcma_private.h"
546 +struct platform_device bcma_nflash_dev = {
547 + .name = "bcma_nflash",
548 + .num_resources = 0,
551 /* Initialize NAND flash access */
552 int bcma_nflash_init(struct bcma_drv_cc *cc)
554 - bcma_err(cc->core->bus, "NAND flash support is broken\n");
555 + struct bcma_bus *bus = cc->core->bus;
557 + if (bus->chipinfo.id != BCMA_CHIP_ID_BCM4706 &&
558 + cc->core->id.rev != 38) {
559 + bcma_err(bus, "NAND flash on unsupported board!\n");
563 + if (!(cc->capabilities & BCMA_CC_CAP_NFLASH)) {
564 + bcma_err(bus, "NAND flash not present according to ChipCommon\n");
568 + cc->nflash.present = true;
569 + if (cc->core->id.rev == 38 &&
570 + (cc->status & BCMA_CC_CHIPST_5357_NAND_BOOT))
571 + cc->nflash.boot = true;
573 + /* Prepare platform device, but don't register it yet. It's too early,
574 + * malloc (required by device_private_init) is not available yet. */
575 + bcma_nflash_dev.dev.platform_data = &cc->nflash;
579 --- a/drivers/bcma/driver_chipcommon_pmu.c
580 +++ b/drivers/bcma/driver_chipcommon_pmu.c
582 #include <linux/export.h>
583 #include <linux/bcma/bcma.h>
585 -static u32 bcma_chipco_pll_read(struct bcma_drv_cc *cc, u32 offset)
586 +u32 bcma_chipco_pll_read(struct bcma_drv_cc *cc, u32 offset)
588 bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR, offset);
589 bcma_cc_read32(cc, BCMA_CC_PLLCTL_ADDR);
590 return bcma_cc_read32(cc, BCMA_CC_PLLCTL_DATA);
592 +EXPORT_SYMBOL_GPL(bcma_chipco_pll_read);
594 void bcma_chipco_pll_write(struct bcma_drv_cc *cc, u32 offset, u32 value)
596 @@ -55,6 +56,109 @@ void bcma_chipco_regctl_maskset(struct b
598 EXPORT_SYMBOL_GPL(bcma_chipco_regctl_maskset);
600 +static u32 bcma_pmu_xtalfreq(struct bcma_drv_cc *cc)
602 + u32 ilp_ctl, alp_hz;
604 + if (!(bcma_cc_read32(cc, BCMA_CC_PMU_STAT) &
605 + BCMA_CC_PMU_STAT_EXT_LPO_AVAIL))
608 + bcma_cc_write32(cc, BCMA_CC_PMU_XTAL_FREQ,
609 + BIT(BCMA_CC_PMU_XTAL_FREQ_MEASURE_SHIFT));
610 + usleep_range(1000, 2000);
612 + ilp_ctl = bcma_cc_read32(cc, BCMA_CC_PMU_XTAL_FREQ);
613 + ilp_ctl &= BCMA_CC_PMU_XTAL_FREQ_ILPCTL_MASK;
615 + bcma_cc_write32(cc, BCMA_CC_PMU_XTAL_FREQ, 0);
617 + alp_hz = ilp_ctl * 32768 / 4;
618 + return (alp_hz + 50000) / 100000 * 100;
621 +static void bcma_pmu2_pll_init0(struct bcma_drv_cc *cc, u32 xtalfreq)
623 + struct bcma_bus *bus = cc->core->bus;
624 + u32 freq_tgt_target = 0, freq_tgt_current;
627 + switch (bus->chipinfo.id) {
628 + case BCMA_CHIP_ID_BCM43142:
629 + /* pmu2_xtaltab0_adfll_485 */
630 + switch (xtalfreq) {
632 + freq_tgt_target = 0x50D52;
635 + freq_tgt_target = 0x307FE;
638 + freq_tgt_target = 0x254EA;
641 + freq_tgt_target = 0x19EF8;
644 + freq_tgt_target = 0x12A75;
650 + if (!freq_tgt_target) {
651 + bcma_err(bus, "Unknown TGT frequency for xtalfreq %d\n",
656 + pll0 = bcma_chipco_pll_read(cc, BCMA_CC_PMU15_PLL_PLLCTL0);
657 + freq_tgt_current = (pll0 & BCMA_CC_PMU15_PLL_PC0_FREQTGT_MASK) >>
658 + BCMA_CC_PMU15_PLL_PC0_FREQTGT_SHIFT;
660 + if (freq_tgt_current == freq_tgt_target) {
661 + bcma_debug(bus, "Target TGT frequency already set\n");
666 + switch (bus->chipinfo.id) {
667 + case BCMA_CHIP_ID_BCM43142:
668 + mask = (u32)~(BCMA_RES_4314_HT_AVAIL |
669 + BCMA_RES_4314_MACPHY_CLK_AVAIL);
671 + bcma_cc_mask32(cc, BCMA_CC_PMU_MINRES_MSK, mask);
672 + bcma_cc_mask32(cc, BCMA_CC_PMU_MAXRES_MSK, mask);
673 + bcma_wait_value(cc->core, BCMA_CLKCTLST,
674 + BCMA_CLKCTLST_HAVEHT, 0, 20000);
678 + pll0 &= ~BCMA_CC_PMU15_PLL_PC0_FREQTGT_MASK;
679 + pll0 |= freq_tgt_target << BCMA_CC_PMU15_PLL_PC0_FREQTGT_SHIFT;
680 + bcma_chipco_pll_write(cc, BCMA_CC_PMU15_PLL_PLLCTL0, pll0);
683 + if (cc->pmu.rev >= 2)
684 + bcma_cc_set32(cc, BCMA_CC_PMU_CTL, BCMA_CC_PMU_CTL_PLL_UPD);
686 + /* TODO: Do we need to update OTP? */
689 +static void bcma_pmu_pll_init(struct bcma_drv_cc *cc)
691 + struct bcma_bus *bus = cc->core->bus;
692 + u32 xtalfreq = bcma_pmu_xtalfreq(cc);
694 + switch (bus->chipinfo.id) {
695 + case BCMA_CHIP_ID_BCM43142:
698 + bcma_pmu2_pll_init0(cc, xtalfreq);
703 static void bcma_pmu_resources_init(struct bcma_drv_cc *cc)
705 struct bcma_bus *bus = cc->core->bus;
706 @@ -65,6 +169,25 @@ static void bcma_pmu_resources_init(stru
710 + case BCMA_CHIP_ID_BCM43142:
711 + min_msk = BCMA_RES_4314_LPLDO_PU |
712 + BCMA_RES_4314_PMU_SLEEP_DIS |
713 + BCMA_RES_4314_PMU_BG_PU |
714 + BCMA_RES_4314_CBUCK_LPOM_PU |
715 + BCMA_RES_4314_CBUCK_PFM_PU |
716 + BCMA_RES_4314_CLDO_PU |
717 + BCMA_RES_4314_LPLDO2_LVM |
718 + BCMA_RES_4314_WL_PMU_PU |
719 + BCMA_RES_4314_LDO3P3_PU |
720 + BCMA_RES_4314_OTP_PU |
721 + BCMA_RES_4314_WL_PWRSW_PU |
722 + BCMA_RES_4314_LQ_AVAIL |
723 + BCMA_RES_4314_LOGIC_RET |
724 + BCMA_RES_4314_MEM_SLEEP |
725 + BCMA_RES_4314_MACPHY_RET |
726 + BCMA_RES_4314_WL_CORE_READY;
727 + max_msk = 0x3FFFFFFF;
730 bcma_debug(bus, "PMU resource config unknown or not needed for device 0x%04X\n",
732 @@ -76,7 +199,10 @@ static void bcma_pmu_resources_init(stru
734 bcma_cc_write32(cc, BCMA_CC_PMU_MAXRES_MSK, max_msk);
736 - /* Add some delay; allow resources to come up and settle. */
738 + * Add some delay; allow resources to come up and settle.
739 + * Delay is required for SoC (early init).
744 @@ -101,7 +227,7 @@ void bcma_chipco_bcm4331_ext_pa_lines_ct
745 bcma_cc_write32(cc, BCMA_CC_CHIPCTL, val);
748 -void bcma_pmu_workarounds(struct bcma_drv_cc *cc)
749 +static void bcma_pmu_workarounds(struct bcma_drv_cc *cc)
751 struct bcma_bus *bus = cc->core->bus;
753 @@ -141,7 +267,7 @@ void bcma_pmu_workarounds(struct bcma_dr
757 -void bcma_pmu_init(struct bcma_drv_cc *cc)
758 +void bcma_pmu_early_init(struct bcma_drv_cc *cc)
762 @@ -150,7 +276,10 @@ void bcma_pmu_init(struct bcma_drv_cc *c
764 bcma_debug(cc->core->bus, "Found rev %u PMU (capabilities 0x%08X)\n",
765 cc->pmu.rev, pmucap);
768 +void bcma_pmu_init(struct bcma_drv_cc *cc)
770 if (cc->pmu.rev == 1)
771 bcma_cc_mask32(cc, BCMA_CC_PMU_CTL,
772 ~BCMA_CC_PMU_CTL_NOILPONW);
773 @@ -158,28 +287,45 @@ void bcma_pmu_init(struct bcma_drv_cc *c
774 bcma_cc_set32(cc, BCMA_CC_PMU_CTL,
775 BCMA_CC_PMU_CTL_NOILPONW);
777 + bcma_pmu_pll_init(cc);
778 bcma_pmu_resources_init(cc);
779 bcma_pmu_workarounds(cc);
782 -u32 bcma_pmu_alp_clock(struct bcma_drv_cc *cc)
783 +u32 bcma_pmu_get_alp_clock(struct bcma_drv_cc *cc)
785 struct bcma_bus *bus = cc->core->bus;
787 switch (bus->chipinfo.id) {
788 + case BCMA_CHIP_ID_BCM4313:
789 + case BCMA_CHIP_ID_BCM43224:
790 + case BCMA_CHIP_ID_BCM43225:
791 + case BCMA_CHIP_ID_BCM43227:
792 + case BCMA_CHIP_ID_BCM43228:
793 + case BCMA_CHIP_ID_BCM4331:
794 + case BCMA_CHIP_ID_BCM43421:
795 + case BCMA_CHIP_ID_BCM43428:
796 + case BCMA_CHIP_ID_BCM43431:
797 case BCMA_CHIP_ID_BCM4716:
798 - case BCMA_CHIP_ID_BCM4748:
799 case BCMA_CHIP_ID_BCM47162:
800 - case BCMA_CHIP_ID_BCM4313:
801 - case BCMA_CHIP_ID_BCM5357:
802 + case BCMA_CHIP_ID_BCM4748:
803 case BCMA_CHIP_ID_BCM4749:
804 + case BCMA_CHIP_ID_BCM5357:
805 case BCMA_CHIP_ID_BCM53572:
806 + case BCMA_CHIP_ID_BCM6362:
809 - case BCMA_CHIP_ID_BCM5356:
810 case BCMA_CHIP_ID_BCM4706:
811 + case BCMA_CHIP_ID_BCM5356:
814 + case BCMA_CHIP_ID_BCM43460:
815 + case BCMA_CHIP_ID_BCM4352:
816 + case BCMA_CHIP_ID_BCM4360:
817 + if (cc->status & BCMA_CC_CHIPST_4360_XTAL_40MZ)
818 + return 40000 * 1000;
820 + return 20000 * 1000;
822 bcma_warn(bus, "No ALP clock specified for %04X device, pmu rev. %d, using default %d Hz\n",
823 bus->chipinfo.id, cc->pmu.rev, BCMA_CC_PMU_ALP_CLOCK);
824 @@ -190,7 +336,7 @@ u32 bcma_pmu_alp_clock(struct bcma_drv_c
825 /* Find the output of the "m" pll divider given pll controls that start with
826 * pllreg "pll0" i.e. 12 for main 6 for phy, 0 for misc.
828 -static u32 bcma_pmu_clock(struct bcma_drv_cc *cc, u32 pll0, u32 m)
829 +static u32 bcma_pmu_pll_clock(struct bcma_drv_cc *cc, u32 pll0, u32 m)
831 u32 tmp, div, ndiv, p1, p2, fc;
832 struct bcma_bus *bus = cc->core->bus;
833 @@ -219,14 +365,14 @@ static u32 bcma_pmu_clock(struct bcma_dr
834 ndiv = (tmp & BCMA_CC_PPL_NDIV_MASK) >> BCMA_CC_PPL_NDIV_SHIFT;
836 /* Do calculation in Mhz */
837 - fc = bcma_pmu_alp_clock(cc) / 1000000;
838 + fc = bcma_pmu_get_alp_clock(cc) / 1000000;
839 fc = (p1 * ndiv * fc) / p2;
841 /* Return clock in Hertz */
842 return (fc / div) * 1000000;
845 -static u32 bcma_pmu_clock_bcm4706(struct bcma_drv_cc *cc, u32 pll0, u32 m)
846 +static u32 bcma_pmu_pll_clock_bcm4706(struct bcma_drv_cc *cc, u32 pll0, u32 m)
848 u32 tmp, ndiv, p1div, p2div;
850 @@ -257,7 +403,7 @@ static u32 bcma_pmu_clock_bcm4706(struct
853 /* query bus clock frequency for PMU-enabled chipcommon */
854 -u32 bcma_pmu_get_clockcontrol(struct bcma_drv_cc *cc)
855 +u32 bcma_pmu_get_bus_clock(struct bcma_drv_cc *cc)
857 struct bcma_bus *bus = cc->core->bus;
859 @@ -265,40 +411,43 @@ u32 bcma_pmu_get_clockcontrol(struct bcm
860 case BCMA_CHIP_ID_BCM4716:
861 case BCMA_CHIP_ID_BCM4748:
862 case BCMA_CHIP_ID_BCM47162:
863 - return bcma_pmu_clock(cc, BCMA_CC_PMU4716_MAINPLL_PLL0,
864 - BCMA_CC_PMU5_MAINPLL_SSB);
865 + return bcma_pmu_pll_clock(cc, BCMA_CC_PMU4716_MAINPLL_PLL0,
866 + BCMA_CC_PMU5_MAINPLL_SSB);
867 case BCMA_CHIP_ID_BCM5356:
868 - return bcma_pmu_clock(cc, BCMA_CC_PMU5356_MAINPLL_PLL0,
869 - BCMA_CC_PMU5_MAINPLL_SSB);
870 + return bcma_pmu_pll_clock(cc, BCMA_CC_PMU5356_MAINPLL_PLL0,
871 + BCMA_CC_PMU5_MAINPLL_SSB);
872 case BCMA_CHIP_ID_BCM5357:
873 case BCMA_CHIP_ID_BCM4749:
874 - return bcma_pmu_clock(cc, BCMA_CC_PMU5357_MAINPLL_PLL0,
875 - BCMA_CC_PMU5_MAINPLL_SSB);
876 + return bcma_pmu_pll_clock(cc, BCMA_CC_PMU5357_MAINPLL_PLL0,
877 + BCMA_CC_PMU5_MAINPLL_SSB);
878 case BCMA_CHIP_ID_BCM4706:
879 - return bcma_pmu_clock_bcm4706(cc, BCMA_CC_PMU4706_MAINPLL_PLL0,
880 - BCMA_CC_PMU5_MAINPLL_SSB);
881 + return bcma_pmu_pll_clock_bcm4706(cc,
882 + BCMA_CC_PMU4706_MAINPLL_PLL0,
883 + BCMA_CC_PMU5_MAINPLL_SSB);
884 case BCMA_CHIP_ID_BCM53572:
887 - bcma_warn(bus, "No backplane clock specified for %04X device, pmu rev. %d, using default %d Hz\n",
888 + bcma_warn(bus, "No bus clock specified for %04X device, pmu rev. %d, using default %d Hz\n",
889 bus->chipinfo.id, cc->pmu.rev, BCMA_CC_PMU_HT_CLOCK);
891 return BCMA_CC_PMU_HT_CLOCK;
893 +EXPORT_SYMBOL_GPL(bcma_pmu_get_bus_clock);
895 /* query cpu clock frequency for PMU-enabled chipcommon */
896 -u32 bcma_pmu_get_clockcpu(struct bcma_drv_cc *cc)
897 +u32 bcma_pmu_get_cpu_clock(struct bcma_drv_cc *cc)
899 struct bcma_bus *bus = cc->core->bus;
901 if (bus->chipinfo.id == BCMA_CHIP_ID_BCM53572)
904 + /* New PMUs can have different clock for bus and CPU */
905 if (cc->pmu.rev >= 5) {
907 switch (bus->chipinfo.id) {
908 case BCMA_CHIP_ID_BCM4706:
909 - return bcma_pmu_clock_bcm4706(cc,
910 + return bcma_pmu_pll_clock_bcm4706(cc,
911 BCMA_CC_PMU4706_MAINPLL_PLL0,
912 BCMA_CC_PMU5_MAINPLL_CPU);
913 case BCMA_CHIP_ID_BCM5356:
914 @@ -313,10 +462,11 @@ u32 bcma_pmu_get_clockcpu(struct bcma_dr
918 - return bcma_pmu_clock(cc, pll, BCMA_CC_PMU5_MAINPLL_CPU);
919 + return bcma_pmu_pll_clock(cc, pll, BCMA_CC_PMU5_MAINPLL_CPU);
922 - return bcma_pmu_get_clockcontrol(cc);
923 + /* On old PMUs CPU has the same clock as the bus */
924 + return bcma_pmu_get_bus_clock(cc);
927 static void bcma_pmu_spuravoid_pll_write(struct bcma_drv_cc *cc, u32 offset,
928 @@ -362,7 +512,7 @@ void bcma_pmu_spuravoid_pllupdate(struct
929 tmp |= (bcm5357_bcm43236_ndiv[spuravoid]) << BCMA_CC_PMU1_PLL0_PC2_NDIV_INT_SHIFT;
930 bcma_cc_write32(cc, BCMA_CC_PLLCTL_DATA, tmp);
933 + tmp = BCMA_CC_PMU_CTL_PLL_UPD;
936 case BCMA_CHIP_ID_BCM4331:
937 @@ -383,7 +533,7 @@ void bcma_pmu_spuravoid_pllupdate(struct
938 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
942 + tmp = BCMA_CC_PMU_CTL_PLL_UPD;
945 case BCMA_CHIP_ID_BCM43224:
946 @@ -416,7 +566,7 @@ void bcma_pmu_spuravoid_pllupdate(struct
947 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
951 + tmp = BCMA_CC_PMU_CTL_PLL_UPD;
954 case BCMA_CHIP_ID_BCM4716:
955 @@ -450,7 +600,7 @@ void bcma_pmu_spuravoid_pllupdate(struct
960 + tmp = BCMA_CC_PMU_CTL_PLL_UPD | BCMA_CC_PMU_CTL_NOILPONW;
963 case BCMA_CHIP_ID_BCM43227:
964 @@ -486,7 +636,7 @@ void bcma_pmu_spuravoid_pllupdate(struct
965 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
969 + tmp = BCMA_CC_PMU_CTL_PLL_UPD;
972 bcma_err(bus, "Unknown spuravoidance settings for chip 0x%04X, not changing PLL\n",
973 --- a/drivers/bcma/driver_chipcommon_sflash.c
974 +++ b/drivers/bcma/driver_chipcommon_sflash.c
976 * Licensed under the GNU/GPL. See COPYING for details.
979 +#include "bcma_private.h"
981 +#include <linux/platform_device.h>
982 #include <linux/bcma/bcma.h>
983 -#include <linux/bcma/bcma_driver_chipcommon.h>
984 -#include <linux/delay.h>
986 -#include "bcma_private.h"
987 +static struct resource bcma_sflash_resource = {
988 + .name = "bcma_sflash",
989 + .start = BCMA_SOC_FLASH2,
991 + .flags = IORESOURCE_MEM | IORESOURCE_READONLY,
994 +struct platform_device bcma_sflash_dev = {
995 + .name = "bcma_sflash",
996 + .resource = &bcma_sflash_resource,
997 + .num_resources = 1,
1000 +struct bcma_sflash_tbl_e {
1007 +static const struct bcma_sflash_tbl_e bcma_sflash_st_tbl[] = {
1008 + { "M25P20", 0x11, 0x10000, 4, },
1009 + { "M25P40", 0x12, 0x10000, 8, },
1011 + { "M25P16", 0x14, 0x10000, 32, },
1012 + { "M25P32", 0x15, 0x10000, 64, },
1013 + { "M25P64", 0x16, 0x10000, 128, },
1014 + { "M25FL128", 0x17, 0x10000, 256, },
1018 +static const struct bcma_sflash_tbl_e bcma_sflash_sst_tbl[] = {
1019 + { "SST25WF512", 1, 0x1000, 16, },
1020 + { "SST25VF512", 0x48, 0x1000, 16, },
1021 + { "SST25WF010", 2, 0x1000, 32, },
1022 + { "SST25VF010", 0x49, 0x1000, 32, },
1023 + { "SST25WF020", 3, 0x1000, 64, },
1024 + { "SST25VF020", 0x43, 0x1000, 64, },
1025 + { "SST25WF040", 4, 0x1000, 128, },
1026 + { "SST25VF040", 0x44, 0x1000, 128, },
1027 + { "SST25VF040B", 0x8d, 0x1000, 128, },
1028 + { "SST25WF080", 5, 0x1000, 256, },
1029 + { "SST25VF080B", 0x8e, 0x1000, 256, },
1030 + { "SST25VF016", 0x41, 0x1000, 512, },
1031 + { "SST25VF032", 0x4a, 0x1000, 1024, },
1032 + { "SST25VF064", 0x4b, 0x1000, 2048, },
1036 +static const struct bcma_sflash_tbl_e bcma_sflash_at_tbl[] = {
1037 + { "AT45DB011", 0xc, 256, 512, },
1038 + { "AT45DB021", 0x14, 256, 1024, },
1039 + { "AT45DB041", 0x1c, 256, 2048, },
1040 + { "AT45DB081", 0x24, 256, 4096, },
1041 + { "AT45DB161", 0x2c, 512, 4096, },
1042 + { "AT45DB321", 0x34, 512, 8192, },
1043 + { "AT45DB642", 0x3c, 1024, 8192, },
1047 +static void bcma_sflash_cmd(struct bcma_drv_cc *cc, u32 opcode)
1050 + bcma_cc_write32(cc, BCMA_CC_FLASHCTL,
1051 + BCMA_CC_FLASHCTL_START | opcode);
1052 + for (i = 0; i < 1000; i++) {
1053 + if (!(bcma_cc_read32(cc, BCMA_CC_FLASHCTL) &
1054 + BCMA_CC_FLASHCTL_BUSY))
1058 + bcma_err(cc->core->bus, "SFLASH control command failed (timeout)!\n");
1061 /* Initialize serial flash access */
1062 int bcma_sflash_init(struct bcma_drv_cc *cc)
1064 - bcma_err(cc->core->bus, "Serial flash support is broken\n");
1065 + struct bcma_bus *bus = cc->core->bus;
1066 + struct bcma_sflash *sflash = &cc->sflash;
1067 + const struct bcma_sflash_tbl_e *e;
1070 + switch (cc->capabilities & BCMA_CC_CAP_FLASHT) {
1071 + case BCMA_CC_FLASHT_STSER:
1072 + bcma_sflash_cmd(cc, BCMA_CC_FLASHCTL_ST_DP);
1074 + bcma_cc_write32(cc, BCMA_CC_FLASHADDR, 0);
1075 + bcma_sflash_cmd(cc, BCMA_CC_FLASHCTL_ST_RES);
1076 + id = bcma_cc_read32(cc, BCMA_CC_FLASHDATA);
1078 + bcma_cc_write32(cc, BCMA_CC_FLASHADDR, 1);
1079 + bcma_sflash_cmd(cc, BCMA_CC_FLASHCTL_ST_RES);
1080 + id2 = bcma_cc_read32(cc, BCMA_CC_FLASHDATA);
1084 + for (e = bcma_sflash_sst_tbl; e->name; e++) {
1092 + for (e = bcma_sflash_st_tbl; e->name; e++) {
1099 + bcma_err(bus, "Unsupported ST serial flash (id: 0x%X, id2: 0x%X)\n", id, id2);
1104 + case BCMA_CC_FLASHT_ATSER:
1105 + bcma_sflash_cmd(cc, BCMA_CC_FLASHCTL_AT_STATUS);
1106 + id = bcma_cc_read32(cc, BCMA_CC_FLASHDATA) & 0x3c;
1108 + for (e = bcma_sflash_at_tbl; e->name; e++) {
1113 + bcma_err(bus, "Unsupported Atmel serial flash (id: 0x%X)\n", id);
1119 + bcma_err(bus, "Unsupported flash type\n");
1123 + sflash->window = BCMA_SOC_FLASH2;
1124 + sflash->blocksize = e->blocksize;
1125 + sflash->numblocks = e->numblocks;
1126 + sflash->size = sflash->blocksize * sflash->numblocks;
1127 + sflash->present = true;
1129 + bcma_info(bus, "Found %s serial flash (size: %dKiB, blocksize: 0x%X, blocks: %d)\n",
1130 + e->name, sflash->size / 1024, sflash->blocksize,
1131 + sflash->numblocks);
1133 + /* Prepare platform device, but don't register it yet. It's too early,
1134 + * malloc (required by device_private_init) is not available yet. */
1135 + bcma_sflash_dev.resource[0].end = bcma_sflash_dev.resource[0].start +
1137 + bcma_sflash_dev.dev.platform_data = sflash;
1142 +++ b/drivers/bcma/driver_gpio.c
1145 + * Broadcom specific AMBA
1148 + * Copyright 2011, Broadcom Corporation
1149 + * Copyright 2012, Hauke Mehrtens <hauke@hauke-m.de>
1151 + * Licensed under the GNU/GPL. See COPYING for details.
1154 +#include <linux/gpio.h>
1155 +#include <linux/export.h>
1156 +#include <linux/bcma/bcma.h>
1158 +#include "bcma_private.h"
1160 +static inline struct bcma_drv_cc *bcma_gpio_get_cc(struct gpio_chip *chip)
1162 + return container_of(chip, struct bcma_drv_cc, gpio);
1165 +static int bcma_gpio_get_value(struct gpio_chip *chip, unsigned gpio)
1167 + struct bcma_drv_cc *cc = bcma_gpio_get_cc(chip);
1169 + return !!bcma_chipco_gpio_in(cc, 1 << gpio);
1172 +static void bcma_gpio_set_value(struct gpio_chip *chip, unsigned gpio,
1175 + struct bcma_drv_cc *cc = bcma_gpio_get_cc(chip);
1177 + bcma_chipco_gpio_out(cc, 1 << gpio, value ? 1 << gpio : 0);
1180 +static int bcma_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
1182 + struct bcma_drv_cc *cc = bcma_gpio_get_cc(chip);
1184 + bcma_chipco_gpio_outen(cc, 1 << gpio, 0);
1188 +static int bcma_gpio_direction_output(struct gpio_chip *chip, unsigned gpio,
1191 + struct bcma_drv_cc *cc = bcma_gpio_get_cc(chip);
1193 + bcma_chipco_gpio_outen(cc, 1 << gpio, 1 << gpio);
1194 + bcma_chipco_gpio_out(cc, 1 << gpio, value ? 1 << gpio : 0);
1198 +static int bcma_gpio_request(struct gpio_chip *chip, unsigned gpio)
1200 + struct bcma_drv_cc *cc = bcma_gpio_get_cc(chip);
1202 + bcma_chipco_gpio_control(cc, 1 << gpio, 0);
1203 + /* clear pulldown */
1204 + bcma_chipco_gpio_pulldown(cc, 1 << gpio, 0);
1206 + bcma_chipco_gpio_pullup(cc, 1 << gpio, 1 << gpio);
1211 +static void bcma_gpio_free(struct gpio_chip *chip, unsigned gpio)
1213 + struct bcma_drv_cc *cc = bcma_gpio_get_cc(chip);
1215 + /* clear pullup */
1216 + bcma_chipco_gpio_pullup(cc, 1 << gpio, 0);
1219 +static int bcma_gpio_to_irq(struct gpio_chip *chip, unsigned gpio)
1221 + struct bcma_drv_cc *cc = bcma_gpio_get_cc(chip);
1223 + if (cc->core->bus->hosttype == BCMA_HOSTTYPE_SOC)
1224 + return bcma_core_irq(cc->core);
1229 +int bcma_gpio_init(struct bcma_drv_cc *cc)
1231 + struct gpio_chip *chip = &cc->gpio;
1233 + chip->label = "bcma_gpio";
1234 + chip->owner = THIS_MODULE;
1235 + chip->request = bcma_gpio_request;
1236 + chip->free = bcma_gpio_free;
1237 + chip->get = bcma_gpio_get_value;
1238 + chip->set = bcma_gpio_set_value;
1239 + chip->direction_input = bcma_gpio_direction_input;
1240 + chip->direction_output = bcma_gpio_direction_output;
1241 + chip->to_irq = bcma_gpio_to_irq;
1243 + /* There is just one SoC in one device and its GPIO addresses should be
1244 + * deterministic to address them more easily. The other buses could get
1245 + * a random base number. */
1246 + if (cc->core->bus->hosttype == BCMA_HOSTTYPE_SOC)
1251 + return gpiochip_add(chip);
1254 +int bcma_gpio_unregister(struct bcma_drv_cc *cc)
1256 + return gpiochip_remove(&cc->gpio);
1258 --- a/drivers/bcma/driver_mips.c
1259 +++ b/drivers/bcma/driver_mips.c
1262 #include <linux/bcma/bcma.h>
1264 +#include <linux/mtd/physmap.h>
1265 +#include <linux/platform_device.h>
1266 #include <linux/serial.h>
1267 #include <linux/serial_core.h>
1268 #include <linux/serial_reg.h>
1269 #include <linux/time.h>
1271 +static const char * const part_probes[] = { "bcm47xxpart", NULL };
1273 +static struct physmap_flash_data bcma_pflash_data = {
1274 + .part_probe_types = part_probes,
1277 +static struct resource bcma_pflash_resource = {
1278 + .name = "bcma_pflash",
1279 + .flags = IORESOURCE_MEM,
1282 +struct platform_device bcma_pflash_dev = {
1283 + .name = "physmap-flash",
1285 + .platform_data = &bcma_pflash_data,
1287 + .resource = &bcma_pflash_resource,
1288 + .num_resources = 1,
1291 /* The 47162a0 hangs when reading MIPS DMP registers registers */
1292 static inline bool bcma_core_mips_bcm47162a0_quirk(struct bcma_device *dev)
1294 @@ -74,28 +96,41 @@ static u32 bcma_core_mips_irqflag(struct
1295 return dev->core_index;
1296 flag = bcma_aread32(dev, BCMA_MIPS_OOBSELOUTA30);
1298 - return flag & 0x1F;
1300 + return flag & 0x1F;
1305 /* Get the MIPS IRQ assignment for a specified device.
1306 * If unassigned, 0 is returned.
1307 + * If disabled, 5 is returned.
1308 + * If not supported, 6 is returned.
1310 -unsigned int bcma_core_mips_irq(struct bcma_device *dev)
1311 +static unsigned int bcma_core_mips_irq(struct bcma_device *dev)
1313 struct bcma_device *mdev = dev->bus->drv_mips.core;
1317 irqflag = bcma_core_mips_irqflag(dev);
1318 + if (irqflag == 0x3f)
1321 - for (irq = 1; irq <= 4; irq++)
1322 + for (irq = 0; irq <= 4; irq++)
1323 if (bcma_read32(mdev, BCMA_MIPS_MIPS74K_INTMASK(irq)) &
1331 +unsigned int bcma_core_irq(struct bcma_device *dev)
1333 + unsigned int mips_irq = bcma_core_mips_irq(dev);
1334 + return mips_irq <= 4 ? mips_irq + 2 : 0;
1336 -EXPORT_SYMBOL(bcma_core_mips_irq);
1337 +EXPORT_SYMBOL(bcma_core_irq);
1339 static void bcma_core_mips_set_irq(struct bcma_device *dev, unsigned int irq)
1341 @@ -114,8 +149,8 @@ static void bcma_core_mips_set_irq(struc
1342 bcma_write32(mdev, BCMA_MIPS_MIPS74K_INTMASK(0),
1343 bcma_read32(mdev, BCMA_MIPS_MIPS74K_INTMASK(0)) &
1346 - bcma_write32(mdev, BCMA_MIPS_MIPS74K_INTMASK(irq), 0);
1347 + else if (oldirq != 5)
1348 + bcma_write32(mdev, BCMA_MIPS_MIPS74K_INTMASK(oldirq), 0);
1350 /* assign the new one */
1352 @@ -123,9 +158,9 @@ static void bcma_core_mips_set_irq(struc
1353 bcma_read32(mdev, BCMA_MIPS_MIPS74K_INTMASK(0)) |
1356 - u32 oldirqflag = bcma_read32(mdev,
1357 - BCMA_MIPS_MIPS74K_INTMASK(irq));
1359 + u32 irqinitmask = bcma_read32(mdev,
1360 + BCMA_MIPS_MIPS74K_INTMASK(irq));
1361 + if (irqinitmask) {
1362 struct bcma_device *core;
1364 /* backplane irq line is in use, find out who uses
1365 @@ -133,7 +168,7 @@ static void bcma_core_mips_set_irq(struc
1367 list_for_each_entry(core, &bus->cores, list) {
1368 if ((1 << bcma_core_mips_irqflag(core)) ==
1371 bcma_core_mips_set_irq(core, 0);
1374 @@ -143,15 +178,31 @@ static void bcma_core_mips_set_irq(struc
1378 - bcma_info(bus, "set_irq: core 0x%04x, irq %d => %d\n",
1379 - dev->id.id, oldirq + 2, irq + 2);
1380 + bcma_debug(bus, "set_irq: core 0x%04x, irq %d => %d\n",
1381 + dev->id.id, oldirq <= 4 ? oldirq + 2 : 0, irq + 2);
1384 +static void bcma_core_mips_set_irq_name(struct bcma_bus *bus, unsigned int irq,
1385 + u16 coreid, u8 unit)
1387 + struct bcma_device *core;
1389 + core = bcma_find_core_unit(bus, coreid, unit);
1392 + "Can not find core (id: 0x%x, unit %i) for IRQ configuration.\n",
1397 + bcma_core_mips_set_irq(core, irq);
1400 static void bcma_core_mips_print_irq(struct bcma_device *dev, unsigned int irq)
1403 static const char *irq_name[] = {"2(S)", "3", "4", "5", "6", "D", "I"};
1404 - printk(KERN_INFO KBUILD_MODNAME ": core 0x%04x, irq :", dev->id.id);
1405 + printk(KERN_DEBUG KBUILD_MODNAME ": core 0x%04x, irq :", dev->id.id);
1406 for (i = 0; i <= 6; i++)
1407 printk(" %s%s", irq_name[i], i == irq ? "*" : " ");
1409 @@ -171,7 +222,7 @@ u32 bcma_cpu_clock(struct bcma_drv_mips
1410 struct bcma_bus *bus = mcore->core->bus;
1412 if (bus->drv_cc.capabilities & BCMA_CC_CAP_PMU)
1413 - return bcma_pmu_get_clockcpu(&bus->drv_cc);
1414 + return bcma_pmu_get_cpu_clock(&bus->drv_cc);
1416 bcma_err(bus, "No PMU available, need this to get the cpu clock\n");
1418 @@ -181,85 +232,143 @@ EXPORT_SYMBOL(bcma_cpu_clock);
1419 static void bcma_core_mips_flash_detect(struct bcma_drv_mips *mcore)
1421 struct bcma_bus *bus = mcore->core->bus;
1422 + struct bcma_drv_cc *cc = &bus->drv_cc;
1423 + struct bcma_pflash *pflash = &cc->pflash;
1425 - switch (bus->drv_cc.capabilities & BCMA_CC_CAP_FLASHT) {
1426 + switch (cc->capabilities & BCMA_CC_CAP_FLASHT) {
1427 case BCMA_CC_FLASHT_STSER:
1428 case BCMA_CC_FLASHT_ATSER:
1429 bcma_debug(bus, "Found serial flash\n");
1430 - bcma_sflash_init(&bus->drv_cc);
1431 + bcma_sflash_init(cc);
1433 case BCMA_CC_FLASHT_PARA:
1434 bcma_debug(bus, "Found parallel flash\n");
1435 - bus->drv_cc.pflash.window = 0x1c000000;
1436 - bus->drv_cc.pflash.window_size = 0x02000000;
1437 + pflash->present = true;
1438 + pflash->window = BCMA_SOC_FLASH2;
1439 + pflash->window_size = BCMA_SOC_FLASH2_SZ;
1441 - if ((bcma_read32(bus->drv_cc.core, BCMA_CC_FLASH_CFG) &
1442 + if ((bcma_read32(cc->core, BCMA_CC_FLASH_CFG) &
1443 BCMA_CC_FLASH_CFG_DS) == 0)
1444 - bus->drv_cc.pflash.buswidth = 1;
1445 + pflash->buswidth = 1;
1447 - bus->drv_cc.pflash.buswidth = 2;
1448 + pflash->buswidth = 2;
1450 + bcma_pflash_data.width = pflash->buswidth;
1451 + bcma_pflash_resource.start = pflash->window;
1452 + bcma_pflash_resource.end = pflash->window + pflash->window_size;
1456 bcma_err(bus, "Flash type not supported\n");
1459 - if (bus->drv_cc.core->id.rev == 38 ||
1460 + if (cc->core->id.rev == 38 ||
1461 bus->chipinfo.id == BCMA_CHIP_ID_BCM4706) {
1462 - if (bus->drv_cc.capabilities & BCMA_CC_CAP_NFLASH) {
1463 + if (cc->capabilities & BCMA_CC_CAP_NFLASH) {
1464 bcma_debug(bus, "Found NAND flash\n");
1465 - bcma_nflash_init(&bus->drv_cc);
1466 + bcma_nflash_init(cc);
1471 +void bcma_core_mips_early_init(struct bcma_drv_mips *mcore)
1473 + struct bcma_bus *bus = mcore->core->bus;
1475 + if (mcore->early_setup_done)
1478 + bcma_chipco_serial_init(&bus->drv_cc);
1479 + bcma_core_mips_flash_detect(mcore);
1481 + mcore->early_setup_done = true;
1484 +static void bcma_fix_i2s_irqflag(struct bcma_bus *bus)
1486 + struct bcma_device *cpu, *pcie, *i2s;
1488 + /* Fixup the interrupts in 4716/4748 for i2s core (2010 Broadcom SDK)
1489 + * (IRQ flags > 7 are ignored when setting the interrupt masks)
1491 + if (bus->chipinfo.id != BCMA_CHIP_ID_BCM4716 &&
1492 + bus->chipinfo.id != BCMA_CHIP_ID_BCM4748)
1495 + cpu = bcma_find_core(bus, BCMA_CORE_MIPS_74K);
1496 + pcie = bcma_find_core(bus, BCMA_CORE_PCIE);
1497 + i2s = bcma_find_core(bus, BCMA_CORE_I2S);
1498 + if (cpu && pcie && i2s &&
1499 + bcma_aread32(cpu, BCMA_MIPS_OOBSELINA74) == 0x08060504 &&
1500 + bcma_aread32(pcie, BCMA_MIPS_OOBSELINA74) == 0x08060504 &&
1501 + bcma_aread32(i2s, BCMA_MIPS_OOBSELOUTA30) == 0x88) {
1502 + bcma_awrite32(cpu, BCMA_MIPS_OOBSELINA74, 0x07060504);
1503 + bcma_awrite32(pcie, BCMA_MIPS_OOBSELINA74, 0x07060504);
1504 + bcma_awrite32(i2s, BCMA_MIPS_OOBSELOUTA30, 0x87);
1506 + "Moved i2s interrupt to oob line 7 instead of 8\n");
1510 void bcma_core_mips_init(struct bcma_drv_mips *mcore)
1512 struct bcma_bus *bus;
1513 struct bcma_device *core;
1514 bus = mcore->core->bus;
1516 - bcma_info(bus, "Initializing MIPS core...\n");
1517 + if (mcore->setup_done)
1520 - if (!mcore->setup_done)
1521 - mcore->assigned_irqs = 1;
1522 + bcma_debug(bus, "Initializing MIPS core...\n");
1524 - /* Assign IRQs to all cores on the bus */
1525 - list_for_each_entry(core, &bus->cores, list) {
1530 - mips_irq = bcma_core_mips_irq(core);
1534 - core->irq = mips_irq + 2;
1535 - if (core->irq > 5)
1537 - switch (core->id.id) {
1538 - case BCMA_CORE_PCI:
1539 - case BCMA_CORE_PCIE:
1540 - case BCMA_CORE_ETHERNET:
1541 - case BCMA_CORE_ETHERNET_GBIT:
1542 - case BCMA_CORE_MAC_GBIT:
1543 - case BCMA_CORE_80211:
1544 - case BCMA_CORE_USB20_HOST:
1545 - /* These devices get their own IRQ line if available,
1546 - * the rest goes on IRQ0
1548 - if (mcore->assigned_irqs <= 4)
1549 - bcma_core_mips_set_irq(core,
1550 - mcore->assigned_irqs++);
1552 + bcma_core_mips_early_init(mcore);
1554 + bcma_fix_i2s_irqflag(bus);
1556 + switch (bus->chipinfo.id) {
1557 + case BCMA_CHIP_ID_BCM4716:
1558 + case BCMA_CHIP_ID_BCM4748:
1559 + bcma_core_mips_set_irq_name(bus, 1, BCMA_CORE_80211, 0);
1560 + bcma_core_mips_set_irq_name(bus, 2, BCMA_CORE_MAC_GBIT, 0);
1561 + bcma_core_mips_set_irq_name(bus, 3, BCMA_CORE_USB20_HOST, 0);
1562 + bcma_core_mips_set_irq_name(bus, 4, BCMA_CORE_PCIE, 0);
1563 + bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_CHIPCOMMON, 0);
1564 + bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_I2S, 0);
1566 + case BCMA_CHIP_ID_BCM5356:
1567 + case BCMA_CHIP_ID_BCM47162:
1568 + case BCMA_CHIP_ID_BCM53572:
1569 + bcma_core_mips_set_irq_name(bus, 1, BCMA_CORE_80211, 0);
1570 + bcma_core_mips_set_irq_name(bus, 2, BCMA_CORE_MAC_GBIT, 0);
1571 + bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_CHIPCOMMON, 0);
1573 + case BCMA_CHIP_ID_BCM5357:
1574 + case BCMA_CHIP_ID_BCM4749:
1575 + bcma_core_mips_set_irq_name(bus, 1, BCMA_CORE_80211, 0);
1576 + bcma_core_mips_set_irq_name(bus, 2, BCMA_CORE_MAC_GBIT, 0);
1577 + bcma_core_mips_set_irq_name(bus, 3, BCMA_CORE_USB20_HOST, 0);
1578 + bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_CHIPCOMMON, 0);
1579 + bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_I2S, 0);
1581 + case BCMA_CHIP_ID_BCM4706:
1582 + bcma_core_mips_set_irq_name(bus, 1, BCMA_CORE_PCIE, 0);
1583 + bcma_core_mips_set_irq_name(bus, 2, BCMA_CORE_4706_MAC_GBIT,
1585 + bcma_core_mips_set_irq_name(bus, 3, BCMA_CORE_PCIE, 1);
1586 + bcma_core_mips_set_irq_name(bus, 4, BCMA_CORE_USB20_HOST, 0);
1587 + bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_4706_CHIPCOMMON,
1591 + list_for_each_entry(core, &bus->cores, list) {
1592 + core->irq = bcma_core_irq(core);
1595 + "Unknown device (0x%x) found, can not configure IRQs\n",
1596 + bus->chipinfo.id);
1598 - bcma_info(bus, "IRQ reconfiguration done\n");
1599 + bcma_debug(bus, "IRQ reconfiguration done\n");
1600 bcma_core_mips_dump_irq(bus);
1602 - if (mcore->setup_done)
1605 - bcma_chipco_serial_init(&bus->drv_cc);
1606 - bcma_core_mips_flash_detect(mcore);
1607 mcore->setup_done = true;
1609 --- a/drivers/bcma/driver_pci.c
1610 +++ b/drivers/bcma/driver_pci.c
1611 @@ -51,7 +51,7 @@ static void bcma_pcie_mdio_set_phy(struc
1612 v = pcicore_read32(pc, BCMA_CORE_PCI_MDIO_CONTROL);
1613 if (v & BCMA_CORE_PCI_MDIOCTL_ACCESS_DONE)
1616 + usleep_range(1000, 2000);
1620 @@ -92,7 +92,7 @@ static u16 bcma_pcie_mdio_read(struct bc
1621 ret = pcicore_read32(pc, BCMA_CORE_PCI_MDIO_DATA);
1625 + usleep_range(1000, 2000);
1627 pcicore_write32(pc, BCMA_CORE_PCI_MDIO_CONTROL, 0);
1629 @@ -132,7 +132,7 @@ static void bcma_pcie_mdio_write(struct
1630 v = pcicore_read32(pc, BCMA_CORE_PCI_MDIO_CONTROL);
1631 if (v & BCMA_CORE_PCI_MDIOCTL_ACCESS_DONE)
1634 + usleep_range(1000, 2000);
1636 pcicore_write32(pc, BCMA_CORE_PCI_MDIO_CONTROL, 0);
1638 --- a/drivers/bcma/driver_pci_host.c
1639 +++ b/drivers/bcma/driver_pci_host.c
1640 @@ -35,11 +35,6 @@ bool __devinit bcma_core_pci_is_in_hostm
1641 chipid_top != 0x5300)
1644 - if (bus->sprom.boardflags_lo & BCMA_CORE_PCI_BFL_NOPCI) {
1645 - bcma_info(bus, "This PCI core is disabled and not working\n");
1649 bcma_core_enable(pc->core, 0);
1651 return !mips_busprobe32(tmp, pc->core->io_addr);
1652 @@ -99,19 +94,19 @@ static int bcma_extpci_read_config(struc
1654 /* we support only two functions on device 0 */
1659 /* accesses to config registers with offsets >= 256
1660 * requires indirect access.
1662 if (off >= PCI_CONFIG_SPACE_SIZE) {
1663 addr = (func << 12);
1664 - addr |= (off & 0x0FFF);
1665 + addr |= (off & 0x0FFC);
1666 val = bcma_pcie_read_config(pc, addr);
1668 addr = BCMA_CORE_PCI_PCICFG0;
1669 addr |= (func << 8);
1670 - addr |= (off & 0xfc);
1671 + addr |= (off & 0xFC);
1672 val = pcicore_read32(pc, addr);
1675 @@ -124,11 +119,9 @@ static int bcma_extpci_read_config(struc
1678 if (mips_busprobe32(val, mmio)) {
1684 - val = readl(mmio);
1686 val >>= (8 * (off & 3));
1688 @@ -156,7 +149,7 @@ static int bcma_extpci_write_config(stru
1689 const void *buf, int len)
1692 - u32 addr = 0, val = 0;
1694 void __iomem *mmio = 0;
1695 u16 chipid = pc->core->bus->chipinfo.id;
1697 @@ -164,16 +157,22 @@ static int bcma_extpci_write_config(stru
1698 if (unlikely(len != 1 && len != 2 && len != 4))
1701 + /* we support only two functions on device 0 */
1705 /* accesses to config registers with offsets >= 256
1706 * requires indirect access.
1708 - if (off < PCI_CONFIG_SPACE_SIZE) {
1709 - addr = pc->core->addr + BCMA_CORE_PCI_PCICFG0;
1710 + if (off >= PCI_CONFIG_SPACE_SIZE) {
1711 + addr = (func << 12);
1712 + addr |= (off & 0x0FFC);
1713 + val = bcma_pcie_read_config(pc, addr);
1715 + addr = BCMA_CORE_PCI_PCICFG0;
1716 addr |= (func << 8);
1717 - addr |= (off & 0xfc);
1718 - mmio = ioremap_nocache(addr, sizeof(val));
1721 + addr |= (off & 0xFC);
1722 + val = pcicore_read32(pc, addr);
1725 addr = bcma_get_cfgspace_addr(pc, dev, func, off);
1726 @@ -185,19 +184,17 @@ static int bcma_extpci_write_config(stru
1729 if (mips_busprobe32(val, mmio)) {
1738 - val = readl(mmio);
1739 val &= ~(0xFF << (8 * (off & 3)));
1740 val |= *((const u8 *)buf) << (8 * (off & 3));
1743 - val = readl(mmio);
1744 val &= ~(0xFFFF << (8 * (off & 3)));
1745 val |= *((const u16 *)buf) << (8 * (off & 3));
1747 @@ -205,13 +202,14 @@ static int bcma_extpci_write_config(stru
1748 val = *((const u32 *)buf);
1751 - if (dev == 0 && !addr) {
1753 /* accesses to config registers with offsets >= 256
1754 * requires indirect access.
1756 - addr = (func << 12);
1757 - addr |= (off & 0x0FFF);
1758 - bcma_pcie_write_config(pc, addr, val);
1759 + if (off >= PCI_CONFIG_SPACE_SIZE)
1760 + bcma_pcie_write_config(pc, addr, val);
1762 + pcicore_write32(pc, addr, val);
1766 @@ -282,7 +280,7 @@ static u8 __devinit bcma_find_pci_capabi
1767 /* check for Header type 0 */
1768 bcma_extpci_read_config(pc, dev, func, PCI_HEADER_TYPE, &byte_val,
1770 - if ((byte_val & 0x7f) != PCI_HEADER_TYPE_NORMAL)
1771 + if ((byte_val & 0x7F) != PCI_HEADER_TYPE_NORMAL)
1774 /* check if the capability pointer field exists */
1775 @@ -396,12 +394,19 @@ void __devinit bcma_core_pci_hostmode_in
1777 bcma_info(bus, "PCIEcore in host mode found\n");
1779 + if (bus->sprom.boardflags_lo & BCMA_CORE_PCI_BFL_NOPCI) {
1780 + bcma_info(bus, "This PCIE core is disabled and not working\n");
1784 pc_host = kzalloc(sizeof(*pc_host), GFP_KERNEL);
1786 bcma_err(bus, "can not allocate memory");
1790 + spin_lock_init(&pc_host->cfgspace_lock);
1792 pc->host_controller = pc_host;
1793 pc_host->pci_controller.io_resource = &pc_host->io_resource;
1794 pc_host->pci_controller.mem_resource = &pc_host->mem_resource;
1795 @@ -425,9 +430,9 @@ void __devinit bcma_core_pci_hostmode_in
1796 pc_host->io_resource.flags = IORESOURCE_IO | IORESOURCE_PCI_FIXED;
1800 + usleep_range(3000, 5000);
1801 pcicore_write32(pc, BCMA_CORE_PCI_CTL, BCMA_CORE_PCI_CTL_RST_OE);
1804 pcicore_write32(pc, BCMA_CORE_PCI_CTL, BCMA_CORE_PCI_CTL_RST |
1805 BCMA_CORE_PCI_CTL_RST_OE);
1807 @@ -452,6 +457,8 @@ void __devinit bcma_core_pci_hostmode_in
1808 pc_host->mem_resource.start = BCMA_SOC_PCI_MEM;
1809 pc_host->mem_resource.end = BCMA_SOC_PCI_MEM +
1810 BCMA_SOC_PCI_MEM_SZ - 1;
1811 + pc_host->io_resource.start = 0x100;
1812 + pc_host->io_resource.end = 0x47F;
1813 pci_membase_1G = BCMA_SOC_PCIE_DMA_H32;
1814 pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI0,
1815 tmp | BCMA_SOC_PCI_MEM);
1816 @@ -459,6 +466,8 @@ void __devinit bcma_core_pci_hostmode_in
1817 pc_host->mem_resource.start = BCMA_SOC_PCI1_MEM;
1818 pc_host->mem_resource.end = BCMA_SOC_PCI1_MEM +
1819 BCMA_SOC_PCI_MEM_SZ - 1;
1820 + pc_host->io_resource.start = 0x480;
1821 + pc_host->io_resource.end = 0x7FF;
1822 pci_membase_1G = BCMA_SOC_PCIE1_DMA_H32;
1823 pc_host->host_cfg_addr = BCMA_SOC_PCI1_CFG;
1824 pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI0,
1825 @@ -481,10 +490,21 @@ void __devinit bcma_core_pci_hostmode_in
1826 * before issuing configuration requests to PCI Express
1832 bcma_core_pci_enable_crs(pc);
1834 + if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4706 ||
1835 + bus->chipinfo.id == BCMA_CHIP_ID_BCM4716) {
1837 + bcma_extpci_read_config(pc, 0, 0, BCMA_CORE_PCI_CFG_DEVCTRL,
1838 + &val16, sizeof(val16));
1839 + val16 |= (2 << 5); /* Max payload size of 512 */
1840 + val16 |= (2 << 12); /* MRRS 512 */
1841 + bcma_extpci_write_config(pc, 0, 0, BCMA_CORE_PCI_CFG_DEVCTRL,
1842 + &val16, sizeof(val16));
1845 /* Enable PCI bridge BAR0 memory & master access */
1846 tmp = PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
1847 bcma_extpci_write_config(pc, 0, 0, PCI_COMMAND, &tmp, sizeof(tmp));
1848 @@ -501,7 +521,7 @@ void __devinit bcma_core_pci_hostmode_in
1849 set_io_port_base(pc_host->pci_controller.io_map_base);
1850 /* Give some time to the PCI controller to configure itself with the new
1851 * values. Not waiting at this point causes crashes of the machine. */
1853 + usleep_range(10000, 15000);
1854 register_pci_controller(&pc_host->pci_controller);
1857 @@ -534,7 +554,7 @@ DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_
1858 static void bcma_core_pci_fixup_addresses(struct pci_dev *dev)
1860 struct resource *res;
1864 if (dev->bus->ops->read != bcma_core_pci_hostmode_read_config) {
1865 /* This is not a device on the PCI-core bridge. */
1866 @@ -547,8 +567,12 @@ static void bcma_core_pci_fixup_addresse
1868 for (pos = 0; pos < 6; pos++) {
1869 res = &dev->resource[pos];
1870 - if (res->flags & (IORESOURCE_IO | IORESOURCE_MEM))
1871 - pci_assign_resource(dev, pos);
1872 + if (res->flags & (IORESOURCE_IO | IORESOURCE_MEM)) {
1873 + err = pci_assign_resource(dev, pos);
1875 + pr_err("PCI: Problem fixing up the addresses on %s\n",
1880 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, bcma_core_pci_fixup_addresses);
1881 @@ -569,7 +593,7 @@ int bcma_core_pci_plat_dev_init(struct p
1882 pr_info("PCI: Fixing up device %s\n", pci_name(dev));
1884 /* Fix up interrupt lines */
1885 - dev->irq = bcma_core_mips_irq(pc_host->pdev->core) + 2;
1886 + dev->irq = bcma_core_irq(pc_host->pdev->core);
1887 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
1890 @@ -588,6 +612,6 @@ int bcma_core_pci_pcibios_map_irq(const
1892 pc_host = container_of(dev->bus->ops, struct bcma_drv_pci_host,
1894 - return bcma_core_mips_irq(pc_host->pdev->core) + 2;
1895 + return bcma_core_irq(pc_host->pdev->core);
1897 EXPORT_SYMBOL(bcma_core_pci_pcibios_map_irq);
1898 --- a/drivers/bcma/host_pci.c
1899 +++ b/drivers/bcma/host_pci.c
1900 @@ -77,8 +77,8 @@ static void bcma_host_pci_write32(struct
1903 #ifdef CONFIG_BCMA_BLOCKIO
1904 -void bcma_host_pci_block_read(struct bcma_device *core, void *buffer,
1905 - size_t count, u16 offset, u8 reg_width)
1906 +static void bcma_host_pci_block_read(struct bcma_device *core, void *buffer,
1907 + size_t count, u16 offset, u8 reg_width)
1909 void __iomem *addr = core->bus->mmio + offset;
1910 if (core->bus->mapped_core != core)
1911 @@ -100,8 +100,9 @@ void bcma_host_pci_block_read(struct bcm
1915 -void bcma_host_pci_block_write(struct bcma_device *core, const void *buffer,
1916 - size_t count, u16 offset, u8 reg_width)
1917 +static void bcma_host_pci_block_write(struct bcma_device *core,
1918 + const void *buffer, size_t count,
1919 + u16 offset, u8 reg_width)
1921 void __iomem *addr = core->bus->mmio + offset;
1922 if (core->bus->mapped_core != core)
1923 @@ -139,7 +140,7 @@ static void bcma_host_pci_awrite32(struc
1924 iowrite32(value, core->bus->mmio + (1 * BCMA_CORE_SIZE) + offset);
1927 -const struct bcma_host_ops bcma_host_pci_ops = {
1928 +static const struct bcma_host_ops bcma_host_pci_ops = {
1929 .read8 = bcma_host_pci_read8,
1930 .read16 = bcma_host_pci_read16,
1931 .read32 = bcma_host_pci_read32,
1932 @@ -237,7 +238,7 @@ static void __devexit bcma_host_pci_remo
1933 pci_set_drvdata(dev, NULL);
1937 +#ifdef CONFIG_PM_SLEEP
1938 static int bcma_host_pci_suspend(struct device *dev)
1940 struct pci_dev *pdev = to_pci_dev(dev);
1941 @@ -260,11 +261,11 @@ static SIMPLE_DEV_PM_OPS(bcma_pm_ops, bc
1942 bcma_host_pci_resume);
1943 #define BCMA_PM_OPS (&bcma_pm_ops)
1945 -#else /* CONFIG_PM */
1946 +#else /* CONFIG_PM_SLEEP */
1948 #define BCMA_PM_OPS NULL
1950 -#endif /* CONFIG_PM */
1951 +#endif /* CONFIG_PM_SLEEP */
1953 static DEFINE_PCI_DEVICE_TABLE(bcma_pci_bridge_tbl) = {
1954 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x0576) },
1955 @@ -272,7 +273,9 @@ static DEFINE_PCI_DEVICE_TABLE(bcma_pci_
1956 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4331) },
1957 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4353) },
1958 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4357) },
1959 + { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4358) },
1960 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4359) },
1961 + { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4365) },
1962 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4727) },
1965 --- a/drivers/bcma/host_soc.c
1966 +++ b/drivers/bcma/host_soc.c
1967 @@ -143,7 +143,7 @@ static void bcma_host_soc_awrite32(struc
1968 writel(value, core->io_wrap + offset);
1971 -const struct bcma_host_ops bcma_host_soc_ops = {
1972 +static const struct bcma_host_ops bcma_host_soc_ops = {
1973 .read8 = bcma_host_soc_read8,
1974 .read16 = bcma_host_soc_read16,
1975 .read32 = bcma_host_soc_read32,
1976 --- a/drivers/bcma/main.c
1977 +++ b/drivers/bcma/main.c
1980 #include "bcma_private.h"
1981 #include <linux/module.h>
1982 +#include <linux/platform_device.h>
1983 #include <linux/bcma/bcma.h>
1984 #include <linux/slab.h>
1986 @@ -80,6 +81,37 @@ struct bcma_device *bcma_find_core(struc
1988 EXPORT_SYMBOL_GPL(bcma_find_core);
1990 +struct bcma_device *bcma_find_core_unit(struct bcma_bus *bus, u16 coreid,
1993 + struct bcma_device *core;
1995 + list_for_each_entry(core, &bus->cores, list) {
1996 + if (core->id.id == coreid && core->core_unit == unit)
2002 +bool bcma_wait_value(struct bcma_device *core, u16 reg, u32 mask, u32 value,
2005 + unsigned long deadline = jiffies + timeout;
2009 + val = bcma_read32(core, reg);
2010 + if ((val & mask) == value)
2014 + } while (!time_after_eq(jiffies, deadline));
2016 + bcma_warn(core->bus, "Timeout waiting for register 0x%04X!\n", reg);
2021 static void bcma_release_core_dev(struct device *dev)
2023 struct bcma_device *core = container_of(dev, struct bcma_device, dev);
2024 @@ -107,6 +139,11 @@ static int bcma_register_cores(struct bc
2028 + /* Only first GMAC core on BCM4706 is connected and working */
2029 + if (core->id.id == BCMA_CORE_4706_MAC_GBIT &&
2030 + core->core_unit > 0)
2033 core->dev.release = bcma_release_core_dev;
2034 core->dev.bus = &bcma_bus_type;
2035 dev_set_name(&core->dev, "bcma%d:%d", bus->num, dev_id);
2036 @@ -136,6 +173,41 @@ static int bcma_register_cores(struct bc
2040 +#ifdef CONFIG_BCMA_DRIVER_MIPS
2041 + if (bus->drv_cc.pflash.present) {
2042 + err = platform_device_register(&bcma_pflash_dev);
2044 + bcma_err(bus, "Error registering parallel flash\n");
2048 +#ifdef CONFIG_BCMA_SFLASH
2049 + if (bus->drv_cc.sflash.present) {
2050 + err = platform_device_register(&bcma_sflash_dev);
2052 + bcma_err(bus, "Error registering serial flash\n");
2056 +#ifdef CONFIG_BCMA_NFLASH
2057 + if (bus->drv_cc.nflash.present) {
2058 + err = platform_device_register(&bcma_nflash_dev);
2060 + bcma_err(bus, "Error registering NAND flash\n");
2063 + err = bcma_gpio_init(&bus->drv_cc);
2064 + if (err == -ENOTSUPP)
2065 + bcma_debug(bus, "GPIO driver not activated\n");
2067 + bcma_err(bus, "Error registering GPIO driver: %i\n", err);
2069 + if (bus->hosttype == BCMA_HOSTTYPE_SOC) {
2070 + err = bcma_chipco_watchdog_register(&bus->drv_cc);
2072 + bcma_err(bus, "Error registering watchdog driver\n");
2078 @@ -148,6 +220,8 @@ static void bcma_unregister_cores(struct
2079 if (core->dev_registered)
2080 device_unregister(&core->dev);
2082 + if (bus->hosttype == BCMA_HOSTTYPE_SOC)
2083 + platform_device_unregister(bus->drv_cc.watchdog);
2086 int __devinit bcma_bus_register(struct bcma_bus *bus)
2087 @@ -166,6 +240,20 @@ int __devinit bcma_bus_register(struct b
2091 + /* Early init CC core */
2092 + core = bcma_find_core(bus, bcma_cc_core_id(bus));
2094 + bus->drv_cc.core = core;
2095 + bcma_core_chipcommon_early_init(&bus->drv_cc);
2098 + /* Try to get SPROM */
2099 + err = bcma_sprom_get(bus);
2100 + if (err == -ENOENT) {
2101 + bcma_err(bus, "No SPROM available\n");
2103 + bcma_err(bus, "Failed to get SPROM: %d\n", err);
2106 core = bcma_find_core(bus, bcma_cc_core_id(bus));
2108 @@ -181,10 +269,17 @@ int __devinit bcma_bus_register(struct b
2111 /* Init PCIE core */
2112 - core = bcma_find_core(bus, BCMA_CORE_PCIE);
2113 + core = bcma_find_core_unit(bus, BCMA_CORE_PCIE, 0);
2115 - bus->drv_pci.core = core;
2116 - bcma_core_pci_init(&bus->drv_pci);
2117 + bus->drv_pci[0].core = core;
2118 + bcma_core_pci_init(&bus->drv_pci[0]);
2121 + /* Init PCIE core */
2122 + core = bcma_find_core_unit(bus, BCMA_CORE_PCIE, 1);
2124 + bus->drv_pci[1].core = core;
2125 + bcma_core_pci_init(&bus->drv_pci[1]);
2128 /* Init GBIT MAC COMMON core */
2129 @@ -194,13 +289,6 @@ int __devinit bcma_bus_register(struct b
2130 bcma_core_gmac_cmn_init(&bus->drv_gmac_cmn);
2133 - /* Try to get SPROM */
2134 - err = bcma_sprom_get(bus);
2135 - if (err == -ENOENT) {
2136 - bcma_err(bus, "No SPROM available\n");
2138 - bcma_err(bus, "Failed to get SPROM: %d\n", err);
2140 /* Register found cores */
2141 bcma_register_cores(bus);
2143 @@ -211,7 +299,24 @@ int __devinit bcma_bus_register(struct b
2145 void bcma_bus_unregister(struct bcma_bus *bus)
2147 + struct bcma_device *cores[3];
2150 + err = bcma_gpio_unregister(&bus->drv_cc);
2151 + if (err == -EBUSY)
2152 + bcma_err(bus, "Some GPIOs are still in use.\n");
2154 + bcma_err(bus, "Can not unregister GPIO driver: %i\n", err);
2156 + cores[0] = bcma_find_core(bus, BCMA_CORE_MIPS_74K);
2157 + cores[1] = bcma_find_core(bus, BCMA_CORE_PCIE);
2158 + cores[2] = bcma_find_core(bus, BCMA_CORE_4706_MAC_GBIT_COMMON);
2160 bcma_unregister_cores(bus);
2167 int __init bcma_bus_early_register(struct bcma_bus *bus,
2168 @@ -248,18 +353,18 @@ int __init bcma_bus_early_register(struc
2172 - /* Init CC core */
2173 + /* Early init CC core */
2174 core = bcma_find_core(bus, bcma_cc_core_id(bus));
2176 bus->drv_cc.core = core;
2177 - bcma_core_chipcommon_init(&bus->drv_cc);
2178 + bcma_core_chipcommon_early_init(&bus->drv_cc);
2181 - /* Init MIPS core */
2182 + /* Early init MIPS core */
2183 core = bcma_find_core(bus, BCMA_CORE_MIPS_74K);
2185 bus->drv_mips.core = core;
2186 - bcma_core_mips_init(&bus->drv_mips);
2187 + bcma_core_mips_early_init(&bus->drv_mips);
2190 bcma_info(bus, "Early bus registered\n");
2191 --- a/drivers/bcma/scan.c
2192 +++ b/drivers/bcma/scan.c
2193 @@ -84,6 +84,8 @@ static const struct bcma_device_id_name
2194 { BCMA_CORE_I2S, "I2S" },
2195 { BCMA_CORE_SDR_DDR1_MEM_CTL, "SDR/DDR1 Memory Controller" },
2196 { BCMA_CORE_SHIM, "SHIM" },
2197 + { BCMA_CORE_PCIE2, "PCIe Gen2" },
2198 + { BCMA_CORE_ARM_CR4, "ARM CR4" },
2199 { BCMA_CORE_DEFAULT, "Default" },
2202 @@ -137,19 +139,19 @@ static void bcma_scan_switch_core(struct
2206 -static u32 bcma_erom_get_ent(struct bcma_bus *bus, u32 **eromptr)
2207 +static u32 bcma_erom_get_ent(struct bcma_bus *bus, u32 __iomem **eromptr)
2209 u32 ent = readl(*eromptr);
2214 -static void bcma_erom_push_ent(u32 **eromptr)
2215 +static void bcma_erom_push_ent(u32 __iomem **eromptr)
2220 -static s32 bcma_erom_get_ci(struct bcma_bus *bus, u32 **eromptr)
2221 +static s32 bcma_erom_get_ci(struct bcma_bus *bus, u32 __iomem **eromptr)
2223 u32 ent = bcma_erom_get_ent(bus, eromptr);
2224 if (!(ent & SCAN_ER_VALID))
2225 @@ -159,14 +161,14 @@ static s32 bcma_erom_get_ci(struct bcma_
2229 -static bool bcma_erom_is_end(struct bcma_bus *bus, u32 **eromptr)
2230 +static bool bcma_erom_is_end(struct bcma_bus *bus, u32 __iomem **eromptr)
2232 u32 ent = bcma_erom_get_ent(bus, eromptr);
2233 bcma_erom_push_ent(eromptr);
2234 return (ent == (SCAN_ER_TAG_END | SCAN_ER_VALID));
2237 -static bool bcma_erom_is_bridge(struct bcma_bus *bus, u32 **eromptr)
2238 +static bool bcma_erom_is_bridge(struct bcma_bus *bus, u32 __iomem **eromptr)
2240 u32 ent = bcma_erom_get_ent(bus, eromptr);
2241 bcma_erom_push_ent(eromptr);
2242 @@ -175,7 +177,7 @@ static bool bcma_erom_is_bridge(struct b
2243 ((ent & SCAN_ADDR_TYPE) == SCAN_ADDR_TYPE_BRIDGE));
2246 -static void bcma_erom_skip_component(struct bcma_bus *bus, u32 **eromptr)
2247 +static void bcma_erom_skip_component(struct bcma_bus *bus, u32 __iomem **eromptr)
2251 @@ -189,7 +191,7 @@ static void bcma_erom_skip_component(str
2252 bcma_erom_push_ent(eromptr);
2255 -static s32 bcma_erom_get_mst_port(struct bcma_bus *bus, u32 **eromptr)
2256 +static s32 bcma_erom_get_mst_port(struct bcma_bus *bus, u32 __iomem **eromptr)
2258 u32 ent = bcma_erom_get_ent(bus, eromptr);
2259 if (!(ent & SCAN_ER_VALID))
2260 @@ -199,7 +201,7 @@ static s32 bcma_erom_get_mst_port(struct
2264 -static s32 bcma_erom_get_addr_desc(struct bcma_bus *bus, u32 **eromptr,
2265 +static s32 bcma_erom_get_addr_desc(struct bcma_bus *bus, u32 __iomem **eromptr,
2268 u32 addrl, addrh, sizel, sizeh = 0;
2269 --- a/drivers/bcma/sprom.c
2270 +++ b/drivers/bcma/sprom.c
2271 @@ -72,12 +72,12 @@ fail:
2273 **************************************************/
2275 -static void bcma_sprom_read(struct bcma_bus *bus, u16 offset, u16 *sprom)
2276 +static void bcma_sprom_read(struct bcma_bus *bus, u16 offset, u16 *sprom,
2280 - for (i = 0; i < SSB_SPROMSIZE_WORDS_R4; i++)
2281 - sprom[i] = bcma_read16(bus->drv_cc.core,
2282 - offset + (i * 2));
2283 + for (i = 0; i < words; i++)
2284 + sprom[i] = bcma_read16(bus->drv_cc.core, offset + (i * 2));
2287 /**************************************************
2288 @@ -124,29 +124,29 @@ static inline u8 bcma_crc8(u8 crc, u8 da
2289 return t[crc ^ data];
2292 -static u8 bcma_sprom_crc(const u16 *sprom)
2293 +static u8 bcma_sprom_crc(const u16 *sprom, size_t words)
2298 - for (word = 0; word < SSB_SPROMSIZE_WORDS_R4 - 1; word++) {
2299 + for (word = 0; word < words - 1; word++) {
2300 crc = bcma_crc8(crc, sprom[word] & 0x00FF);
2301 crc = bcma_crc8(crc, (sprom[word] & 0xFF00) >> 8);
2303 - crc = bcma_crc8(crc, sprom[SSB_SPROMSIZE_WORDS_R4 - 1] & 0x00FF);
2304 + crc = bcma_crc8(crc, sprom[words - 1] & 0x00FF);
2310 -static int bcma_sprom_check_crc(const u16 *sprom)
2311 +static int bcma_sprom_check_crc(const u16 *sprom, size_t words)
2317 - crc = bcma_sprom_crc(sprom);
2318 - tmp = sprom[SSB_SPROMSIZE_WORDS_R4 - 1] & SSB_SPROM_REVISION_CRC;
2319 + crc = bcma_sprom_crc(sprom, words);
2320 + tmp = sprom[words - 1] & SSB_SPROM_REVISION_CRC;
2321 expected_crc = tmp >> SSB_SPROM_REVISION_CRC_SHIFT;
2322 if (crc != expected_crc)
2324 @@ -154,21 +154,25 @@ static int bcma_sprom_check_crc(const u1
2328 -static int bcma_sprom_valid(const u16 *sprom)
2329 +static int bcma_sprom_valid(struct bcma_bus *bus, const u16 *sprom,
2335 - err = bcma_sprom_check_crc(sprom);
2336 + err = bcma_sprom_check_crc(sprom, words);
2340 - revision = sprom[SSB_SPROMSIZE_WORDS_R4 - 1] & SSB_SPROM_REVISION_REV;
2341 - if (revision != 8 && revision != 9) {
2342 + revision = sprom[words - 1] & SSB_SPROM_REVISION_REV;
2343 + if (revision != 8 && revision != 9 && revision != 10) {
2344 pr_err("Unsupported SPROM revision: %d\n", revision);
2348 + bus->sprom.revision = revision;
2349 + bcma_debug(bus, "Found SPROM revision %d\n", revision);
2354 @@ -208,15 +212,13 @@ static void bcma_sprom_extract_r8(struct
2355 BUILD_BUG_ON(ARRAY_SIZE(pwr_info_offset) !=
2356 ARRAY_SIZE(bus->sprom.core_pwr_info));
2358 - bus->sprom.revision = sprom[SSB_SPROMSIZE_WORDS_R4 - 1] &
2359 - SSB_SPROM_REVISION_REV;
2361 for (i = 0; i < 3; i++) {
2362 v = sprom[SPOFF(SSB_SPROM8_IL0MAC) + i];
2363 *(((__be16 *)bus->sprom.il0mac) + i) = cpu_to_be16(v);
2366 SPEX(board_rev, SSB_SPROM8_BOARDREV, ~0, 0);
2367 + SPEX(board_type, SSB_SPROM1_SPID, ~0, 0);
2369 SPEX(txpid2g[0], SSB_SPROM4_TXPID2G01, SSB_SPROM4_TXPID2G0,
2370 SSB_SPROM4_TXPID2G0_SHIFT);
2371 @@ -501,13 +503,15 @@ static bool bcma_sprom_onchip_available(
2372 case BCMA_CHIP_ID_BCM4331:
2373 present = chip_status & BCMA_CC_CHIPST_4331_OTP_PRESENT;
2376 + case BCMA_CHIP_ID_BCM43142:
2377 case BCMA_CHIP_ID_BCM43224:
2378 case BCMA_CHIP_ID_BCM43225:
2379 /* for these chips OTP is always available */
2382 + case BCMA_CHIP_ID_BCM43227:
2383 case BCMA_CHIP_ID_BCM43228:
2384 + case BCMA_CHIP_ID_BCM43428:
2385 present = chip_status & BCMA_CC_CHIPST_43228_OTP_PRESENT;
2388 @@ -547,7 +551,9 @@ int bcma_sprom_get(struct bcma_bus *bus)
2390 u16 offset = BCMA_CC_SPROM;
2393 + size_t sprom_sizes[] = { SSB_SPROMSIZE_WORDS_R4,
2394 + SSB_SPROMSIZE_WORDS_R10, };
2397 if (!bus->drv_cc.core)
2399 @@ -576,29 +582,37 @@ int bcma_sprom_get(struct bcma_bus *bus)
2403 - sprom = kcalloc(SSB_SPROMSIZE_WORDS_R4, sizeof(u16),
2408 if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4331 ||
2409 bus->chipinfo.id == BCMA_CHIP_ID_BCM43431)
2410 bcma_chipco_bcm4331_ext_pa_lines_ctl(&bus->drv_cc, false);
2412 bcma_debug(bus, "SPROM offset 0x%x\n", offset);
2413 - bcma_sprom_read(bus, offset, sprom);
2414 + for (i = 0; i < ARRAY_SIZE(sprom_sizes); i++) {
2415 + size_t words = sprom_sizes[i];
2417 + sprom = kcalloc(words, sizeof(u16), GFP_KERNEL);
2421 + bcma_sprom_read(bus, offset, sprom, words);
2422 + err = bcma_sprom_valid(bus, sprom, words);
2429 if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4331 ||
2430 bus->chipinfo.id == BCMA_CHIP_ID_BCM43431)
2431 bcma_chipco_bcm4331_ext_pa_lines_ctl(&bus->drv_cc, true);
2433 - err = bcma_sprom_valid(sprom);
2437 - bcma_sprom_extract_r8(bus, sprom);
2439 + bcma_warn(bus, "Invalid SPROM read from the PCIe card, trying to use fallback SPROM\n");
2440 + err = bcma_fill_sprom_with_fallback(bus, &bus->sprom);
2442 + bcma_sprom_extract_r8(bus, sprom);
2450 --- a/include/linux/bcma/bcma.h
2451 +++ b/include/linux/bcma/bcma.h
2453 #include <linux/bcma/bcma_driver_gmac_cmn.h>
2454 #include <linux/ssb/ssb.h> /* SPROM sharing */
2456 -#include "bcma_regs.h"
2457 +#include <linux/bcma/bcma_regs.h>
2461 @@ -134,12 +134,17 @@ struct bcma_host_ops {
2462 #define BCMA_CORE_I2S 0x834
2463 #define BCMA_CORE_SDR_DDR1_MEM_CTL 0x835 /* SDR/DDR1 memory controller core */
2464 #define BCMA_CORE_SHIM 0x837 /* SHIM component in ubus/6362 */
2465 +#define BCMA_CORE_PHY_AC 0x83B
2466 +#define BCMA_CORE_PCIE2 0x83C /* PCI Express Gen2 */
2467 +#define BCMA_CORE_USB30_DEV 0x83D
2468 +#define BCMA_CORE_ARM_CR4 0x83E
2469 #define BCMA_CORE_DEFAULT 0xFFF
2471 #define BCMA_MAX_NR_CORES 16
2473 /* Chip IDs of PCIe devices */
2474 #define BCMA_CHIP_ID_BCM4313 0x4313
2475 +#define BCMA_CHIP_ID_BCM43142 43142
2476 #define BCMA_CHIP_ID_BCM43224 43224
2477 #define BCMA_PKG_ID_BCM43224_FAB_CSM 0x8
2478 #define BCMA_PKG_ID_BCM43224_FAB_SMIC 0xa
2479 @@ -157,6 +162,7 @@ struct bcma_host_ops {
2481 /* Chip IDs of SoCs */
2482 #define BCMA_CHIP_ID_BCM4706 0x5300
2483 +#define BCMA_PKG_ID_BCM4706L 1
2484 #define BCMA_CHIP_ID_BCM4716 0x4716
2485 #define BCMA_PKG_ID_BCM4716 8
2486 #define BCMA_PKG_ID_BCM4717 9
2487 @@ -166,7 +172,65 @@ struct bcma_host_ops {
2488 #define BCMA_CHIP_ID_BCM4749 0x4749
2489 #define BCMA_CHIP_ID_BCM5356 0x5356
2490 #define BCMA_CHIP_ID_BCM5357 0x5357
2491 +#define BCMA_PKG_ID_BCM5358 9
2492 +#define BCMA_PKG_ID_BCM47186 10
2493 +#define BCMA_PKG_ID_BCM5357 11
2494 #define BCMA_CHIP_ID_BCM53572 53572
2495 +#define BCMA_PKG_ID_BCM47188 9
2497 +/* Board types (on PCI usually equals to the subsystem dev id) */
2499 +#define BCMA_BOARD_TYPE_BCM94313BU 0X050F
2500 +#define BCMA_BOARD_TYPE_BCM94313HM 0X0510
2501 +#define BCMA_BOARD_TYPE_BCM94313EPA 0X0511
2502 +#define BCMA_BOARD_TYPE_BCM94313HMG 0X051C
2504 +#define BCMA_BOARD_TYPE_BCM94716NR2 0X04CD
2506 +#define BCMA_BOARD_TYPE_BCM943224X21 0X056E
2507 +#define BCMA_BOARD_TYPE_BCM943224X21_FCC 0X00D1
2508 +#define BCMA_BOARD_TYPE_BCM943224X21B 0X00E9
2509 +#define BCMA_BOARD_TYPE_BCM943224M93 0X008B
2510 +#define BCMA_BOARD_TYPE_BCM943224M93A 0X0090
2511 +#define BCMA_BOARD_TYPE_BCM943224X16 0X0093
2512 +#define BCMA_BOARD_TYPE_BCM94322X9 0X008D
2513 +#define BCMA_BOARD_TYPE_BCM94322M35E 0X008E
2515 +#define BCMA_BOARD_TYPE_BCM943228BU8 0X0540
2516 +#define BCMA_BOARD_TYPE_BCM943228BU9 0X0541
2517 +#define BCMA_BOARD_TYPE_BCM943228BU 0X0542
2518 +#define BCMA_BOARD_TYPE_BCM943227HM4L 0X0543
2519 +#define BCMA_BOARD_TYPE_BCM943227HMB 0X0544
2520 +#define BCMA_BOARD_TYPE_BCM943228HM4L 0X0545
2521 +#define BCMA_BOARD_TYPE_BCM943228SD 0X0573
2523 +#define BCMA_BOARD_TYPE_BCM94331X19 0X00D6
2524 +#define BCMA_BOARD_TYPE_BCM94331X28 0X00E4
2525 +#define BCMA_BOARD_TYPE_BCM94331X28B 0X010E
2526 +#define BCMA_BOARD_TYPE_BCM94331PCIEBT3AX 0X00E4
2527 +#define BCMA_BOARD_TYPE_BCM94331X12_2G 0X00EC
2528 +#define BCMA_BOARD_TYPE_BCM94331X12_5G 0X00ED
2529 +#define BCMA_BOARD_TYPE_BCM94331X29B 0X00EF
2530 +#define BCMA_BOARD_TYPE_BCM94331CSAX 0X00EF
2531 +#define BCMA_BOARD_TYPE_BCM94331X19C 0X00F5
2532 +#define BCMA_BOARD_TYPE_BCM94331X33 0X00F4
2533 +#define BCMA_BOARD_TYPE_BCM94331BU 0X0523
2534 +#define BCMA_BOARD_TYPE_BCM94331S9BU 0X0524
2535 +#define BCMA_BOARD_TYPE_BCM94331MC 0X0525
2536 +#define BCMA_BOARD_TYPE_BCM94331MCI 0X0526
2537 +#define BCMA_BOARD_TYPE_BCM94331PCIEBT4 0X0527
2538 +#define BCMA_BOARD_TYPE_BCM94331HM 0X0574
2539 +#define BCMA_BOARD_TYPE_BCM94331PCIEDUAL 0X059B
2540 +#define BCMA_BOARD_TYPE_BCM94331MCH5 0X05A9
2541 +#define BCMA_BOARD_TYPE_BCM94331CS 0X05C6
2542 +#define BCMA_BOARD_TYPE_BCM94331CD 0X05DA
2544 +#define BCMA_BOARD_TYPE_BCM953572BU 0X058D
2545 +#define BCMA_BOARD_TYPE_BCM953572NR2 0X058E
2546 +#define BCMA_BOARD_TYPE_BCM947188NR2 0X058F
2547 +#define BCMA_BOARD_TYPE_BCM953572SDRNR2 0X0590
2549 +#define BCMA_BOARD_TYPE_BCM943142HM 0X05E0
2551 struct bcma_device {
2552 struct bcma_bus *bus;
2553 @@ -251,7 +315,7 @@ struct bcma_bus {
2556 struct bcma_drv_cc drv_cc;
2557 - struct bcma_drv_pci drv_pci;
2558 + struct bcma_drv_pci drv_pci[2];
2559 struct bcma_drv_mips drv_mips;
2560 struct bcma_drv_gmac_cmn drv_gmac_cmn;
2562 @@ -345,6 +409,7 @@ extern void bcma_core_set_clockmode(stru
2563 enum bcma_clkmode clkmode);
2564 extern void bcma_core_pll_ctl(struct bcma_device *core, u32 req, u32 status,
2566 +extern u32 bcma_chipco_pll_read(struct bcma_drv_cc *cc, u32 offset);
2567 #define BCMA_DMA_TRANSLATION_MASK 0xC0000000
2568 #define BCMA_DMA_TRANSLATION_NONE 0x00000000
2569 #define BCMA_DMA_TRANSLATION_DMA32_CMT 0x40000000 /* Client Mode Translation for 32-bit DMA */
2570 --- a/include/linux/bcma/bcma_driver_chipcommon.h
2571 +++ b/include/linux/bcma/bcma_driver_chipcommon.h
2573 #ifndef LINUX_BCMA_DRIVER_CC_H_
2574 #define LINUX_BCMA_DRIVER_CC_H_
2576 +#include <linux/platform_device.h>
2577 +#include <linux/gpio.h>
2579 /** ChipCommon core registers. **/
2580 #define BCMA_CC_ID 0x0000
2581 #define BCMA_CC_ID_ID 0x0000FFFF
2583 #define BCMA_CC_FLASHT_NONE 0x00000000 /* No flash */
2584 #define BCMA_CC_FLASHT_STSER 0x00000100 /* ST serial flash */
2585 #define BCMA_CC_FLASHT_ATSER 0x00000200 /* Atmel serial flash */
2586 -#define BCMA_CC_FLASHT_NFLASH 0x00000200 /* NAND flash */
2587 +#define BCMA_CC_FLASHT_NAND 0x00000300 /* NAND flash */
2588 #define BCMA_CC_FLASHT_PARA 0x00000700 /* Parallel flash */
2589 #define BCMA_CC_CAP_PLLT 0x00038000 /* PLL Type */
2590 #define BCMA_PLLTYPE_NONE 0x00000000
2592 #define BCMA_CC_CHIPST_4706_SFLASH_TYPE BIT(2) /* 0: 8b-p/ST-s flash, 1: 16b-p/Atmal-s flash */
2593 #define BCMA_CC_CHIPST_4706_MIPS_BENDIAN BIT(3) /* 0: little, 1: big endian */
2594 #define BCMA_CC_CHIPST_4706_PCIE1_DISABLE BIT(5) /* PCIE1 enable strap pin */
2595 +#define BCMA_CC_CHIPST_5357_NAND_BOOT BIT(4) /* NAND boot, valid for CC rev 38 and/or BCM5357 */
2596 +#define BCMA_CC_CHIPST_4360_XTAL_40MZ 0x00000001
2597 #define BCMA_CC_JCMD 0x0030 /* Rev >= 10 only */
2598 #define BCMA_CC_JCMD_START 0x80000000
2599 #define BCMA_CC_JCMD_BUSY 0x80000000
2600 @@ -266,6 +271,29 @@
2601 #define BCMA_CC_SROM_CONTROL_SIZE_16K 0x00000004
2602 #define BCMA_CC_SROM_CONTROL_SIZE_SHIFT 1
2603 #define BCMA_CC_SROM_CONTROL_PRESENT 0x00000001
2604 +/* Block 0x140 - 0x190 registers are chipset specific */
2605 +#define BCMA_CC_4706_FLASHSCFG 0x18C /* Flash struct configuration */
2606 +#define BCMA_CC_4706_FLASHSCFG_MASK 0x000000ff
2607 +#define BCMA_CC_4706_FLASHSCFG_SF1 0x00000001 /* 2nd serial flash present */
2608 +#define BCMA_CC_4706_FLASHSCFG_PF1 0x00000002 /* 2nd parallel flash present */
2609 +#define BCMA_CC_4706_FLASHSCFG_SF1_TYPE 0x00000004 /* 2nd serial flash type : 0 : ST, 1 : Atmel */
2610 +#define BCMA_CC_4706_FLASHSCFG_NF1 0x00000008 /* 2nd NAND flash present */
2611 +#define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_MASK 0x000000f0
2612 +#define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_4MB 0x00000010 /* 4MB */
2613 +#define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_8MB 0x00000020 /* 8MB */
2614 +#define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_16MB 0x00000030 /* 16MB */
2615 +#define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_32MB 0x00000040 /* 32MB */
2616 +#define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_64MB 0x00000050 /* 64MB */
2617 +#define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_128MB 0x00000060 /* 128MB */
2618 +#define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_256MB 0x00000070 /* 256MB */
2619 +/* NAND flash registers for BCM4706 (corerev = 31) */
2620 +#define BCMA_CC_NFLASH_CTL 0x01A0
2621 +#define BCMA_CC_NFLASH_CTL_ERR 0x08000000
2622 +#define BCMA_CC_NFLASH_CONF 0x01A4
2623 +#define BCMA_CC_NFLASH_COL_ADDR 0x01A8
2624 +#define BCMA_CC_NFLASH_ROW_ADDR 0x01AC
2625 +#define BCMA_CC_NFLASH_DATA 0x01B0
2626 +#define BCMA_CC_NFLASH_WAITCNT0 0x01B4
2627 /* 0x1E0 is defined as shared BCMA_CLKCTLST */
2628 #define BCMA_CC_HW_WORKAROUND 0x01E4 /* Hardware workaround (rev >= 20) */
2629 #define BCMA_CC_UART0_DATA 0x0300
2631 #define BCMA_CC_PMU_CTL 0x0600 /* PMU control */
2632 #define BCMA_CC_PMU_CTL_ILP_DIV 0xFFFF0000 /* ILP div mask */
2633 #define BCMA_CC_PMU_CTL_ILP_DIV_SHIFT 16
2634 +#define BCMA_CC_PMU_CTL_RES 0x00006000 /* reset control mask */
2635 +#define BCMA_CC_PMU_CTL_RES_SHIFT 13
2636 +#define BCMA_CC_PMU_CTL_RES_RELOAD 0x2 /* reload POR values */
2637 #define BCMA_CC_PMU_CTL_PLL_UPD 0x00000400
2638 #define BCMA_CC_PMU_CTL_NOILPONW 0x00000200 /* No ILP on wait */
2639 #define BCMA_CC_PMU_CTL_HTREQEN 0x00000100 /* HT req enable */
2641 #define BCMA_CC_PMU_CAP 0x0604 /* PMU capabilities */
2642 #define BCMA_CC_PMU_CAP_REVISION 0x000000FF /* Revision mask */
2643 #define BCMA_CC_PMU_STAT 0x0608 /* PMU status */
2644 +#define BCMA_CC_PMU_STAT_EXT_LPO_AVAIL 0x00000100
2645 +#define BCMA_CC_PMU_STAT_WDRESET 0x00000080
2646 #define BCMA_CC_PMU_STAT_INTPEND 0x00000040 /* Interrupt pending */
2647 #define BCMA_CC_PMU_STAT_SBCLKST 0x00000030 /* Backplane clock status? */
2648 #define BCMA_CC_PMU_STAT_HAVEALP 0x00000008 /* ALP available */
2649 @@ -324,7 +357,66 @@
2650 #define BCMA_CC_REGCTL_DATA 0x065C
2651 #define BCMA_CC_PLLCTL_ADDR 0x0660
2652 #define BCMA_CC_PLLCTL_DATA 0x0664
2653 +#define BCMA_CC_PMU_STRAPOPT 0x0668 /* (corerev >= 28) */
2654 +#define BCMA_CC_PMU_XTAL_FREQ 0x066C /* (pmurev >= 10) */
2655 +#define BCMA_CC_PMU_XTAL_FREQ_ILPCTL_MASK 0x00001FFF
2656 +#define BCMA_CC_PMU_XTAL_FREQ_MEASURE_MASK 0x80000000
2657 +#define BCMA_CC_PMU_XTAL_FREQ_MEASURE_SHIFT 31
2658 #define BCMA_CC_SPROM 0x0800 /* SPROM beginning */
2659 +/* NAND flash MLC controller registers (corerev >= 38) */
2660 +#define BCMA_CC_NAND_REVISION 0x0C00
2661 +#define BCMA_CC_NAND_CMD_START 0x0C04
2662 +#define BCMA_CC_NAND_CMD_ADDR_X 0x0C08
2663 +#define BCMA_CC_NAND_CMD_ADDR 0x0C0C
2664 +#define BCMA_CC_NAND_CMD_END_ADDR 0x0C10
2665 +#define BCMA_CC_NAND_CS_NAND_SELECT 0x0C14
2666 +#define BCMA_CC_NAND_CS_NAND_XOR 0x0C18
2667 +#define BCMA_CC_NAND_SPARE_RD0 0x0C20
2668 +#define BCMA_CC_NAND_SPARE_RD4 0x0C24
2669 +#define BCMA_CC_NAND_SPARE_RD8 0x0C28
2670 +#define BCMA_CC_NAND_SPARE_RD12 0x0C2C
2671 +#define BCMA_CC_NAND_SPARE_WR0 0x0C30
2672 +#define BCMA_CC_NAND_SPARE_WR4 0x0C34
2673 +#define BCMA_CC_NAND_SPARE_WR8 0x0C38
2674 +#define BCMA_CC_NAND_SPARE_WR12 0x0C3C
2675 +#define BCMA_CC_NAND_ACC_CONTROL 0x0C40
2676 +#define BCMA_CC_NAND_CONFIG 0x0C48
2677 +#define BCMA_CC_NAND_TIMING_1 0x0C50
2678 +#define BCMA_CC_NAND_TIMING_2 0x0C54
2679 +#define BCMA_CC_NAND_SEMAPHORE 0x0C58
2680 +#define BCMA_CC_NAND_DEVID 0x0C60
2681 +#define BCMA_CC_NAND_DEVID_X 0x0C64
2682 +#define BCMA_CC_NAND_BLOCK_LOCK_STATUS 0x0C68
2683 +#define BCMA_CC_NAND_INTFC_STATUS 0x0C6C
2684 +#define BCMA_CC_NAND_ECC_CORR_ADDR_X 0x0C70
2685 +#define BCMA_CC_NAND_ECC_CORR_ADDR 0x0C74
2686 +#define BCMA_CC_NAND_ECC_UNC_ADDR_X 0x0C78
2687 +#define BCMA_CC_NAND_ECC_UNC_ADDR 0x0C7C
2688 +#define BCMA_CC_NAND_READ_ERROR_COUNT 0x0C80
2689 +#define BCMA_CC_NAND_CORR_STAT_THRESHOLD 0x0C84
2690 +#define BCMA_CC_NAND_READ_ADDR_X 0x0C90
2691 +#define BCMA_CC_NAND_READ_ADDR 0x0C94
2692 +#define BCMA_CC_NAND_PAGE_PROGRAM_ADDR_X 0x0C98
2693 +#define BCMA_CC_NAND_PAGE_PROGRAM_ADDR 0x0C9C
2694 +#define BCMA_CC_NAND_COPY_BACK_ADDR_X 0x0CA0
2695 +#define BCMA_CC_NAND_COPY_BACK_ADDR 0x0CA4
2696 +#define BCMA_CC_NAND_BLOCK_ERASE_ADDR_X 0x0CA8
2697 +#define BCMA_CC_NAND_BLOCK_ERASE_ADDR 0x0CAC
2698 +#define BCMA_CC_NAND_INV_READ_ADDR_X 0x0CB0
2699 +#define BCMA_CC_NAND_INV_READ_ADDR 0x0CB4
2700 +#define BCMA_CC_NAND_BLK_WR_PROTECT 0x0CC0
2701 +#define BCMA_CC_NAND_ACC_CONTROL_CS1 0x0CD0
2702 +#define BCMA_CC_NAND_CONFIG_CS1 0x0CD4
2703 +#define BCMA_CC_NAND_TIMING_1_CS1 0x0CD8
2704 +#define BCMA_CC_NAND_TIMING_2_CS1 0x0CDC
2705 +#define BCMA_CC_NAND_SPARE_RD16 0x0D30
2706 +#define BCMA_CC_NAND_SPARE_RD20 0x0D34
2707 +#define BCMA_CC_NAND_SPARE_RD24 0x0D38
2708 +#define BCMA_CC_NAND_SPARE_RD28 0x0D3C
2709 +#define BCMA_CC_NAND_CACHE_ADDR 0x0D40
2710 +#define BCMA_CC_NAND_CACHE_DATA 0x0D44
2711 +#define BCMA_CC_NAND_CTRL_CONFIG 0x0D48
2712 +#define BCMA_CC_NAND_CTRL_STATUS 0x0D4C
2714 /* Divider allocation in 4716/47162/5356 */
2715 #define BCMA_CC_PMU5_MAINPLL_CPU 1
2716 @@ -350,6 +442,23 @@
2717 #define BCMA_CC_PMU6_4706_PROC_NDIV_MODE_MASK 0x00000007
2718 #define BCMA_CC_PMU6_4706_PROC_NDIV_MODE_SHIFT 0
2721 +#define BCMA_CC_PMU15_PLL_PLLCTL0 0
2722 +#define BCMA_CC_PMU15_PLL_PC0_CLKSEL_MASK 0x00000003
2723 +#define BCMA_CC_PMU15_PLL_PC0_CLKSEL_SHIFT 0
2724 +#define BCMA_CC_PMU15_PLL_PC0_FREQTGT_MASK 0x003FFFFC
2725 +#define BCMA_CC_PMU15_PLL_PC0_FREQTGT_SHIFT 2
2726 +#define BCMA_CC_PMU15_PLL_PC0_PRESCALE_MASK 0x00C00000
2727 +#define BCMA_CC_PMU15_PLL_PC0_PRESCALE_SHIFT 22
2728 +#define BCMA_CC_PMU15_PLL_PC0_KPCTRL_MASK 0x07000000
2729 +#define BCMA_CC_PMU15_PLL_PC0_KPCTRL_SHIFT 24
2730 +#define BCMA_CC_PMU15_PLL_PC0_FCNTCTRL_MASK 0x38000000
2731 +#define BCMA_CC_PMU15_PLL_PC0_FCNTCTRL_SHIFT 27
2732 +#define BCMA_CC_PMU15_PLL_PC0_FDCMODE_MASK 0x40000000
2733 +#define BCMA_CC_PMU15_PLL_PC0_FDCMODE_SHIFT 30
2734 +#define BCMA_CC_PMU15_PLL_PC0_CTRLBIAS_MASK 0x80000000
2735 +#define BCMA_CC_PMU15_PLL_PC0_CTRLBIAS_SHIFT 31
2737 /* ALP clock on pre-PMU chips */
2738 #define BCMA_CC_PMU_ALP_CLOCK 20000000
2739 /* HT clock for systems with PMU-enabled chipcommon */
2740 @@ -415,6 +524,44 @@
2741 /* 4313 Chip specific ChipControl register bits */
2742 #define BCMA_CCTRL_4313_12MA_LED_DRIVE 0x00000007 /* 12 mA drive strengh for later 4313 */
2744 +/* BCM5357 ChipControl register bits */
2745 +#define BCMA_CHIPCTL_5357_EXTPA BIT(14)
2746 +#define BCMA_CHIPCTL_5357_ANT_MUX_2O3 BIT(15)
2747 +#define BCMA_CHIPCTL_5357_NFLASH BIT(16)
2748 +#define BCMA_CHIPCTL_5357_I2S_PINS_ENABLE BIT(18)
2749 +#define BCMA_CHIPCTL_5357_I2CSPI_PINS_ENABLE BIT(19)
2751 +#define BCMA_RES_4314_LPLDO_PU BIT(0)
2752 +#define BCMA_RES_4314_PMU_SLEEP_DIS BIT(1)
2753 +#define BCMA_RES_4314_PMU_BG_PU BIT(2)
2754 +#define BCMA_RES_4314_CBUCK_LPOM_PU BIT(3)
2755 +#define BCMA_RES_4314_CBUCK_PFM_PU BIT(4)
2756 +#define BCMA_RES_4314_CLDO_PU BIT(5)
2757 +#define BCMA_RES_4314_LPLDO2_LVM BIT(6)
2758 +#define BCMA_RES_4314_WL_PMU_PU BIT(7)
2759 +#define BCMA_RES_4314_LNLDO_PU BIT(8)
2760 +#define BCMA_RES_4314_LDO3P3_PU BIT(9)
2761 +#define BCMA_RES_4314_OTP_PU BIT(10)
2762 +#define BCMA_RES_4314_XTAL_PU BIT(11)
2763 +#define BCMA_RES_4314_WL_PWRSW_PU BIT(12)
2764 +#define BCMA_RES_4314_LQ_AVAIL BIT(13)
2765 +#define BCMA_RES_4314_LOGIC_RET BIT(14)
2766 +#define BCMA_RES_4314_MEM_SLEEP BIT(15)
2767 +#define BCMA_RES_4314_MACPHY_RET BIT(16)
2768 +#define BCMA_RES_4314_WL_CORE_READY BIT(17)
2769 +#define BCMA_RES_4314_ILP_REQ BIT(18)
2770 +#define BCMA_RES_4314_ALP_AVAIL BIT(19)
2771 +#define BCMA_RES_4314_MISC_PWRSW_PU BIT(20)
2772 +#define BCMA_RES_4314_SYNTH_PWRSW_PU BIT(21)
2773 +#define BCMA_RES_4314_RX_PWRSW_PU BIT(22)
2774 +#define BCMA_RES_4314_RADIO_PU BIT(23)
2775 +#define BCMA_RES_4314_VCO_LDO_PU BIT(24)
2776 +#define BCMA_RES_4314_AFE_LDO_PU BIT(25)
2777 +#define BCMA_RES_4314_RX_LDO_PU BIT(26)
2778 +#define BCMA_RES_4314_TX_LDO_PU BIT(27)
2779 +#define BCMA_RES_4314_HT_AVAIL BIT(28)
2780 +#define BCMA_RES_4314_MACPHY_CLK_AVAIL BIT(29)
2782 /* Data for the PMU, if available.
2783 * Check availability with ((struct bcma_chipcommon)->capabilities & BCMA_CC_CAP_PMU)
2785 @@ -425,11 +572,36 @@ struct bcma_chipcommon_pmu {
2787 #ifdef CONFIG_BCMA_DRIVER_MIPS
2788 struct bcma_pflash {
2795 +#ifdef CONFIG_BCMA_SFLASH
2796 +struct bcma_sflash {
2803 + struct mtd_info *mtd;
2808 +#ifdef CONFIG_BCMA_NFLASH
2811 +struct bcma_nflash {
2813 + bool boot; /* This is the flash the SoC boots from */
2815 + struct mtd_info *mtd;
2819 struct bcma_serial_port {
2821 unsigned long clockspeed;
2822 @@ -445,15 +617,30 @@ struct bcma_drv_cc {
2824 u32 capabilities_ext;
2826 + u8 early_setup_done:1;
2827 /* Fast Powerup Delay constant */
2828 u16 fast_pwrup_delay;
2829 struct bcma_chipcommon_pmu pmu;
2830 #ifdef CONFIG_BCMA_DRIVER_MIPS
2831 struct bcma_pflash pflash;
2832 +#ifdef CONFIG_BCMA_SFLASH
2833 + struct bcma_sflash sflash;
2835 +#ifdef CONFIG_BCMA_NFLASH
2836 + struct bcma_nflash nflash;
2839 int nr_serial_ports;
2840 struct bcma_serial_port serial_ports[4];
2841 #endif /* CONFIG_BCMA_DRIVER_MIPS */
2843 + struct platform_device *watchdog;
2845 + /* Lock for GPIO register access. */
2846 + spinlock_t gpio_lock;
2847 +#ifdef CONFIG_BCMA_DRIVER_GPIO
2848 + struct gpio_chip gpio;
2852 /* Register access */
2853 @@ -470,14 +657,16 @@ struct bcma_drv_cc {
2854 bcma_cc_write32(cc, offset, (bcma_cc_read32(cc, offset) & (mask)) | (set))
2856 extern void bcma_core_chipcommon_init(struct bcma_drv_cc *cc);
2857 +extern void bcma_core_chipcommon_early_init(struct bcma_drv_cc *cc);
2859 extern void bcma_chipco_suspend(struct bcma_drv_cc *cc);
2860 extern void bcma_chipco_resume(struct bcma_drv_cc *cc);
2862 void bcma_chipco_bcm4331_ext_pa_lines_ctl(struct bcma_drv_cc *cc, bool enable);
2864 -extern void bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc,
2866 +extern u32 bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc, u32 ticks);
2868 +extern u32 bcma_chipco_get_alp_clock(struct bcma_drv_cc *cc);
2870 void bcma_chipco_irq_mask(struct bcma_drv_cc *cc, u32 mask, u32 value);
2872 @@ -490,9 +679,12 @@ u32 bcma_chipco_gpio_outen(struct bcma_d
2873 u32 bcma_chipco_gpio_control(struct bcma_drv_cc *cc, u32 mask, u32 value);
2874 u32 bcma_chipco_gpio_intmask(struct bcma_drv_cc *cc, u32 mask, u32 value);
2875 u32 bcma_chipco_gpio_polarity(struct bcma_drv_cc *cc, u32 mask, u32 value);
2876 +u32 bcma_chipco_gpio_pullup(struct bcma_drv_cc *cc, u32 mask, u32 value);
2877 +u32 bcma_chipco_gpio_pulldown(struct bcma_drv_cc *cc, u32 mask, u32 value);
2880 extern void bcma_pmu_init(struct bcma_drv_cc *cc);
2881 +extern void bcma_pmu_early_init(struct bcma_drv_cc *cc);
2883 extern void bcma_chipco_pll_write(struct bcma_drv_cc *cc, u32 offset,
2885 @@ -504,4 +696,6 @@ extern void bcma_chipco_regctl_maskset(s
2886 u32 offset, u32 mask, u32 set);
2887 extern void bcma_pmu_spuravoid_pllupdate(struct bcma_drv_cc *cc, int spuravoid);
2889 +extern u32 bcma_pmu_get_bus_clock(struct bcma_drv_cc *cc);
2891 #endif /* LINUX_BCMA_DRIVER_CC_H_ */
2892 --- a/include/linux/bcma/bcma_driver_mips.h
2893 +++ b/include/linux/bcma/bcma_driver_mips.h
2895 #define BCMA_MIPS_MIPS74K_GPIOEN 0x0048
2896 #define BCMA_MIPS_MIPS74K_CLKCTLST 0x01E0
2898 +#define BCMA_MIPS_OOBSELINA74 0x004
2899 #define BCMA_MIPS_OOBSELOUTA30 0x100
2902 @@ -35,17 +36,24 @@ struct bcma_device;
2903 struct bcma_drv_mips {
2904 struct bcma_device *core;
2906 - unsigned int assigned_irqs;
2907 + u8 early_setup_done:1;
2910 #ifdef CONFIG_BCMA_DRIVER_MIPS
2911 extern void bcma_core_mips_init(struct bcma_drv_mips *mcore);
2912 +extern void bcma_core_mips_early_init(struct bcma_drv_mips *mcore);
2914 +extern unsigned int bcma_core_irq(struct bcma_device *core);
2916 static inline void bcma_core_mips_init(struct bcma_drv_mips *mcore) { }
2917 +static inline void bcma_core_mips_early_init(struct bcma_drv_mips *mcore) { }
2919 +static inline unsigned int bcma_core_irq(struct bcma_device *core)
2925 extern u32 bcma_cpu_clock(struct bcma_drv_mips *mcore);
2927 -extern unsigned int bcma_core_mips_irq(struct bcma_device *dev);
2929 #endif /* LINUX_BCMA_DRIVER_MIPS_H_ */
2930 --- a/include/linux/bcma/bcma_driver_pci.h
2931 +++ b/include/linux/bcma/bcma_driver_pci.h
2932 @@ -179,6 +179,8 @@ struct pci_dev;
2933 #define BCMA_CORE_PCI_CFG_FUN_MASK 7 /* Function mask */
2934 #define BCMA_CORE_PCI_CFG_OFF_MASK 0xfff /* Register mask */
2936 +#define BCMA_CORE_PCI_CFG_DEVCTRL 0xd8
2938 /* PCIE Root Capability Register bits (Host mode only) */
2939 #define BCMA_CORE_PCI_RC_CRS_VISIBILITY 0x0001
2941 --- a/include/linux/bcma/bcma_regs.h
2942 +++ b/include/linux/bcma/bcma_regs.h
2944 #define BCMA_CLKCTLST_HAVEHTREQ 0x00000010 /* HT available request */
2945 #define BCMA_CLKCTLST_HWCROFF 0x00000020 /* Force HW clock request off */
2946 #define BCMA_CLKCTLST_EXTRESREQ 0x00000700 /* Mask of external resource requests */
2947 +#define BCMA_CLKCTLST_EXTRESREQ_SHIFT 8
2948 #define BCMA_CLKCTLST_HAVEALP 0x00010000 /* ALP available */
2949 #define BCMA_CLKCTLST_HAVEHT 0x00020000 /* HT available */
2950 #define BCMA_CLKCTLST_BP_ON_ALP 0x00040000 /* RO: running on ALP clock */
2951 #define BCMA_CLKCTLST_BP_ON_HT 0x00080000 /* RO: running on HT clock */
2952 #define BCMA_CLKCTLST_EXTRESST 0x07000000 /* Mask of external resource status */
2953 +#define BCMA_CLKCTLST_EXTRESST_SHIFT 24
2954 /* Is there any BCM4328 on BCMA bus? */
2955 #define BCMA_CLKCTLST_4328A0_HAVEHT 0x00010000 /* 4328a0 has reversed bits */
2956 #define BCMA_CLKCTLST_4328A0_HAVEALP 0x00020000 /* 4328a0 has reversed bits */
2958 #define BCMA_IOST_BIST_DONE 0x8000
2959 #define BCMA_RESET_CTL 0x0800
2960 #define BCMA_RESET_CTL_RESET 0x0001
2961 +#define BCMA_RESET_ST 0x0804
2963 /* BCMA PCI config space registers. */
2964 #define BCMA_PCI_PMCSR 0x44
2966 * (2 ZettaBytes), high 32 bits
2969 +#define BCMA_SOC_FLASH1 0x1fc00000 /* MIPS Flash Region 1 */
2970 +#define BCMA_SOC_FLASH1_SZ 0x00400000 /* MIPS Size of Flash Region 1 */
2971 +#define BCMA_SOC_FLASH2 0x1c000000 /* Flash Region 2 (region 1 shadowed here) */
2972 +#define BCMA_SOC_FLASH2_SZ 0x02000000 /* Size of Flash Region 2 */
2974 #endif /* LINUX_BCMA_REGS_H_ */
2975 --- a/drivers/net/wireless/b43/main.c
2976 +++ b/drivers/net/wireless/b43/main.c
2977 @@ -4622,7 +4622,7 @@ static int b43_wireless_core_init(struct
2978 switch (dev->dev->bus_type) {
2979 #ifdef CONFIG_B43_BCMA
2981 - bcma_core_pci_irq_ctl(&dev->dev->bdev->bus->drv_pci,
2982 + bcma_core_pci_irq_ctl(&dev->dev->bdev->bus->drv_pci[0],
2983 dev->dev->bdev, true);
2986 --- a/drivers/net/wireless/brcm80211/brcmsmac/aiutils.c
2987 +++ b/drivers/net/wireless/brcm80211/brcmsmac/aiutils.c
2988 @@ -695,7 +695,7 @@ void ai_pci_up(struct si_pub *sih)
2989 sii = container_of(sih, struct si_info, pub);
2991 if (sii->icbus->hosttype == BCMA_HOSTTYPE_PCI)
2992 - bcma_core_pci_extend_L1timer(&sii->icbus->drv_pci, true);
2993 + bcma_core_pci_extend_L1timer(&sii->icbus->drv_pci[0], true);
2996 /* Unconfigure and/or apply various WARs when going down */
2997 @@ -706,7 +706,7 @@ void ai_pci_down(struct si_pub *sih)
2998 sii = container_of(sih, struct si_info, pub);
3000 if (sii->icbus->hosttype == BCMA_HOSTTYPE_PCI)
3001 - bcma_core_pci_extend_L1timer(&sii->icbus->drv_pci, false);
3002 + bcma_core_pci_extend_L1timer(&sii->icbus->drv_pci[0], false);
3005 /* Enable BT-COEX & Ex-PA for 4313 */
3006 --- a/drivers/net/wireless/brcm80211/brcmsmac/main.c
3007 +++ b/drivers/net/wireless/brcm80211/brcmsmac/main.c
3008 @@ -5077,7 +5077,7 @@ static int brcms_b_up_prep(struct brcms_
3009 * Configure pci/pcmcia here instead of in brcms_c_attach()
3010 * to allow mfg hotswap: down, hotswap (chip power cycle), up.
3012 - bcma_core_pci_irq_ctl(&wlc_hw->d11core->bus->drv_pci, wlc_hw->d11core,
3013 + bcma_core_pci_irq_ctl(&wlc_hw->d11core->bus->drv_pci[0], wlc_hw->d11core,