1 --- a/drivers/bcma/bcma_private.h
2 +++ b/drivers/bcma/bcma_private.h
7 -int bcma_bus_register(struct bcma_bus *bus);
8 +int __devinit bcma_bus_register(struct bcma_bus *bus);
9 void bcma_bus_unregister(struct bcma_bus *bus);
10 int __init bcma_bus_early_register(struct bcma_bus *bus,
11 struct bcma_device *core_cc,
12 struct bcma_device *core_mips);
14 +int bcma_bus_suspend(struct bcma_bus *bus);
15 int bcma_bus_resume(struct bcma_bus *bus);
18 @@ -47,8 +48,12 @@ extern int __init bcma_host_pci_init(voi
19 extern void __exit bcma_host_pci_exit(void);
20 #endif /* CONFIG_BCMA_HOST_PCI */
23 +u32 bcma_pcie_read(struct bcma_drv_pci *pc, u32 address);
25 #ifdef CONFIG_BCMA_DRIVER_PCI_HOSTMODE
26 -void bcma_core_pci_hostmode_init(struct bcma_drv_pci *pc);
27 +bool __devinit bcma_core_pci_is_in_hostmode(struct bcma_drv_pci *pc);
28 +void __devinit bcma_core_pci_hostmode_init(struct bcma_drv_pci *pc);
29 #endif /* CONFIG_BCMA_DRIVER_PCI_HOSTMODE */
32 --- a/drivers/bcma/host_pci.c
33 +++ b/drivers/bcma/host_pci.c
34 @@ -21,48 +21,58 @@ static void bcma_host_pci_switch_core(st
35 pr_debug("Switched to core: 0x%X\n", core->id.id);
38 -static u8 bcma_host_pci_read8(struct bcma_device *core, u16 offset)
40 +/* Provides access to the requested core. Returns base offset that has to be
41 + * used. It makes use of fixed windows when possible. */
42 +static u16 bcma_host_pci_provide_access_to_core(struct bcma_device *core)
44 + switch (core->id.id) {
45 + case BCMA_CORE_CHIPCOMMON:
46 + return 3 * BCMA_CORE_SIZE;
47 + case BCMA_CORE_PCIE:
48 + return 2 * BCMA_CORE_SIZE;
51 if (core->bus->mapped_core != core)
52 bcma_host_pci_switch_core(core);
56 +static u8 bcma_host_pci_read8(struct bcma_device *core, u16 offset)
58 + offset += bcma_host_pci_provide_access_to_core(core);
59 return ioread8(core->bus->mmio + offset);
62 static u16 bcma_host_pci_read16(struct bcma_device *core, u16 offset)
64 - if (core->bus->mapped_core != core)
65 - bcma_host_pci_switch_core(core);
66 + offset += bcma_host_pci_provide_access_to_core(core);
67 return ioread16(core->bus->mmio + offset);
70 static u32 bcma_host_pci_read32(struct bcma_device *core, u16 offset)
72 - if (core->bus->mapped_core != core)
73 - bcma_host_pci_switch_core(core);
74 + offset += bcma_host_pci_provide_access_to_core(core);
75 return ioread32(core->bus->mmio + offset);
78 static void bcma_host_pci_write8(struct bcma_device *core, u16 offset,
81 - if (core->bus->mapped_core != core)
82 - bcma_host_pci_switch_core(core);
83 + offset += bcma_host_pci_provide_access_to_core(core);
84 iowrite8(value, core->bus->mmio + offset);
87 static void bcma_host_pci_write16(struct bcma_device *core, u16 offset,
90 - if (core->bus->mapped_core != core)
91 - bcma_host_pci_switch_core(core);
92 + offset += bcma_host_pci_provide_access_to_core(core);
93 iowrite16(value, core->bus->mmio + offset);
96 static void bcma_host_pci_write32(struct bcma_device *core, u16 offset,
99 - if (core->bus->mapped_core != core)
100 - bcma_host_pci_switch_core(core);
101 + offset += bcma_host_pci_provide_access_to_core(core);
102 iowrite32(value, core->bus->mmio + offset);
105 @@ -144,8 +154,8 @@ const struct bcma_host_ops bcma_host_pci
106 .awrite32 = bcma_host_pci_awrite32,
109 -static int bcma_host_pci_probe(struct pci_dev *dev,
110 - const struct pci_device_id *id)
111 +static int __devinit bcma_host_pci_probe(struct pci_dev *dev,
112 + const struct pci_device_id *id)
114 struct bcma_bus *bus;
116 @@ -225,41 +235,32 @@ static void bcma_host_pci_remove(struct
120 -static int bcma_host_pci_suspend(struct pci_dev *dev, pm_message_t state)
121 +static int bcma_host_pci_suspend(struct device *dev)
123 - struct bcma_bus *bus = pci_get_drvdata(dev);
125 - /* Host specific */
126 - pci_save_state(dev);
127 - pci_disable_device(dev);
128 - pci_set_power_state(dev, pci_choose_state(dev, state));
129 + struct pci_dev *pdev = to_pci_dev(dev);
130 + struct bcma_bus *bus = pci_get_drvdata(pdev);
132 bus->mapped_core = NULL;
135 + return bcma_bus_suspend(bus);
138 -static int bcma_host_pci_resume(struct pci_dev *dev)
139 +static int bcma_host_pci_resume(struct device *dev)
141 - struct bcma_bus *bus = pci_get_drvdata(dev);
143 + struct pci_dev *pdev = to_pci_dev(dev);
144 + struct bcma_bus *bus = pci_get_drvdata(pdev);
146 - /* Host specific */
147 - pci_set_power_state(dev, 0);
148 - err = pci_enable_device(dev);
151 - pci_restore_state(dev);
152 + return bcma_bus_resume(bus);
156 - err = bcma_bus_resume(bus);
159 +static SIMPLE_DEV_PM_OPS(bcma_pm_ops, bcma_host_pci_suspend,
160 + bcma_host_pci_resume);
161 +#define BCMA_PM_OPS (&bcma_pm_ops)
165 #else /* CONFIG_PM */
166 -# define bcma_host_pci_suspend NULL
167 -# define bcma_host_pci_resume NULL
169 +#define BCMA_PM_OPS NULL
171 #endif /* CONFIG_PM */
173 static DEFINE_PCI_DEVICE_TABLE(bcma_pci_bridge_tbl) = {
174 @@ -277,8 +278,7 @@ static struct pci_driver bcma_pci_bridge
175 .id_table = bcma_pci_bridge_tbl,
176 .probe = bcma_host_pci_probe,
177 .remove = bcma_host_pci_remove,
178 - .suspend = bcma_host_pci_suspend,
179 - .resume = bcma_host_pci_resume,
180 + .driver.pm = BCMA_PM_OPS,
183 int __init bcma_host_pci_init(void)
184 --- a/drivers/bcma/main.c
185 +++ b/drivers/bcma/main.c
187 MODULE_DESCRIPTION("Broadcom's specific AMBA driver");
188 MODULE_LICENSE("GPL");
190 +/* contains the number the next bus should get. */
191 +static unsigned int bcma_bus_next_num = 0;
193 +/* bcma_buses_mutex locks the bcma_bus_next_num */
194 +static DEFINE_MUTEX(bcma_buses_mutex);
196 static int bcma_bus_match(struct device *dev, struct device_driver *drv);
197 static int bcma_device_probe(struct device *dev);
198 static int bcma_device_remove(struct device *dev);
199 @@ -55,7 +61,7 @@ static struct bus_type bcma_bus_type = {
200 .dev_attrs = bcma_device_attrs,
203 -static struct bcma_device *bcma_find_core(struct bcma_bus *bus, u16 coreid)
204 +struct bcma_device *bcma_find_core(struct bcma_bus *bus, u16 coreid)
206 struct bcma_device *core;
208 @@ -65,6 +71,7 @@ static struct bcma_device *bcma_find_cor
212 +EXPORT_SYMBOL_GPL(bcma_find_core);
214 static void bcma_release_core_dev(struct device *dev)
216 @@ -93,7 +100,7 @@ static int bcma_register_cores(struct bc
218 core->dev.release = bcma_release_core_dev;
219 core->dev.bus = &bcma_bus_type;
220 - dev_set_name(&core->dev, "bcma%d:%d", 0/*bus->num*/, dev_id);
221 + dev_set_name(&core->dev, "bcma%d:%d", bus->num, dev_id);
223 switch (bus->hosttype) {
224 case BCMA_HOSTTYPE_PCI:
225 @@ -132,11 +139,15 @@ static void bcma_unregister_cores(struct
229 -int bcma_bus_register(struct bcma_bus *bus)
230 +int __devinit bcma_bus_register(struct bcma_bus *bus)
233 struct bcma_device *core;
235 + mutex_lock(&bcma_buses_mutex);
236 + bus->num = bcma_bus_next_num++;
237 + mutex_unlock(&bcma_buses_mutex);
239 /* Scan for devices (cores) */
240 err = bcma_bus_scan(bus);
242 @@ -169,10 +180,8 @@ int bcma_bus_register(struct bcma_bus *b
243 err = bcma_sprom_get(bus);
244 if (err == -ENOENT) {
245 pr_err("No SPROM available\n");
248 pr_err("Failed to get SPROM: %d\n", err);
252 /* Register found cores */
253 bcma_register_cores(bus);
254 @@ -241,6 +250,21 @@ int __init bcma_bus_early_register(struc
258 +int bcma_bus_suspend(struct bcma_bus *bus)
260 + struct bcma_device *core;
262 + list_for_each_entry(core, &bus->cores, list) {
263 + struct device_driver *drv = core->dev.driver;
265 + struct bcma_driver *adrv = container_of(drv, struct bcma_driver, drv);
267 + adrv->suspend(core);
273 int bcma_bus_resume(struct bcma_bus *bus)
275 struct bcma_device *core;
276 @@ -252,6 +276,15 @@ int bcma_bus_resume(struct bcma_bus *bus
277 bcma_core_chipcommon_init(&bus->drv_cc);
280 + list_for_each_entry(core, &bus->cores, list) {
281 + struct device_driver *drv = core->dev.driver;
283 + struct bcma_driver *adrv = container_of(drv, struct bcma_driver, drv);
285 + adrv->resume(core);
292 --- a/drivers/bcma/Kconfig
293 +++ b/drivers/bcma/Kconfig
294 @@ -29,7 +29,7 @@ config BCMA_HOST_PCI
296 config BCMA_DRIVER_PCI_HOSTMODE
297 bool "Driver for PCI core working in hostmode"
298 - depends on BCMA && MIPS
299 + depends on BCMA && MIPS && BCMA_HOST_PCI
301 PCI core hostmode operation (external PCI bus).
303 --- a/drivers/bcma/driver_chipcommon_pmu.c
304 +++ b/drivers/bcma/driver_chipcommon_pmu.c
305 @@ -80,6 +80,7 @@ static void bcma_pmu_resources_init(stru
313 --- a/drivers/bcma/driver_pci.c
314 +++ b/drivers/bcma/driver_pci.c
316 * Broadcom specific AMBA
319 - * Copyright 2005, Broadcom Corporation
320 + * Copyright 2005, 2011, Broadcom Corporation
321 * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
322 + * Copyright 2011, 2012, Hauke Mehrtens <hauke@hauke-m.de>
324 * Licensed under the GNU/GPL. See COPYING for details.
328 **************************************************/
330 -static u32 bcma_pcie_read(struct bcma_drv_pci *pc, u32 address)
331 +u32 bcma_pcie_read(struct bcma_drv_pci *pc, u32 address)
333 - pcicore_write32(pc, 0x130, address);
334 - pcicore_read32(pc, 0x130);
335 - return pcicore_read32(pc, 0x134);
336 + pcicore_write32(pc, BCMA_CORE_PCI_PCIEIND_ADDR, address);
337 + pcicore_read32(pc, BCMA_CORE_PCI_PCIEIND_ADDR);
338 + return pcicore_read32(pc, BCMA_CORE_PCI_PCIEIND_DATA);
342 static void bcma_pcie_write(struct bcma_drv_pci *pc, u32 address, u32 data)
344 - pcicore_write32(pc, 0x130, address);
345 - pcicore_read32(pc, 0x130);
346 - pcicore_write32(pc, 0x134, data);
347 + pcicore_write32(pc, BCMA_CORE_PCI_PCIEIND_ADDR, address);
348 + pcicore_read32(pc, BCMA_CORE_PCI_PCIEIND_ADDR);
349 + pcicore_write32(pc, BCMA_CORE_PCI_PCIEIND_DATA, data);
353 static void bcma_pcie_mdio_set_phy(struct bcma_drv_pci *pc, u8 phy)
355 - const u16 mdio_control = 0x128;
356 - const u16 mdio_data = 0x12C;
360 - v = (1 << 30); /* Start of Transaction */
361 - v |= (1 << 28); /* Write Transaction */
362 - v |= (1 << 17); /* Turnaround */
364 + v = BCMA_CORE_PCI_MDIODATA_START;
365 + v |= BCMA_CORE_PCI_MDIODATA_WRITE;
366 + v |= (BCMA_CORE_PCI_MDIODATA_DEV_ADDR <<
367 + BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF);
368 + v |= (BCMA_CORE_PCI_MDIODATA_BLK_ADDR <<
369 + BCMA_CORE_PCI_MDIODATA_REGADDR_SHF);
370 + v |= BCMA_CORE_PCI_MDIODATA_TA;
372 - pcicore_write32(pc, mdio_data, v);
373 + pcicore_write32(pc, BCMA_CORE_PCI_MDIO_DATA, v);
376 for (i = 0; i < 200; i++) {
377 - v = pcicore_read32(pc, mdio_control);
378 - if (v & 0x100 /* Trans complete */)
379 + v = pcicore_read32(pc, BCMA_CORE_PCI_MDIO_CONTROL);
380 + if (v & BCMA_CORE_PCI_MDIOCTL_ACCESS_DONE)
384 @@ -57,79 +59,84 @@ static void bcma_pcie_mdio_set_phy(struc
386 static u16 bcma_pcie_mdio_read(struct bcma_drv_pci *pc, u8 device, u8 address)
388 - const u16 mdio_control = 0x128;
389 - const u16 mdio_data = 0x12C;
390 int max_retries = 10;
395 - v = 0x80; /* Enable Preamble Sequence */
396 - v |= 0x2; /* MDIO Clock Divisor */
397 - pcicore_write32(pc, mdio_control, v);
398 + /* enable mdio access to SERDES */
399 + v = BCMA_CORE_PCI_MDIOCTL_PREAM_EN;
400 + v |= BCMA_CORE_PCI_MDIOCTL_DIVISOR_VAL;
401 + pcicore_write32(pc, BCMA_CORE_PCI_MDIO_CONTROL, v);
403 if (pc->core->id.rev >= 10) {
405 bcma_pcie_mdio_set_phy(pc, device);
406 + v = (BCMA_CORE_PCI_MDIODATA_DEV_ADDR <<
407 + BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF);
408 + v |= (address << BCMA_CORE_PCI_MDIODATA_REGADDR_SHF);
410 + v = (device << BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF_OLD);
411 + v |= (address << BCMA_CORE_PCI_MDIODATA_REGADDR_SHF_OLD);
414 - v = (1 << 30); /* Start of Transaction */
415 - v |= (1 << 29); /* Read Transaction */
416 - v |= (1 << 17); /* Turnaround */
417 - if (pc->core->id.rev < 10)
418 - v |= (u32)device << 22;
419 - v |= (u32)address << 18;
420 - pcicore_write32(pc, mdio_data, v);
421 + v = BCMA_CORE_PCI_MDIODATA_START;
422 + v |= BCMA_CORE_PCI_MDIODATA_READ;
423 + v |= BCMA_CORE_PCI_MDIODATA_TA;
425 + pcicore_write32(pc, BCMA_CORE_PCI_MDIO_DATA, v);
426 /* Wait for the device to complete the transaction */
428 for (i = 0; i < max_retries; i++) {
429 - v = pcicore_read32(pc, mdio_control);
430 - if (v & 0x100 /* Trans complete */) {
431 + v = pcicore_read32(pc, BCMA_CORE_PCI_MDIO_CONTROL);
432 + if (v & BCMA_CORE_PCI_MDIOCTL_ACCESS_DONE) {
434 - ret = pcicore_read32(pc, mdio_data);
435 + ret = pcicore_read32(pc, BCMA_CORE_PCI_MDIO_DATA);
440 - pcicore_write32(pc, mdio_control, 0);
441 + pcicore_write32(pc, BCMA_CORE_PCI_MDIO_CONTROL, 0);
445 static void bcma_pcie_mdio_write(struct bcma_drv_pci *pc, u8 device,
446 u8 address, u16 data)
448 - const u16 mdio_control = 0x128;
449 - const u16 mdio_data = 0x12C;
450 int max_retries = 10;
454 - v = 0x80; /* Enable Preamble Sequence */
455 - v |= 0x2; /* MDIO Clock Divisor */
456 - pcicore_write32(pc, mdio_control, v);
457 + /* enable mdio access to SERDES */
458 + v = BCMA_CORE_PCI_MDIOCTL_PREAM_EN;
459 + v |= BCMA_CORE_PCI_MDIOCTL_DIVISOR_VAL;
460 + pcicore_write32(pc, BCMA_CORE_PCI_MDIO_CONTROL, v);
462 if (pc->core->id.rev >= 10) {
464 bcma_pcie_mdio_set_phy(pc, device);
465 + v = (BCMA_CORE_PCI_MDIODATA_DEV_ADDR <<
466 + BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF);
467 + v |= (address << BCMA_CORE_PCI_MDIODATA_REGADDR_SHF);
469 + v = (device << BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF_OLD);
470 + v |= (address << BCMA_CORE_PCI_MDIODATA_REGADDR_SHF_OLD);
473 - v = (1 << 30); /* Start of Transaction */
474 - v |= (1 << 28); /* Write Transaction */
475 - v |= (1 << 17); /* Turnaround */
476 - if (pc->core->id.rev < 10)
477 - v |= (u32)device << 22;
478 - v |= (u32)address << 18;
479 + v = BCMA_CORE_PCI_MDIODATA_START;
480 + v |= BCMA_CORE_PCI_MDIODATA_WRITE;
481 + v |= BCMA_CORE_PCI_MDIODATA_TA;
483 - pcicore_write32(pc, mdio_data, v);
484 + pcicore_write32(pc, BCMA_CORE_PCI_MDIO_DATA, v);
485 /* Wait for the device to complete the transaction */
487 for (i = 0; i < max_retries; i++) {
488 - v = pcicore_read32(pc, mdio_control);
489 - if (v & 0x100 /* Trans complete */)
490 + v = pcicore_read32(pc, BCMA_CORE_PCI_MDIO_CONTROL);
491 + if (v & BCMA_CORE_PCI_MDIOCTL_ACCESS_DONE)
495 - pcicore_write32(pc, mdio_control, 0);
496 + pcicore_write32(pc, BCMA_CORE_PCI_MDIO_CONTROL, 0);
499 /**************************************************
500 @@ -138,72 +145,53 @@ static void bcma_pcie_mdio_write(struct
502 static u8 bcma_pcicore_polarity_workaround(struct bcma_drv_pci *pc)
504 - return (bcma_pcie_read(pc, 0x204) & 0x10) ? 0xC0 : 0x80;
507 + tmp = bcma_pcie_read(pc, BCMA_CORE_PCI_PLP_STATUSREG);
508 + if (tmp & BCMA_CORE_PCI_PLP_POLARITYINV_STAT)
509 + return BCMA_CORE_PCI_SERDES_RX_CTRL_FORCE |
510 + BCMA_CORE_PCI_SERDES_RX_CTRL_POLARITY;
512 + return BCMA_CORE_PCI_SERDES_RX_CTRL_FORCE;
515 static void bcma_pcicore_serdes_workaround(struct bcma_drv_pci *pc)
517 - const u8 serdes_pll_device = 0x1D;
518 - const u8 serdes_rx_device = 0x1F;
521 - bcma_pcie_mdio_write(pc, serdes_rx_device, 1 /* Control */,
522 - bcma_pcicore_polarity_workaround(pc));
523 - tmp = bcma_pcie_mdio_read(pc, serdes_pll_device, 1 /* Control */);
525 - bcma_pcie_mdio_write(pc, serdes_pll_device, 1, tmp & ~0x4000);
526 + bcma_pcie_mdio_write(pc, BCMA_CORE_PCI_MDIODATA_DEV_RX,
527 + BCMA_CORE_PCI_SERDES_RX_CTRL,
528 + bcma_pcicore_polarity_workaround(pc));
529 + tmp = bcma_pcie_mdio_read(pc, BCMA_CORE_PCI_MDIODATA_DEV_PLL,
530 + BCMA_CORE_PCI_SERDES_PLL_CTRL);
531 + if (tmp & BCMA_CORE_PCI_PLL_CTRL_FREQDET_EN)
532 + bcma_pcie_mdio_write(pc, BCMA_CORE_PCI_MDIODATA_DEV_PLL,
533 + BCMA_CORE_PCI_SERDES_PLL_CTRL,
534 + tmp & ~BCMA_CORE_PCI_PLL_CTRL_FREQDET_EN);
537 /**************************************************
539 **************************************************/
541 -static void bcma_core_pci_clientmode_init(struct bcma_drv_pci *pc)
542 +static void __devinit bcma_core_pci_clientmode_init(struct bcma_drv_pci *pc)
544 bcma_pcicore_serdes_workaround(pc);
547 -static bool bcma_core_pci_is_in_hostmode(struct bcma_drv_pci *pc)
549 - struct bcma_bus *bus = pc->core->bus;
552 - chipid_top = (bus->chipinfo.id & 0xFF00);
553 - if (chipid_top != 0x4700 &&
554 - chipid_top != 0x5300)
557 -#ifdef CONFIG_SSB_DRIVER_PCICORE
558 - if (bus->sprom.boardflags_lo & SSB_BFL_NOPCI)
560 -#endif /* CONFIG_SSB_DRIVER_PCICORE */
563 - /* TODO: on BCMA we use address from EROM instead of magic formula */
565 - return !mips_busprobe32(tmp, (bus->mmio +
566 - (pc->core->core_index * BCMA_CORE_SIZE)));
572 -void bcma_core_pci_init(struct bcma_drv_pci *pc)
573 +void __devinit bcma_core_pci_init(struct bcma_drv_pci *pc)
578 - if (bcma_core_pci_is_in_hostmode(pc)) {
579 #ifdef CONFIG_BCMA_DRIVER_PCI_HOSTMODE
580 + pc->hostmode = bcma_core_pci_is_in_hostmode(pc);
582 bcma_core_pci_hostmode_init(pc);
584 - pr_err("Driver compiled without support for hostmode PCI\n");
585 #endif /* CONFIG_BCMA_DRIVER_PCI_HOSTMODE */
587 - bcma_core_pci_clientmode_init(pc);
590 - pc->setup_done = true;
592 + bcma_core_pci_clientmode_init(pc);
595 int bcma_core_pci_irq_ctl(struct bcma_drv_pci *pc, struct bcma_device *core,
596 --- a/drivers/bcma/driver_pci_host.c
597 +++ b/drivers/bcma/driver_pci_host.c
599 * Broadcom specific AMBA
600 * PCI Core in hostmode
602 + * Copyright 2005 - 2011, Broadcom Corporation
603 + * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
604 + * Copyright 2011, 2012, Hauke Mehrtens <hauke@hauke-m.de>
606 * Licensed under the GNU/GPL. See COPYING for details.
609 #include "bcma_private.h"
610 +#include <linux/pci.h>
611 +#include <linux/export.h>
612 #include <linux/bcma/bcma.h>
613 +#include <asm/paccess.h>
615 +/* Probe a 32bit value on the bus and catch bus exceptions.
616 + * Returns nonzero on a bus exception.
617 + * This is MIPS specific */
618 +#define mips_busprobe32(val, addr) get_dbe((val), ((u32 *)(addr)))
620 +/* Assume one-hot slot wiring */
621 +#define BCMA_PCI_SLOT_MAX 16
622 +#define PCI_CONFIG_SPACE_SIZE 256
624 +bool __devinit bcma_core_pci_is_in_hostmode(struct bcma_drv_pci *pc)
626 + struct bcma_bus *bus = pc->core->bus;
630 + chipid_top = (bus->chipinfo.id & 0xFF00);
631 + if (chipid_top != 0x4700 &&
632 + chipid_top != 0x5300)
635 + if (bus->sprom.boardflags_lo & BCMA_CORE_PCI_BFL_NOPCI) {
636 + pr_info("This PCI core is disabled and not working\n");
640 + bcma_core_enable(pc->core, 0);
642 + return !mips_busprobe32(tmp, pc->core->io_addr);
645 +static u32 bcma_pcie_read_config(struct bcma_drv_pci *pc, u32 address)
647 + pcicore_write32(pc, BCMA_CORE_PCI_CONFIG_ADDR, address);
648 + pcicore_read32(pc, BCMA_CORE_PCI_CONFIG_ADDR);
649 + return pcicore_read32(pc, BCMA_CORE_PCI_CONFIG_DATA);
652 +static void bcma_pcie_write_config(struct bcma_drv_pci *pc, u32 address,
655 + pcicore_write32(pc, BCMA_CORE_PCI_CONFIG_ADDR, address);
656 + pcicore_read32(pc, BCMA_CORE_PCI_CONFIG_ADDR);
657 + pcicore_write32(pc, BCMA_CORE_PCI_CONFIG_DATA, data);
660 +static u32 bcma_get_cfgspace_addr(struct bcma_drv_pci *pc, unsigned int dev,
661 + unsigned int func, unsigned int off)
665 + /* Issue config commands only when the data link is up (atleast
666 + * one external pcie device is present).
668 + if (dev >= 2 || !(bcma_pcie_read(pc, BCMA_CORE_PCI_DLLP_LSREG)
669 + & BCMA_CORE_PCI_DLLP_LSREG_LINKUP))
672 + /* Type 0 transaction */
673 + /* Slide the PCI window to the appropriate slot */
674 + pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI1, BCMA_CORE_PCI_SBTOPCI_CFG0);
675 + /* Calculate the address */
676 + addr = pc->host_controller->host_cfg_addr;
677 + addr |= (dev << BCMA_CORE_PCI_CFG_SLOT_SHIFT);
678 + addr |= (func << BCMA_CORE_PCI_CFG_FUN_SHIFT);
679 + addr |= (off & ~3);
685 -void bcma_core_pci_hostmode_init(struct bcma_drv_pci *pc)
686 +static int bcma_extpci_read_config(struct bcma_drv_pci *pc, unsigned int dev,
687 + unsigned int func, unsigned int off,
688 + void *buf, int len)
690 - pr_err("No support for PCI core in hostmode yet\n");
693 + void __iomem *mmio = 0;
695 + WARN_ON(!pc->hostmode);
696 + if (unlikely(len != 1 && len != 2 && len != 4))
699 + /* we support only two functions on device 0 */
703 + /* accesses to config registers with offsets >= 256
704 + * requires indirect access.
706 + if (off >= PCI_CONFIG_SPACE_SIZE) {
707 + addr = (func << 12);
708 + addr |= (off & 0x0FFF);
709 + val = bcma_pcie_read_config(pc, addr);
711 + addr = BCMA_CORE_PCI_PCICFG0;
712 + addr |= (func << 8);
713 + addr |= (off & 0xfc);
714 + val = pcicore_read32(pc, addr);
717 + addr = bcma_get_cfgspace_addr(pc, dev, func, off);
718 + if (unlikely(!addr))
721 + mmio = ioremap_nocache(addr, len);
725 + if (mips_busprobe32(val, mmio)) {
732 + val >>= (8 * (off & 3));
736 + *((u8 *)buf) = (u8)val;
739 + *((u16 *)buf) = (u16)val;
742 + *((u32 *)buf) = (u32)val;
753 +static int bcma_extpci_write_config(struct bcma_drv_pci *pc, unsigned int dev,
754 + unsigned int func, unsigned int off,
755 + const void *buf, int len)
758 + u32 addr = 0, val = 0;
759 + void __iomem *mmio = 0;
760 + u16 chipid = pc->core->bus->chipinfo.id;
762 + WARN_ON(!pc->hostmode);
763 + if (unlikely(len != 1 && len != 2 && len != 4))
766 + /* accesses to config registers with offsets >= 256
767 + * requires indirect access.
769 + if (off < PCI_CONFIG_SPACE_SIZE) {
770 + addr = pc->core->addr + BCMA_CORE_PCI_PCICFG0;
771 + addr |= (func << 8);
772 + addr |= (off & 0xfc);
773 + mmio = ioremap_nocache(addr, len);
778 + addr = bcma_get_cfgspace_addr(pc, dev, func, off);
779 + if (unlikely(!addr))
782 + mmio = ioremap_nocache(addr, len);
786 + if (mips_busprobe32(val, mmio)) {
795 + val &= ~(0xFF << (8 * (off & 3)));
796 + val |= *((const u8 *)buf) << (8 * (off & 3));
800 + val &= ~(0xFFFF << (8 * (off & 3)));
801 + val |= *((const u16 *)buf) << (8 * (off & 3));
804 + val = *((const u32 *)buf);
807 + if (dev == 0 && !addr) {
808 + /* accesses to config registers with offsets >= 256
809 + * requires indirect access.
811 + addr = (func << 12);
812 + addr |= (off & 0x0FFF);
813 + bcma_pcie_write_config(pc, addr, val);
817 + if (chipid == 0x4716 || chipid == 0x4748)
829 +static int bcma_core_pci_hostmode_read_config(struct pci_bus *bus,
830 + unsigned int devfn,
831 + int reg, int size, u32 *val)
833 + unsigned long flags;
835 + struct bcma_drv_pci *pc;
836 + struct bcma_drv_pci_host *pc_host;
838 + pc_host = container_of(bus->ops, struct bcma_drv_pci_host, pci_ops);
839 + pc = pc_host->pdev;
841 + spin_lock_irqsave(&pc_host->cfgspace_lock, flags);
842 + err = bcma_extpci_read_config(pc, PCI_SLOT(devfn),
843 + PCI_FUNC(devfn), reg, val, size);
844 + spin_unlock_irqrestore(&pc_host->cfgspace_lock, flags);
846 + return err ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
849 +static int bcma_core_pci_hostmode_write_config(struct pci_bus *bus,
850 + unsigned int devfn,
851 + int reg, int size, u32 val)
853 + unsigned long flags;
855 + struct bcma_drv_pci *pc;
856 + struct bcma_drv_pci_host *pc_host;
858 + pc_host = container_of(bus->ops, struct bcma_drv_pci_host, pci_ops);
859 + pc = pc_host->pdev;
861 + spin_lock_irqsave(&pc_host->cfgspace_lock, flags);
862 + err = bcma_extpci_write_config(pc, PCI_SLOT(devfn),
863 + PCI_FUNC(devfn), reg, &val, size);
864 + spin_unlock_irqrestore(&pc_host->cfgspace_lock, flags);
866 + return err ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
869 +/* return cap_offset if requested capability exists in the PCI config space */
870 +static u8 __devinit bcma_find_pci_capability(struct bcma_drv_pci *pc,
872 + unsigned int func, u8 req_cap_id,
873 + unsigned char *buf, u32 *buflen)
880 + /* check for Header type 0 */
881 + bcma_extpci_read_config(pc, dev, func, PCI_HEADER_TYPE, &byte_val,
883 + if ((byte_val & 0x7f) != PCI_HEADER_TYPE_NORMAL)
886 + /* check if the capability pointer field exists */
887 + bcma_extpci_read_config(pc, dev, func, PCI_STATUS, &byte_val,
889 + if (!(byte_val & PCI_STATUS_CAP_LIST))
892 + /* check if the capability pointer is 0x00 */
893 + bcma_extpci_read_config(pc, dev, func, PCI_CAPABILITY_LIST, &cap_ptr,
895 + if (cap_ptr == 0x00)
898 + /* loop thr'u the capability list and see if the requested capabilty
900 + bcma_extpci_read_config(pc, dev, func, cap_ptr, &cap_id, sizeof(u8));
901 + while (cap_id != req_cap_id) {
902 + bcma_extpci_read_config(pc, dev, func, cap_ptr + 1, &cap_ptr,
904 + if (cap_ptr == 0x00)
906 + bcma_extpci_read_config(pc, dev, func, cap_ptr, &cap_id,
910 + /* found the caller requested capability */
911 + if ((buf != NULL) && (buflen != NULL)) {
920 + /* copy the cpability data excluding cap ID and next ptr */
921 + cap_data = cap_ptr + 2;
922 + if ((bufsize + cap_data) > PCI_CONFIG_SPACE_SIZE)
923 + bufsize = PCI_CONFIG_SPACE_SIZE - cap_data;
925 + while (bufsize--) {
926 + bcma_extpci_read_config(pc, dev, func, cap_data, buf,
936 +/* If the root port is capable of returning Config Request
937 + * Retry Status (CRS) Completion Status to software then
938 + * enable the feature.
940 +static void __devinit bcma_core_pci_enable_crs(struct bcma_drv_pci *pc)
942 + u8 cap_ptr, root_ctrl, root_cap, dev;
946 + cap_ptr = bcma_find_pci_capability(pc, 0, 0, PCI_CAP_ID_EXP, NULL,
948 + root_cap = cap_ptr + PCI_EXP_RTCAP;
949 + bcma_extpci_read_config(pc, 0, 0, root_cap, &val16, sizeof(u16));
950 + if (val16 & BCMA_CORE_PCI_RC_CRS_VISIBILITY) {
951 + /* Enable CRS software visibility */
952 + root_ctrl = cap_ptr + PCI_EXP_RTCTL;
953 + val16 = PCI_EXP_RTCTL_CRSSVE;
954 + bcma_extpci_read_config(pc, 0, 0, root_ctrl, &val16,
957 + /* Initiate a configuration request to read the vendor id
958 + * field of the device function's config space header after
959 + * 100 ms wait time from the end of Reset. If the device is
960 + * not done with its internal initialization, it must at
961 + * least return a completion TLP, with a completion status
962 + * of "Configuration Request Retry Status (CRS)". The root
963 + * complex must complete the request to the host by returning
964 + * a read-data value of 0001h for the Vendor ID field and
965 + * all 1s for any additional bytes included in the request.
966 + * Poll using the config reads for max wait time of 1 sec or
967 + * until we receive the successful completion status. Repeat
968 + * the procedure for all the devices.
970 + for (dev = 1; dev < BCMA_PCI_SLOT_MAX; dev++) {
971 + for (i = 0; i < 100000; i++) {
972 + bcma_extpci_read_config(pc, dev, 0,
973 + PCI_VENDOR_ID, &val16,
980 + pr_err("PCI: Broken device in slot %d\n", dev);
985 +void __devinit bcma_core_pci_hostmode_init(struct bcma_drv_pci *pc)
987 + struct bcma_bus *bus = pc->core->bus;
988 + struct bcma_drv_pci_host *pc_host;
990 + u32 pci_membase_1G;
991 + unsigned long io_map_base;
993 + pr_info("PCIEcore in host mode found\n");
995 + pc_host = kzalloc(sizeof(*pc_host), GFP_KERNEL);
997 + pr_err("can not allocate memory");
1001 + pc->host_controller = pc_host;
1002 + pc_host->pci_controller.io_resource = &pc_host->io_resource;
1003 + pc_host->pci_controller.mem_resource = &pc_host->mem_resource;
1004 + pc_host->pci_controller.pci_ops = &pc_host->pci_ops;
1005 + pc_host->pdev = pc;
1007 + pci_membase_1G = BCMA_SOC_PCI_DMA;
1008 + pc_host->host_cfg_addr = BCMA_SOC_PCI_CFG;
1010 + pc_host->pci_ops.read = bcma_core_pci_hostmode_read_config;
1011 + pc_host->pci_ops.write = bcma_core_pci_hostmode_write_config;
1013 + pc_host->mem_resource.name = "BCMA PCIcore external memory",
1014 + pc_host->mem_resource.start = BCMA_SOC_PCI_DMA;
1015 + pc_host->mem_resource.end = BCMA_SOC_PCI_DMA + BCMA_SOC_PCI_DMA_SZ - 1;
1016 + pc_host->mem_resource.flags = IORESOURCE_MEM | IORESOURCE_PCI_FIXED;
1018 + pc_host->io_resource.name = "BCMA PCIcore external I/O",
1019 + pc_host->io_resource.start = 0x100;
1020 + pc_host->io_resource.end = 0x7FF;
1021 + pc_host->io_resource.flags = IORESOURCE_IO | IORESOURCE_PCI_FIXED;
1025 + pcicore_write32(pc, BCMA_CORE_PCI_CTL, BCMA_CORE_PCI_CTL_RST_OE);
1027 + pcicore_write32(pc, BCMA_CORE_PCI_CTL, BCMA_CORE_PCI_CTL_RST |
1028 + BCMA_CORE_PCI_CTL_RST_OE);
1030 + /* 64 MB I/O access window. On 4716, use
1031 + * sbtopcie0 to access the device registers. We
1032 + * can't use address match 2 (1 GB window) region
1033 + * as mips can't generate 64-bit address on the
1036 + if (bus->chipinfo.id == 0x4716 || bus->chipinfo.id == 0x4748) {
1037 + pc_host->mem_resource.start = BCMA_SOC_PCI_MEM;
1038 + pc_host->mem_resource.end = BCMA_SOC_PCI_MEM +
1039 + BCMA_SOC_PCI_MEM_SZ - 1;
1040 + pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI0,
1041 + BCMA_CORE_PCI_SBTOPCI_MEM | BCMA_SOC_PCI_MEM);
1042 + } else if (bus->chipinfo.id == 0x5300) {
1043 + tmp = BCMA_CORE_PCI_SBTOPCI_MEM;
1044 + tmp |= BCMA_CORE_PCI_SBTOPCI_PREF;
1045 + tmp |= BCMA_CORE_PCI_SBTOPCI_BURST;
1046 + if (pc->core->core_unit == 0) {
1047 + pc_host->mem_resource.start = BCMA_SOC_PCI_MEM;
1048 + pc_host->mem_resource.end = BCMA_SOC_PCI_MEM +
1049 + BCMA_SOC_PCI_MEM_SZ - 1;
1050 + pci_membase_1G = BCMA_SOC_PCIE_DMA_H32;
1051 + pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI0,
1052 + tmp | BCMA_SOC_PCI_MEM);
1053 + } else if (pc->core->core_unit == 1) {
1054 + pc_host->mem_resource.start = BCMA_SOC_PCI1_MEM;
1055 + pc_host->mem_resource.end = BCMA_SOC_PCI1_MEM +
1056 + BCMA_SOC_PCI_MEM_SZ - 1;
1057 + pci_membase_1G = BCMA_SOC_PCIE1_DMA_H32;
1058 + pc_host->host_cfg_addr = BCMA_SOC_PCI1_CFG;
1059 + pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI0,
1060 + tmp | BCMA_SOC_PCI1_MEM);
1063 + pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI0,
1064 + BCMA_CORE_PCI_SBTOPCI_IO);
1066 + /* 64 MB configuration access window */
1067 + pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI1, BCMA_CORE_PCI_SBTOPCI_CFG0);
1069 + /* 1 GB memory access window */
1070 + pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI2,
1071 + BCMA_CORE_PCI_SBTOPCI_MEM | pci_membase_1G);
1074 + /* As per PCI Express Base Spec 1.1 we need to wait for
1075 + * at least 100 ms from the end of a reset (cold/warm/hot)
1076 + * before issuing configuration requests to PCI Express
1081 + bcma_core_pci_enable_crs(pc);
1083 + /* Enable PCI bridge BAR0 memory & master access */
1084 + tmp = PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
1085 + bcma_extpci_write_config(pc, 0, 0, PCI_COMMAND, &tmp, sizeof(tmp));
1087 + /* Enable PCI interrupts */
1088 + pcicore_write32(pc, BCMA_CORE_PCI_IMASK, BCMA_CORE_PCI_IMASK_INTA);
1090 + /* Ok, ready to run, register it to the system.
1091 + * The following needs change, if we want to port hostmode
1092 + * to non-MIPS platform. */
1093 + io_map_base = (unsigned long)ioremap_nocache(BCMA_SOC_PCI_MEM,
1095 + pc_host->pci_controller.io_map_base = io_map_base;
1096 + set_io_port_base(pc_host->pci_controller.io_map_base);
1097 + /* Give some time to the PCI controller to configure itself with the new
1098 + * values. Not waiting at this point causes crashes of the machine. */
1100 + register_pci_controller(&pc_host->pci_controller);
1104 +/* Early PCI fixup for a device on the PCI-core bridge. */
1105 +static void bcma_core_pci_fixup_pcibridge(struct pci_dev *dev)
1107 + if (dev->bus->ops->read != bcma_core_pci_hostmode_read_config) {
1108 + /* This is not a device on the PCI-core bridge. */
1111 + if (PCI_SLOT(dev->devfn) != 0)
1114 + pr_info("PCI: Fixing up bridge %s\n", pci_name(dev));
1116 + /* Enable PCI bridge bus mastering and memory space */
1117 + pci_set_master(dev);
1118 + if (pcibios_enable_device(dev, ~0) < 0) {
1119 + pr_err("PCI: BCMA bridge enable failed\n");
1123 + /* Enable PCI bridge BAR1 prefetch and burst */
1124 + pci_write_config_dword(dev, BCMA_PCI_BAR1_CONTROL, 3);
1126 +DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, bcma_core_pci_fixup_pcibridge);
1128 +/* Early PCI fixup for all PCI-cores to set the correct memory address. */
1129 +static void bcma_core_pci_fixup_addresses(struct pci_dev *dev)
1131 + struct resource *res;
1134 + if (dev->bus->ops->read != bcma_core_pci_hostmode_read_config) {
1135 + /* This is not a device on the PCI-core bridge. */
1138 + if (PCI_SLOT(dev->devfn) == 0)
1141 + pr_info("PCI: Fixing up addresses %s\n", pci_name(dev));
1143 + for (pos = 0; pos < 6; pos++) {
1144 + res = &dev->resource[pos];
1145 + if (res->flags & (IORESOURCE_IO | IORESOURCE_MEM))
1146 + pci_assign_resource(dev, pos);
1149 +DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, bcma_core_pci_fixup_addresses);
1151 +/* This function is called when doing a pci_enable_device().
1152 + * We must first check if the device is a device on the PCI-core bridge. */
1153 +int bcma_core_pci_plat_dev_init(struct pci_dev *dev)
1155 + struct bcma_drv_pci_host *pc_host;
1157 + if (dev->bus->ops->read != bcma_core_pci_hostmode_read_config) {
1158 + /* This is not a device on the PCI-core bridge. */
1161 + pc_host = container_of(dev->bus->ops, struct bcma_drv_pci_host,
1164 + pr_info("PCI: Fixing up device %s\n", pci_name(dev));
1166 + /* Fix up interrupt lines */
1167 + dev->irq = bcma_core_mips_irq(pc_host->pdev->core) + 2;
1168 + pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
1172 +EXPORT_SYMBOL(bcma_core_pci_plat_dev_init);
1174 +/* PCI device IRQ mapping. */
1175 +int bcma_core_pci_pcibios_map_irq(const struct pci_dev *dev)
1177 + struct bcma_drv_pci_host *pc_host;
1179 + if (dev->bus->ops->read != bcma_core_pci_hostmode_read_config) {
1180 + /* This is not a device on the PCI-core bridge. */
1184 + pc_host = container_of(dev->bus->ops, struct bcma_drv_pci_host,
1186 + return bcma_core_mips_irq(pc_host->pdev->core) + 2;
1188 +EXPORT_SYMBOL(bcma_core_pci_pcibios_map_irq);
1189 --- a/drivers/bcma/scan.c
1190 +++ b/drivers/bcma/scan.c
1191 @@ -212,6 +212,17 @@ static struct bcma_device *bcma_find_cor
1195 +static struct bcma_device *bcma_find_core_reverse(struct bcma_bus *bus, u16 coreid)
1197 + struct bcma_device *core;
1199 + list_for_each_entry_reverse(core, &bus->cores, list) {
1200 + if (core->id.id == coreid)
1206 static int bcma_get_next_core(struct bcma_bus *bus, u32 __iomem **eromptr,
1207 struct bcma_device_id *match, int core_num,
1208 struct bcma_device *core)
1209 @@ -353,6 +364,7 @@ static int bcma_get_next_core(struct bcm
1210 void bcma_init_bus(struct bcma_bus *bus)
1213 + struct bcma_chipinfo *chipinfo = &(bus->chipinfo);
1217 @@ -363,9 +375,12 @@ void bcma_init_bus(struct bcma_bus *bus)
1218 bcma_scan_switch_core(bus, BCMA_ADDR_BASE);
1220 tmp = bcma_scan_read32(bus, 0, BCMA_CC_ID);
1221 - bus->chipinfo.id = (tmp & BCMA_CC_ID_ID) >> BCMA_CC_ID_ID_SHIFT;
1222 - bus->chipinfo.rev = (tmp & BCMA_CC_ID_REV) >> BCMA_CC_ID_REV_SHIFT;
1223 - bus->chipinfo.pkg = (tmp & BCMA_CC_ID_PKG) >> BCMA_CC_ID_PKG_SHIFT;
1224 + chipinfo->id = (tmp & BCMA_CC_ID_ID) >> BCMA_CC_ID_ID_SHIFT;
1225 + chipinfo->rev = (tmp & BCMA_CC_ID_REV) >> BCMA_CC_ID_REV_SHIFT;
1226 + chipinfo->pkg = (tmp & BCMA_CC_ID_PKG) >> BCMA_CC_ID_PKG_SHIFT;
1227 + pr_info("Found chip with id 0x%04X, rev 0x%02X and package 0x%02X\n",
1228 + chipinfo->id, chipinfo->rev, chipinfo->pkg);
1230 bus->init_done = true;
1233 @@ -392,6 +407,7 @@ int bcma_bus_scan(struct bcma_bus *bus)
1234 bcma_scan_switch_core(bus, erombase);
1236 while (eromptr < eromend) {
1237 + struct bcma_device *other_core;
1238 struct bcma_device *core = kzalloc(sizeof(*core), GFP_KERNEL);
1241 @@ -399,18 +415,23 @@ int bcma_bus_scan(struct bcma_bus *bus)
1244 err = bcma_get_next_core(bus, &eromptr, NULL, core_num, core);
1245 - if (err == -ENODEV) {
1248 - } else if (err == -ENXIO)
1250 - else if (err == -ESPIPE)
1255 + if (err == -ENODEV) {
1258 + } else if (err == -ENXIO) {
1260 + } else if (err == -ESPIPE) {
1266 core->core_index = core_num++;
1268 + other_core = bcma_find_core_reverse(bus, core->id.id);
1269 + core->core_unit = (other_core == NULL) ? 0 : other_core->core_unit + 1;
1271 pr_info("Core %d found: %s "
1272 "(manuf 0x%03X, id 0x%03X, rev 0x%02X, class 0x%X)\n",
1273 --- a/drivers/bcma/sprom.c
1274 +++ b/drivers/bcma/sprom.c
1276 * Broadcom specific AMBA
1279 + * Copyright 2011, 2012, Hauke Mehrtens <hauke@hauke-m.de>
1281 * Licensed under the GNU/GPL. See COPYING for details.
1285 #include <linux/dma-mapping.h>
1286 #include <linux/slab.h>
1288 -#define SPOFF(offset) ((offset) / sizeof(u16))
1289 +static int(*get_fallback_sprom)(struct bcma_bus *dev, struct ssb_sprom *out);
1292 + * bcma_arch_register_fallback_sprom - Registers a method providing a
1293 + * fallback SPROM if no SPROM is found.
1295 + * @sprom_callback: The callback function.
1297 + * With this function the architecture implementation may register a
1298 + * callback handler which fills the SPROM data structure. The fallback is
1299 + * used for PCI based BCMA devices, where no valid SPROM can be found
1300 + * in the shadow registers and to provide the SPROM for SoCs where BCMA is
1301 + * to controll the system bus.
1303 + * This function is useful for weird architectures that have a half-assed
1304 + * BCMA device hardwired to their PCI bus.
1306 + * This function is available for architecture code, only. So it is not
1309 +int bcma_arch_register_fallback_sprom(int (*sprom_callback)(struct bcma_bus *bus,
1310 + struct ssb_sprom *out))
1312 + if (get_fallback_sprom)
1314 + get_fallback_sprom = sprom_callback;
1319 +static int bcma_fill_sprom_with_fallback(struct bcma_bus *bus,
1320 + struct ssb_sprom *out)
1324 + if (!get_fallback_sprom) {
1329 + err = get_fallback_sprom(bus, out);
1333 + pr_debug("Using SPROM revision %d provided by"
1334 + " platform.\n", bus->sprom.revision);
1337 + pr_warn("Using fallback SPROM failed (err %d)\n", err);
1341 /**************************************************
1343 @@ -124,37 +176,253 @@ static int bcma_sprom_valid(const u16 *s
1345 **************************************************/
1347 +#define SPOFF(offset) ((offset) / sizeof(u16))
1349 +#define SPEX(_field, _offset, _mask, _shift) \
1350 + bus->sprom._field = ((sprom[SPOFF(_offset)] & (_mask)) >> (_shift))
1352 static void bcma_sprom_extract_r8(struct bcma_bus *bus, const u16 *sprom)
1357 + u16 pwr_info_offset[] = {
1358 + SSB_SROM8_PWR_INFO_CORE0, SSB_SROM8_PWR_INFO_CORE1,
1359 + SSB_SROM8_PWR_INFO_CORE2, SSB_SROM8_PWR_INFO_CORE3
1361 + BUILD_BUG_ON(ARRAY_SIZE(pwr_info_offset) !=
1362 + ARRAY_SIZE(bus->sprom.core_pwr_info));
1364 + bus->sprom.revision = sprom[SSB_SPROMSIZE_WORDS_R4 - 1] &
1365 + SSB_SPROM_REVISION_REV;
1367 for (i = 0; i < 3; i++) {
1368 v = sprom[SPOFF(SSB_SPROM8_IL0MAC) + i];
1369 *(((__be16 *)bus->sprom.il0mac) + i) = cpu_to_be16(v);
1372 - bus->sprom.board_rev = sprom[SPOFF(SSB_SPROM8_BOARDREV)];
1373 + SPEX(board_rev, SSB_SPROM8_BOARDREV, ~0, 0);
1375 - bus->sprom.boardflags_lo = sprom[SPOFF(SSB_SPROM8_BFLLO)];
1376 - bus->sprom.boardflags_hi = sprom[SPOFF(SSB_SPROM8_BFLHI)];
1377 - bus->sprom.boardflags2_lo = sprom[SPOFF(SSB_SPROM8_BFL2LO)];
1378 - bus->sprom.boardflags2_hi = sprom[SPOFF(SSB_SPROM8_BFL2HI)];
1379 + SPEX(txpid2g[0], SSB_SPROM4_TXPID2G01, SSB_SPROM4_TXPID2G0,
1380 + SSB_SPROM4_TXPID2G0_SHIFT);
1381 + SPEX(txpid2g[1], SSB_SPROM4_TXPID2G01, SSB_SPROM4_TXPID2G1,
1382 + SSB_SPROM4_TXPID2G1_SHIFT);
1383 + SPEX(txpid2g[2], SSB_SPROM4_TXPID2G23, SSB_SPROM4_TXPID2G2,
1384 + SSB_SPROM4_TXPID2G2_SHIFT);
1385 + SPEX(txpid2g[3], SSB_SPROM4_TXPID2G23, SSB_SPROM4_TXPID2G3,
1386 + SSB_SPROM4_TXPID2G3_SHIFT);
1388 + SPEX(txpid5gl[0], SSB_SPROM4_TXPID5GL01, SSB_SPROM4_TXPID5GL0,
1389 + SSB_SPROM4_TXPID5GL0_SHIFT);
1390 + SPEX(txpid5gl[1], SSB_SPROM4_TXPID5GL01, SSB_SPROM4_TXPID5GL1,
1391 + SSB_SPROM4_TXPID5GL1_SHIFT);
1392 + SPEX(txpid5gl[2], SSB_SPROM4_TXPID5GL23, SSB_SPROM4_TXPID5GL2,
1393 + SSB_SPROM4_TXPID5GL2_SHIFT);
1394 + SPEX(txpid5gl[3], SSB_SPROM4_TXPID5GL23, SSB_SPROM4_TXPID5GL3,
1395 + SSB_SPROM4_TXPID5GL3_SHIFT);
1397 + SPEX(txpid5g[0], SSB_SPROM4_TXPID5G01, SSB_SPROM4_TXPID5G0,
1398 + SSB_SPROM4_TXPID5G0_SHIFT);
1399 + SPEX(txpid5g[1], SSB_SPROM4_TXPID5G01, SSB_SPROM4_TXPID5G1,
1400 + SSB_SPROM4_TXPID5G1_SHIFT);
1401 + SPEX(txpid5g[2], SSB_SPROM4_TXPID5G23, SSB_SPROM4_TXPID5G2,
1402 + SSB_SPROM4_TXPID5G2_SHIFT);
1403 + SPEX(txpid5g[3], SSB_SPROM4_TXPID5G23, SSB_SPROM4_TXPID5G3,
1404 + SSB_SPROM4_TXPID5G3_SHIFT);
1406 + SPEX(txpid5gh[0], SSB_SPROM4_TXPID5GH01, SSB_SPROM4_TXPID5GH0,
1407 + SSB_SPROM4_TXPID5GH0_SHIFT);
1408 + SPEX(txpid5gh[1], SSB_SPROM4_TXPID5GH01, SSB_SPROM4_TXPID5GH1,
1409 + SSB_SPROM4_TXPID5GH1_SHIFT);
1410 + SPEX(txpid5gh[2], SSB_SPROM4_TXPID5GH23, SSB_SPROM4_TXPID5GH2,
1411 + SSB_SPROM4_TXPID5GH2_SHIFT);
1412 + SPEX(txpid5gh[3], SSB_SPROM4_TXPID5GH23, SSB_SPROM4_TXPID5GH3,
1413 + SSB_SPROM4_TXPID5GH3_SHIFT);
1415 + SPEX(boardflags_lo, SSB_SPROM8_BFLLO, ~0, 0);
1416 + SPEX(boardflags_hi, SSB_SPROM8_BFLHI, ~0, 0);
1417 + SPEX(boardflags2_lo, SSB_SPROM8_BFL2LO, ~0, 0);
1418 + SPEX(boardflags2_hi, SSB_SPROM8_BFL2HI, ~0, 0);
1420 + SPEX(country_code, SSB_SPROM8_CCODE, ~0, 0);
1422 + /* Extract cores power info info */
1423 + for (i = 0; i < ARRAY_SIZE(pwr_info_offset); i++) {
1424 + o = pwr_info_offset[i];
1425 + SPEX(core_pwr_info[i].itssi_2g, o + SSB_SROM8_2G_MAXP_ITSSI,
1426 + SSB_SPROM8_2G_ITSSI, SSB_SPROM8_2G_ITSSI_SHIFT);
1427 + SPEX(core_pwr_info[i].maxpwr_2g, o + SSB_SROM8_2G_MAXP_ITSSI,
1428 + SSB_SPROM8_2G_MAXP, 0);
1430 + SPEX(core_pwr_info[i].pa_2g[0], o + SSB_SROM8_2G_PA_0, ~0, 0);
1431 + SPEX(core_pwr_info[i].pa_2g[1], o + SSB_SROM8_2G_PA_1, ~0, 0);
1432 + SPEX(core_pwr_info[i].pa_2g[2], o + SSB_SROM8_2G_PA_2, ~0, 0);
1434 + SPEX(core_pwr_info[i].itssi_5g, o + SSB_SROM8_5G_MAXP_ITSSI,
1435 + SSB_SPROM8_5G_ITSSI, SSB_SPROM8_5G_ITSSI_SHIFT);
1436 + SPEX(core_pwr_info[i].maxpwr_5g, o + SSB_SROM8_5G_MAXP_ITSSI,
1437 + SSB_SPROM8_5G_MAXP, 0);
1438 + SPEX(core_pwr_info[i].maxpwr_5gh, o + SSB_SPROM8_5GHL_MAXP,
1439 + SSB_SPROM8_5GH_MAXP, 0);
1440 + SPEX(core_pwr_info[i].maxpwr_5gl, o + SSB_SPROM8_5GHL_MAXP,
1441 + SSB_SPROM8_5GL_MAXP, SSB_SPROM8_5GL_MAXP_SHIFT);
1443 + SPEX(core_pwr_info[i].pa_5gl[0], o + SSB_SROM8_5GL_PA_0, ~0, 0);
1444 + SPEX(core_pwr_info[i].pa_5gl[1], o + SSB_SROM8_5GL_PA_1, ~0, 0);
1445 + SPEX(core_pwr_info[i].pa_5gl[2], o + SSB_SROM8_5GL_PA_2, ~0, 0);
1446 + SPEX(core_pwr_info[i].pa_5g[0], o + SSB_SROM8_5G_PA_0, ~0, 0);
1447 + SPEX(core_pwr_info[i].pa_5g[1], o + SSB_SROM8_5G_PA_1, ~0, 0);
1448 + SPEX(core_pwr_info[i].pa_5g[2], o + SSB_SROM8_5G_PA_2, ~0, 0);
1449 + SPEX(core_pwr_info[i].pa_5gh[0], o + SSB_SROM8_5GH_PA_0, ~0, 0);
1450 + SPEX(core_pwr_info[i].pa_5gh[1], o + SSB_SROM8_5GH_PA_1, ~0, 0);
1451 + SPEX(core_pwr_info[i].pa_5gh[2], o + SSB_SROM8_5GH_PA_2, ~0, 0);
1454 + SPEX(fem.ghz2.tssipos, SSB_SPROM8_FEM2G, SSB_SROM8_FEM_TSSIPOS,
1455 + SSB_SROM8_FEM_TSSIPOS_SHIFT);
1456 + SPEX(fem.ghz2.extpa_gain, SSB_SPROM8_FEM2G, SSB_SROM8_FEM_EXTPA_GAIN,
1457 + SSB_SROM8_FEM_EXTPA_GAIN_SHIFT);
1458 + SPEX(fem.ghz2.pdet_range, SSB_SPROM8_FEM2G, SSB_SROM8_FEM_PDET_RANGE,
1459 + SSB_SROM8_FEM_PDET_RANGE_SHIFT);
1460 + SPEX(fem.ghz2.tr_iso, SSB_SPROM8_FEM2G, SSB_SROM8_FEM_TR_ISO,
1461 + SSB_SROM8_FEM_TR_ISO_SHIFT);
1462 + SPEX(fem.ghz2.antswlut, SSB_SPROM8_FEM2G, SSB_SROM8_FEM_ANTSWLUT,
1463 + SSB_SROM8_FEM_ANTSWLUT_SHIFT);
1465 + SPEX(fem.ghz5.tssipos, SSB_SPROM8_FEM5G, SSB_SROM8_FEM_TSSIPOS,
1466 + SSB_SROM8_FEM_TSSIPOS_SHIFT);
1467 + SPEX(fem.ghz5.extpa_gain, SSB_SPROM8_FEM5G, SSB_SROM8_FEM_EXTPA_GAIN,
1468 + SSB_SROM8_FEM_EXTPA_GAIN_SHIFT);
1469 + SPEX(fem.ghz5.pdet_range, SSB_SPROM8_FEM5G, SSB_SROM8_FEM_PDET_RANGE,
1470 + SSB_SROM8_FEM_PDET_RANGE_SHIFT);
1471 + SPEX(fem.ghz5.tr_iso, SSB_SPROM8_FEM5G, SSB_SROM8_FEM_TR_ISO,
1472 + SSB_SROM8_FEM_TR_ISO_SHIFT);
1473 + SPEX(fem.ghz5.antswlut, SSB_SPROM8_FEM5G, SSB_SROM8_FEM_ANTSWLUT,
1474 + SSB_SROM8_FEM_ANTSWLUT_SHIFT);
1478 + * Indicates the presence of external SPROM.
1480 +static bool bcma_sprom_ext_available(struct bcma_bus *bus)
1486 + if (bus->drv_cc.core->id.rev >= 31) {
1487 + if (!(bus->drv_cc.capabilities & BCMA_CC_CAP_SPROM))
1490 + srom_control = bcma_read32(bus->drv_cc.core,
1491 + BCMA_CC_SROM_CONTROL);
1492 + return srom_control & BCMA_CC_SROM_CONTROL_PRESENT;
1495 + /* older chipcommon revisions use chip status register */
1496 + chip_status = bcma_read32(bus->drv_cc.core, BCMA_CC_CHIPSTAT);
1497 + switch (bus->chipinfo.id) {
1499 + present_mask = BCMA_CC_CHIPST_4313_SPROM_PRESENT;
1503 + present_mask = BCMA_CC_CHIPST_4331_SPROM_PRESENT;
1510 + return chip_status & present_mask;
1514 + * Indicates that on-chip OTP memory is present and enabled.
1516 +static bool bcma_sprom_onchip_available(struct bcma_bus *bus)
1522 + chip_status = bcma_read32(bus->drv_cc.core, BCMA_CC_CHIPSTAT);
1523 + switch (bus->chipinfo.id) {
1525 + present = chip_status & BCMA_CC_CHIPST_4313_OTP_PRESENT;
1529 + present = chip_status & BCMA_CC_CHIPST_4331_OTP_PRESENT;
1534 + /* for these chips OTP is always available */
1543 - bus->sprom.country_code = sprom[SPOFF(SSB_SPROM8_CCODE)];
1545 + otpsize = bus->drv_cc.capabilities & BCMA_CC_CAP_OTPS;
1546 + otpsize >>= BCMA_CC_CAP_OTPS_SHIFT;
1549 + return otpsize != 0;
1553 + * Verify OTP is filled and determine the byte
1554 + * offset where SPROM data is located.
1556 + * On error, returns 0; byte offset otherwise.
1558 +static int bcma_sprom_onchip_offset(struct bcma_bus *bus)
1560 + struct bcma_device *cc = bus->drv_cc.core;
1563 + /* verify OTP status */
1564 + if ((bcma_read32(cc, BCMA_CC_OTPS) & BCMA_CC_OTPS_GU_PROG_HW) == 0)
1567 + /* obtain bit offset from otplayout register */
1568 + offset = (bcma_read32(cc, BCMA_CC_OTPL) & BCMA_CC_OTPL_GURGN_OFFSET);
1569 + return BCMA_CC_SPROM + (offset >> 3);
1572 int bcma_sprom_get(struct bcma_bus *bus)
1575 + u16 offset = BCMA_CC_SPROM;
1579 if (!bus->drv_cc.core)
1582 - if (!(bus->drv_cc.capabilities & BCMA_CC_CAP_SPROM))
1584 + if (!bcma_sprom_ext_available(bus)) {
1586 + * External SPROM takes precedence so check
1587 + * on-chip OTP only when no external SPROM
1590 + if (bcma_sprom_onchip_available(bus)) {
1591 + /* determine offset */
1592 + offset = bcma_sprom_onchip_offset(bus);
1596 + * Maybe there is no SPROM on the device?
1597 + * Now we ask the arch code if there is some sprom
1598 + * available for this device in some other storage.
1600 + err = bcma_fill_sprom_with_fallback(bus, &bus->sprom);
1605 sprom = kcalloc(SSB_SPROMSIZE_WORDS_R4, sizeof(u16),
1607 @@ -164,11 +432,7 @@ int bcma_sprom_get(struct bcma_bus *bus)
1608 if (bus->chipinfo.id == 0x4331)
1609 bcma_chipco_bcm4331_ext_pa_lines_ctl(&bus->drv_cc, false);
1611 - /* Most cards have SPROM moved by additional offset 0x30 (48 dwords).
1612 - * According to brcm80211 this applies to cards with PCIe rev >= 6
1613 - * TODO: understand this condition and use it */
1614 - offset = (bus->chipinfo.id == 0x4331) ? BCMA_CC_SPROM :
1615 - BCMA_CC_SPROM_PCIE6;
1616 + pr_debug("SPROM offset 0x%x\n", offset);
1617 bcma_sprom_read(bus, offset, sprom);
1619 if (bus->chipinfo.id == 0x4331)
1620 --- a/include/linux/bcma/bcma.h
1621 +++ b/include/linux/bcma/bcma.h
1622 @@ -136,6 +136,7 @@ struct bcma_device {
1623 bool dev_registered;
1630 @@ -162,7 +163,7 @@ struct bcma_driver {
1632 int (*probe)(struct bcma_device *dev);
1633 void (*remove)(struct bcma_device *dev);
1634 - int (*suspend)(struct bcma_device *dev, pm_message_t state);
1635 + int (*suspend)(struct bcma_device *dev);
1636 int (*resume)(struct bcma_device *dev);
1637 void (*shutdown)(struct bcma_device *dev);
1639 @@ -175,6 +176,12 @@ int __bcma_driver_register(struct bcma_d
1641 extern void bcma_driver_unregister(struct bcma_driver *drv);
1643 +/* Set a fallback SPROM.
1644 + * See kdoc at the function definition for complete documentation. */
1645 +extern int bcma_arch_register_fallback_sprom(
1646 + int (*sprom_callback)(struct bcma_bus *bus,
1647 + struct ssb_sprom *out));
1650 /* The MMIO area. */
1652 @@ -195,6 +202,7 @@ struct bcma_bus {
1653 struct list_head cores;
1658 struct bcma_drv_cc drv_cc;
1659 struct bcma_drv_pci drv_pci;
1660 @@ -205,62 +213,84 @@ struct bcma_bus {
1661 struct ssb_sprom sprom;
1664 -extern inline u32 bcma_read8(struct bcma_device *core, u16 offset)
1665 +static inline u32 bcma_read8(struct bcma_device *core, u16 offset)
1667 return core->bus->ops->read8(core, offset);
1669 -extern inline u32 bcma_read16(struct bcma_device *core, u16 offset)
1670 +static inline u32 bcma_read16(struct bcma_device *core, u16 offset)
1672 return core->bus->ops->read16(core, offset);
1674 -extern inline u32 bcma_read32(struct bcma_device *core, u16 offset)
1675 +static inline u32 bcma_read32(struct bcma_device *core, u16 offset)
1677 return core->bus->ops->read32(core, offset);
1681 void bcma_write8(struct bcma_device *core, u16 offset, u32 value)
1683 core->bus->ops->write8(core, offset, value);
1687 void bcma_write16(struct bcma_device *core, u16 offset, u32 value)
1689 core->bus->ops->write16(core, offset, value);
1693 void bcma_write32(struct bcma_device *core, u16 offset, u32 value)
1695 core->bus->ops->write32(core, offset, value);
1697 #ifdef CONFIG_BCMA_BLOCKIO
1698 -extern inline void bcma_block_read(struct bcma_device *core, void *buffer,
1699 +static inline void bcma_block_read(struct bcma_device *core, void *buffer,
1700 size_t count, u16 offset, u8 reg_width)
1702 core->bus->ops->block_read(core, buffer, count, offset, reg_width);
1704 -extern inline void bcma_block_write(struct bcma_device *core, const void *buffer,
1705 - size_t count, u16 offset, u8 reg_width)
1706 +static inline void bcma_block_write(struct bcma_device *core,
1707 + const void *buffer, size_t count,
1708 + u16 offset, u8 reg_width)
1710 core->bus->ops->block_write(core, buffer, count, offset, reg_width);
1713 -extern inline u32 bcma_aread32(struct bcma_device *core, u16 offset)
1714 +static inline u32 bcma_aread32(struct bcma_device *core, u16 offset)
1716 return core->bus->ops->aread32(core, offset);
1720 void bcma_awrite32(struct bcma_device *core, u16 offset, u32 value)
1722 core->bus->ops->awrite32(core, offset, value);
1725 -#define bcma_mask32(cc, offset, mask) \
1726 - bcma_write32(cc, offset, bcma_read32(cc, offset) & (mask))
1727 -#define bcma_set32(cc, offset, set) \
1728 - bcma_write32(cc, offset, bcma_read32(cc, offset) | (set))
1729 -#define bcma_maskset32(cc, offset, mask, set) \
1730 - bcma_write32(cc, offset, (bcma_read32(cc, offset) & (mask)) | (set))
1731 +static inline void bcma_mask32(struct bcma_device *cc, u16 offset, u32 mask)
1733 + bcma_write32(cc, offset, bcma_read32(cc, offset) & mask);
1735 +static inline void bcma_set32(struct bcma_device *cc, u16 offset, u32 set)
1737 + bcma_write32(cc, offset, bcma_read32(cc, offset) | set);
1739 +static inline void bcma_maskset32(struct bcma_device *cc,
1740 + u16 offset, u32 mask, u32 set)
1742 + bcma_write32(cc, offset, (bcma_read32(cc, offset) & mask) | set);
1744 +static inline void bcma_mask16(struct bcma_device *cc, u16 offset, u16 mask)
1746 + bcma_write16(cc, offset, bcma_read16(cc, offset) & mask);
1748 +static inline void bcma_set16(struct bcma_device *cc, u16 offset, u16 set)
1750 + bcma_write16(cc, offset, bcma_read16(cc, offset) | set);
1752 +static inline void bcma_maskset16(struct bcma_device *cc,
1753 + u16 offset, u16 mask, u16 set)
1755 + bcma_write16(cc, offset, (bcma_read16(cc, offset) & mask) | set);
1758 +extern struct bcma_device *bcma_find_core(struct bcma_bus *bus, u16 coreid);
1759 extern bool bcma_core_is_enabled(struct bcma_device *core);
1760 extern void bcma_core_disable(struct bcma_device *core, u32 flags);
1761 extern int bcma_core_enable(struct bcma_device *core, u32 flags);
1762 --- a/include/linux/bcma/bcma_driver_chipcommon.h
1763 +++ b/include/linux/bcma/bcma_driver_chipcommon.h
1765 #define BCMA_CC_OTPS_HW_PROTECT 0x00000001
1766 #define BCMA_CC_OTPS_SW_PROTECT 0x00000002
1767 #define BCMA_CC_OTPS_CID_PROTECT 0x00000004
1768 +#define BCMA_CC_OTPS_GU_PROG_IND 0x00000F00 /* General Use programmed indication */
1769 +#define BCMA_CC_OTPS_GU_PROG_IND_SHIFT 8
1770 +#define BCMA_CC_OTPS_GU_PROG_HW 0x00000100 /* HW region programmed */
1771 #define BCMA_CC_OTPC 0x0014 /* OTP control */
1772 #define BCMA_CC_OTPC_RECWAIT 0xFF000000
1773 #define BCMA_CC_OTPC_PROGWAIT 0x00FFFF00
1775 #define BCMA_CC_OTPP_READ 0x40000000
1776 #define BCMA_CC_OTPP_START 0x80000000
1777 #define BCMA_CC_OTPP_BUSY 0x80000000
1778 +#define BCMA_CC_OTPL 0x001C /* OTP layout */
1779 +#define BCMA_CC_OTPL_GURGN_OFFSET 0x00000FFF /* offset of general use region */
1780 #define BCMA_CC_IRQSTAT 0x0020
1781 #define BCMA_CC_IRQMASK 0x0024
1782 #define BCMA_CC_IRQ_GPIO 0x00000001 /* gpio intr */
1784 #define BCMA_CC_IRQ_WDRESET 0x80000000 /* watchdog reset occurred */
1785 #define BCMA_CC_CHIPCTL 0x0028 /* Rev >= 11 only */
1786 #define BCMA_CC_CHIPSTAT 0x002C /* Rev >= 11 only */
1787 +#define BCMA_CC_CHIPST_4313_SPROM_PRESENT 1
1788 +#define BCMA_CC_CHIPST_4313_OTP_PRESENT 2
1789 +#define BCMA_CC_CHIPST_4331_SPROM_PRESENT 2
1790 +#define BCMA_CC_CHIPST_4331_OTP_PRESENT 4
1791 #define BCMA_CC_JCMD 0x0030 /* Rev >= 10 only */
1792 #define BCMA_CC_JCMD_START 0x80000000
1793 #define BCMA_CC_JCMD_BUSY 0x80000000
1794 @@ -181,6 +190,22 @@
1795 #define BCMA_CC_FLASH_CFG 0x0128
1796 #define BCMA_CC_FLASH_CFG_DS 0x0010 /* Data size, 0=8bit, 1=16bit */
1797 #define BCMA_CC_FLASH_WAITCNT 0x012C
1798 +#define BCMA_CC_SROM_CONTROL 0x0190
1799 +#define BCMA_CC_SROM_CONTROL_START 0x80000000
1800 +#define BCMA_CC_SROM_CONTROL_BUSY 0x80000000
1801 +#define BCMA_CC_SROM_CONTROL_OPCODE 0x60000000
1802 +#define BCMA_CC_SROM_CONTROL_OP_READ 0x00000000
1803 +#define BCMA_CC_SROM_CONTROL_OP_WRITE 0x20000000
1804 +#define BCMA_CC_SROM_CONTROL_OP_WRDIS 0x40000000
1805 +#define BCMA_CC_SROM_CONTROL_OP_WREN 0x60000000
1806 +#define BCMA_CC_SROM_CONTROL_OTPSEL 0x00000010
1807 +#define BCMA_CC_SROM_CONTROL_LOCK 0x00000008
1808 +#define BCMA_CC_SROM_CONTROL_SIZE_MASK 0x00000006
1809 +#define BCMA_CC_SROM_CONTROL_SIZE_1K 0x00000000
1810 +#define BCMA_CC_SROM_CONTROL_SIZE_4K 0x00000002
1811 +#define BCMA_CC_SROM_CONTROL_SIZE_16K 0x00000004
1812 +#define BCMA_CC_SROM_CONTROL_SIZE_SHIFT 1
1813 +#define BCMA_CC_SROM_CONTROL_PRESENT 0x00000001
1814 /* 0x1E0 is defined as shared BCMA_CLKCTLST */
1815 #define BCMA_CC_HW_WORKAROUND 0x01E4 /* Hardware workaround (rev >= 20) */
1816 #define BCMA_CC_UART0_DATA 0x0300
1818 #define BCMA_CC_PMU_CTL 0x0600 /* PMU control */
1819 #define BCMA_CC_PMU_CTL_ILP_DIV 0xFFFF0000 /* ILP div mask */
1820 #define BCMA_CC_PMU_CTL_ILP_DIV_SHIFT 16
1821 +#define BCMA_CC_PMU_CTL_PLL_UPD 0x00000400
1822 #define BCMA_CC_PMU_CTL_NOILPONW 0x00000200 /* No ILP on wait */
1823 #define BCMA_CC_PMU_CTL_HTREQEN 0x00000100 /* HT req enable */
1824 #define BCMA_CC_PMU_CTL_ALPREQEN 0x00000080 /* ALP req enable */
1826 #define BCMA_CC_PLLCTL_ADDR 0x0660
1827 #define BCMA_CC_PLLCTL_DATA 0x0664
1828 #define BCMA_CC_SPROM 0x0800 /* SPROM beginning */
1829 -#define BCMA_CC_SPROM_PCIE6 0x0830 /* SPROM beginning on PCIe rev >= 6 */
1831 /* Divider allocation in 4716/47162/5356 */
1832 #define BCMA_CC_PMU5_MAINPLL_CPU 1
1833 --- a/include/linux/bcma/bcma_driver_pci.h
1834 +++ b/include/linux/bcma/bcma_driver_pci.h
1835 @@ -53,6 +53,35 @@ struct pci_dev;
1836 #define BCMA_CORE_PCI_SBTOPCI1_MASK 0xFC000000
1837 #define BCMA_CORE_PCI_SBTOPCI2 0x0108 /* Backplane to PCI translation 2 (sbtopci2) */
1838 #define BCMA_CORE_PCI_SBTOPCI2_MASK 0xC0000000
1839 +#define BCMA_CORE_PCI_CONFIG_ADDR 0x0120 /* pcie config space access */
1840 +#define BCMA_CORE_PCI_CONFIG_DATA 0x0124 /* pcie config space access */
1841 +#define BCMA_CORE_PCI_MDIO_CONTROL 0x0128 /* controls the mdio access */
1842 +#define BCMA_CORE_PCI_MDIOCTL_DIVISOR_MASK 0x7f /* clock to be used on MDIO */
1843 +#define BCMA_CORE_PCI_MDIOCTL_DIVISOR_VAL 0x2
1844 +#define BCMA_CORE_PCI_MDIOCTL_PREAM_EN 0x80 /* Enable preamble sequnce */
1845 +#define BCMA_CORE_PCI_MDIOCTL_ACCESS_DONE 0x100 /* Tranaction complete */
1846 +#define BCMA_CORE_PCI_MDIO_DATA 0x012c /* Data to the mdio access */
1847 +#define BCMA_CORE_PCI_MDIODATA_MASK 0x0000ffff /* data 2 bytes */
1848 +#define BCMA_CORE_PCI_MDIODATA_TA 0x00020000 /* Turnaround */
1849 +#define BCMA_CORE_PCI_MDIODATA_REGADDR_SHF_OLD 18 /* Regaddr shift (rev < 10) */
1850 +#define BCMA_CORE_PCI_MDIODATA_REGADDR_MASK_OLD 0x003c0000 /* Regaddr Mask (rev < 10) */
1851 +#define BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF_OLD 22 /* Physmedia devaddr shift (rev < 10) */
1852 +#define BCMA_CORE_PCI_MDIODATA_DEVADDR_MASK_OLD 0x0fc00000 /* Physmedia devaddr Mask (rev < 10) */
1853 +#define BCMA_CORE_PCI_MDIODATA_REGADDR_SHF 18 /* Regaddr shift */
1854 +#define BCMA_CORE_PCI_MDIODATA_REGADDR_MASK 0x007c0000 /* Regaddr Mask */
1855 +#define BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF 23 /* Physmedia devaddr shift */
1856 +#define BCMA_CORE_PCI_MDIODATA_DEVADDR_MASK 0x0f800000 /* Physmedia devaddr Mask */
1857 +#define BCMA_CORE_PCI_MDIODATA_WRITE 0x10000000 /* write Transaction */
1858 +#define BCMA_CORE_PCI_MDIODATA_READ 0x20000000 /* Read Transaction */
1859 +#define BCMA_CORE_PCI_MDIODATA_START 0x40000000 /* start of Transaction */
1860 +#define BCMA_CORE_PCI_MDIODATA_DEV_ADDR 0x0 /* dev address for serdes */
1861 +#define BCMA_CORE_PCI_MDIODATA_BLK_ADDR 0x1F /* blk address for serdes */
1862 +#define BCMA_CORE_PCI_MDIODATA_DEV_PLL 0x1d /* SERDES PLL Dev */
1863 +#define BCMA_CORE_PCI_MDIODATA_DEV_TX 0x1e /* SERDES TX Dev */
1864 +#define BCMA_CORE_PCI_MDIODATA_DEV_RX 0x1f /* SERDES RX Dev */
1865 +#define BCMA_CORE_PCI_PCIEIND_ADDR 0x0130 /* indirect access to the internal register */
1866 +#define BCMA_CORE_PCI_PCIEIND_DATA 0x0134 /* Data to/from the internal regsiter */
1867 +#define BCMA_CORE_PCI_CLKREQENCTRL 0x0138 /* >= rev 6, Clkreq rdma control */
1868 #define BCMA_CORE_PCI_PCICFG0 0x0400 /* PCI config space 0 (rev >= 8) */
1869 #define BCMA_CORE_PCI_PCICFG1 0x0500 /* PCI config space 1 (rev >= 8) */
1870 #define BCMA_CORE_PCI_PCICFG2 0x0600 /* PCI config space 2 (rev >= 8) */
1871 @@ -72,20 +101,114 @@ struct pci_dev;
1872 #define BCMA_CORE_PCI_SBTOPCI_RC_READL 0x00000010 /* Memory read line */
1873 #define BCMA_CORE_PCI_SBTOPCI_RC_READM 0x00000020 /* Memory read multiple */
1875 +/* PCIE protocol PHY diagnostic registers */
1876 +#define BCMA_CORE_PCI_PLP_MODEREG 0x200 /* Mode */
1877 +#define BCMA_CORE_PCI_PLP_STATUSREG 0x204 /* Status */
1878 +#define BCMA_CORE_PCI_PLP_POLARITYINV_STAT 0x10 /* Status reg PCIE_PLP_STATUSREG */
1879 +#define BCMA_CORE_PCI_PLP_LTSSMCTRLREG 0x208 /* LTSSM control */
1880 +#define BCMA_CORE_PCI_PLP_LTLINKNUMREG 0x20c /* Link Training Link number */
1881 +#define BCMA_CORE_PCI_PLP_LTLANENUMREG 0x210 /* Link Training Lane number */
1882 +#define BCMA_CORE_PCI_PLP_LTNFTSREG 0x214 /* Link Training N_FTS */
1883 +#define BCMA_CORE_PCI_PLP_ATTNREG 0x218 /* Attention */
1884 +#define BCMA_CORE_PCI_PLP_ATTNMASKREG 0x21C /* Attention Mask */
1885 +#define BCMA_CORE_PCI_PLP_RXERRCTR 0x220 /* Rx Error */
1886 +#define BCMA_CORE_PCI_PLP_RXFRMERRCTR 0x224 /* Rx Framing Error */
1887 +#define BCMA_CORE_PCI_PLP_RXERRTHRESHREG 0x228 /* Rx Error threshold */
1888 +#define BCMA_CORE_PCI_PLP_TESTCTRLREG 0x22C /* Test Control reg */
1889 +#define BCMA_CORE_PCI_PLP_SERDESCTRLOVRDREG 0x230 /* SERDES Control Override */
1890 +#define BCMA_CORE_PCI_PLP_TIMINGOVRDREG 0x234 /* Timing param override */
1891 +#define BCMA_CORE_PCI_PLP_RXTXSMDIAGREG 0x238 /* RXTX State Machine Diag */
1892 +#define BCMA_CORE_PCI_PLP_LTSSMDIAGREG 0x23C /* LTSSM State Machine Diag */
1894 +/* PCIE protocol DLLP diagnostic registers */
1895 +#define BCMA_CORE_PCI_DLLP_LCREG 0x100 /* Link Control */
1896 +#define BCMA_CORE_PCI_DLLP_LSREG 0x104 /* Link Status */
1897 +#define BCMA_CORE_PCI_DLLP_LAREG 0x108 /* Link Attention */
1898 +#define BCMA_CORE_PCI_DLLP_LSREG_LINKUP (1 << 16)
1899 +#define BCMA_CORE_PCI_DLLP_LAMASKREG 0x10C /* Link Attention Mask */
1900 +#define BCMA_CORE_PCI_DLLP_NEXTTXSEQNUMREG 0x110 /* Next Tx Seq Num */
1901 +#define BCMA_CORE_PCI_DLLP_ACKEDTXSEQNUMREG 0x114 /* Acked Tx Seq Num */
1902 +#define BCMA_CORE_PCI_DLLP_PURGEDTXSEQNUMREG 0x118 /* Purged Tx Seq Num */
1903 +#define BCMA_CORE_PCI_DLLP_RXSEQNUMREG 0x11C /* Rx Sequence Number */
1904 +#define BCMA_CORE_PCI_DLLP_LRREG 0x120 /* Link Replay */
1905 +#define BCMA_CORE_PCI_DLLP_LACKTOREG 0x124 /* Link Ack Timeout */
1906 +#define BCMA_CORE_PCI_DLLP_PMTHRESHREG 0x128 /* Power Management Threshold */
1907 +#define BCMA_CORE_PCI_DLLP_RTRYWPREG 0x12C /* Retry buffer write ptr */
1908 +#define BCMA_CORE_PCI_DLLP_RTRYRPREG 0x130 /* Retry buffer Read ptr */
1909 +#define BCMA_CORE_PCI_DLLP_RTRYPPREG 0x134 /* Retry buffer Purged ptr */
1910 +#define BCMA_CORE_PCI_DLLP_RTRRWREG 0x138 /* Retry buffer Read/Write */
1911 +#define BCMA_CORE_PCI_DLLP_ECTHRESHREG 0x13C /* Error Count Threshold */
1912 +#define BCMA_CORE_PCI_DLLP_TLPERRCTRREG 0x140 /* TLP Error Counter */
1913 +#define BCMA_CORE_PCI_DLLP_ERRCTRREG 0x144 /* Error Counter */
1914 +#define BCMA_CORE_PCI_DLLP_NAKRXCTRREG 0x148 /* NAK Received Counter */
1915 +#define BCMA_CORE_PCI_DLLP_TESTREG 0x14C /* Test */
1916 +#define BCMA_CORE_PCI_DLLP_PKTBIST 0x150 /* Packet BIST */
1917 +#define BCMA_CORE_PCI_DLLP_PCIE11 0x154 /* DLLP PCIE 1.1 reg */
1919 +/* SERDES RX registers */
1920 +#define BCMA_CORE_PCI_SERDES_RX_CTRL 1 /* Rx cntrl */
1921 +#define BCMA_CORE_PCI_SERDES_RX_CTRL_FORCE 0x80 /* rxpolarity_force */
1922 +#define BCMA_CORE_PCI_SERDES_RX_CTRL_POLARITY 0x40 /* rxpolarity_value */
1923 +#define BCMA_CORE_PCI_SERDES_RX_TIMER1 2 /* Rx Timer1 */
1924 +#define BCMA_CORE_PCI_SERDES_RX_CDR 6 /* CDR */
1925 +#define BCMA_CORE_PCI_SERDES_RX_CDRBW 7 /* CDR BW */
1927 +/* SERDES PLL registers */
1928 +#define BCMA_CORE_PCI_SERDES_PLL_CTRL 1 /* PLL control reg */
1929 +#define BCMA_CORE_PCI_PLL_CTRL_FREQDET_EN 0x4000 /* bit 14 is FREQDET on */
1931 /* PCIcore specific boardflags */
1932 #define BCMA_CORE_PCI_BFL_NOPCI 0x00000400 /* Board leaves PCI floating */
1934 +/* PCIE Config space accessing MACROS */
1935 +#define BCMA_CORE_PCI_CFG_BUS_SHIFT 24 /* Bus shift */
1936 +#define BCMA_CORE_PCI_CFG_SLOT_SHIFT 19 /* Slot/Device shift */
1937 +#define BCMA_CORE_PCI_CFG_FUN_SHIFT 16 /* Function shift */
1938 +#define BCMA_CORE_PCI_CFG_OFF_SHIFT 0 /* Register shift */
1940 +#define BCMA_CORE_PCI_CFG_BUS_MASK 0xff /* Bus mask */
1941 +#define BCMA_CORE_PCI_CFG_SLOT_MASK 0x1f /* Slot/Device mask */
1942 +#define BCMA_CORE_PCI_CFG_FUN_MASK 7 /* Function mask */
1943 +#define BCMA_CORE_PCI_CFG_OFF_MASK 0xfff /* Register mask */
1945 +/* PCIE Root Capability Register bits (Host mode only) */
1946 +#define BCMA_CORE_PCI_RC_CRS_VISIBILITY 0x0001
1948 +struct bcma_drv_pci;
1950 +#ifdef CONFIG_BCMA_DRIVER_PCI_HOSTMODE
1951 +struct bcma_drv_pci_host {
1952 + struct bcma_drv_pci *pdev;
1954 + u32 host_cfg_addr;
1955 + spinlock_t cfgspace_lock;
1957 + struct pci_controller pci_controller;
1958 + struct pci_ops pci_ops;
1959 + struct resource mem_resource;
1960 + struct resource io_resource;
1964 struct bcma_drv_pci {
1965 struct bcma_device *core;
1969 +#ifdef CONFIG_BCMA_DRIVER_PCI_HOSTMODE
1970 + struct bcma_drv_pci_host *host_controller;
1974 /* Register access */
1975 #define pcicore_read32(pc, offset) bcma_read32((pc)->core, offset)
1976 #define pcicore_write32(pc, offset, val) bcma_write32((pc)->core, offset, val)
1978 -extern void bcma_core_pci_init(struct bcma_drv_pci *pc);
1979 +extern void __devinit bcma_core_pci_init(struct bcma_drv_pci *pc);
1980 extern int bcma_core_pci_irq_ctl(struct bcma_drv_pci *pc,
1981 struct bcma_device *core, bool enable);
1983 +extern int bcma_core_pci_pcibios_map_irq(const struct pci_dev *dev);
1984 +extern int bcma_core_pci_plat_dev_init(struct pci_dev *dev);
1986 #endif /* LINUX_BCMA_DRIVER_PCI_H_ */
1987 --- a/include/linux/bcma/bcma_regs.h
1988 +++ b/include/linux/bcma/bcma_regs.h
1990 #define BCMA_PCI_GPIO_XTAL 0x40 /* PCI config space GPIO 14 for Xtal powerup */
1991 #define BCMA_PCI_GPIO_PLL 0x80 /* PCI config space GPIO 15 for PLL powerdown */
1993 +/* SiliconBackplane Address Map.
1994 + * All regions may not exist on all chips.
1996 +#define BCMA_SOC_SDRAM_BASE 0x00000000U /* Physical SDRAM */
1997 +#define BCMA_SOC_PCI_MEM 0x08000000U /* Host Mode sb2pcitranslation0 (64 MB) */
1998 +#define BCMA_SOC_PCI_MEM_SZ (64 * 1024 * 1024)
1999 +#define BCMA_SOC_PCI_CFG 0x0c000000U /* Host Mode sb2pcitranslation1 (64 MB) */
2000 +#define BCMA_SOC_SDRAM_SWAPPED 0x10000000U /* Byteswapped Physical SDRAM */
2001 +#define BCMA_SOC_SDRAM_R2 0x80000000U /* Region 2 for sdram (512 MB) */
2004 +#define BCMA_SOC_PCI_DMA 0x40000000U /* Client Mode sb2pcitranslation2 (1 GB) */
2005 +#define BCMA_SOC_PCI_DMA2 0x80000000U /* Client Mode sb2pcitranslation2 (1 GB) */
2006 +#define BCMA_SOC_PCI_DMA_SZ 0x40000000U /* Client Mode sb2pcitranslation2 size in bytes */
2007 +#define BCMA_SOC_PCIE_DMA_L32 0x00000000U /* PCIE Client Mode sb2pcitranslation2
2008 + * (2 ZettaBytes), low 32 bits
2010 +#define BCMA_SOC_PCIE_DMA_H32 0x80000000U /* PCIE Client Mode sb2pcitranslation2
2011 + * (2 ZettaBytes), high 32 bits
2014 +#define BCMA_SOC_PCI1_MEM 0x40000000U /* Host Mode sb2pcitranslation0 (64 MB) */
2015 +#define BCMA_SOC_PCI1_CFG 0x44000000U /* Host Mode sb2pcitranslation1 (64 MB) */
2016 +#define BCMA_SOC_PCIE1_DMA_H32 0xc0000000U /* PCIE Client Mode sb2pcitranslation2
2017 + * (2 ZettaBytes), high 32 bits
2020 #endif /* LINUX_BCMA_REGS_H_ */