1 --- a/drivers/bcma/Makefile
2 +++ b/drivers/bcma/Makefile
3 @@ -3,6 +3,7 @@ bcma-y += driver_chipcommon.o driver
4 bcma-$(CONFIG_BCMA_SFLASH) += driver_chipcommon_sflash.o
5 bcma-$(CONFIG_BCMA_NFLASH) += driver_chipcommon_nflash.o
7 +bcma-y += driver_pcie2.o
8 bcma-$(CONFIG_BCMA_DRIVER_PCI_HOSTMODE) += driver_pci_host.o
9 bcma-$(CONFIG_BCMA_DRIVER_MIPS) += driver_mips.o
10 bcma-$(CONFIG_BCMA_DRIVER_GMAC_CMN) += driver_gmac_cmn.o
11 --- a/drivers/bcma/driver_chipcommon_pmu.c
12 +++ b/drivers/bcma/driver_chipcommon_pmu.c
13 @@ -603,6 +603,7 @@ void bcma_pmu_spuravoid_pllupdate(struct
14 tmp = BCMA_CC_PMU_CTL_PLL_UPD | BCMA_CC_PMU_CTL_NOILPONW;
17 + case BCMA_CHIP_ID_BCM43217:
18 case BCMA_CHIP_ID_BCM43227:
19 case BCMA_CHIP_ID_BCM43228:
20 case BCMA_CHIP_ID_BCM43428:
21 --- a/drivers/bcma/driver_gpio.c
22 +++ b/drivers/bcma/driver_gpio.c
23 @@ -218,7 +218,15 @@ int bcma_gpio_init(struct bcma_drv_cc *c
24 #if IS_BUILTIN(CONFIG_BCMA_HOST_SOC)
25 chip->to_irq = bcma_gpio_to_irq;
28 + switch (cc->core->bus->chipinfo.id) {
29 + case BCMA_CHIP_ID_BCM5357:
30 + case BCMA_CHIP_ID_BCM53572:
37 /* There is just one SoC in one device and its GPIO addresses should be
38 * deterministic to address them more easily. The other buses could get
39 * a random base number. */
41 +++ b/drivers/bcma/driver_pcie2.c
44 + * Broadcom specific AMBA
47 + * Copyright 2014, Broadcom Corporation
48 + * Copyright 2014, Rafał Miłecki <zajec5@gmail.com>
50 + * Licensed under the GNU/GPL. See COPYING for details.
53 +#include "bcma_private.h"
54 +#include <linux/bcma/bcma.h>
56 +/**************************************************
58 + **************************************************/
61 +static u32 bcma_core_pcie2_cfg_read(struct bcma_drv_pcie2 *pcie2, u32 addr)
63 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, addr);
64 + pcie2_read32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR);
65 + return pcie2_read32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA);
69 +static void bcma_core_pcie2_cfg_write(struct bcma_drv_pcie2 *pcie2, u32 addr,
72 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, addr);
73 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, val);
76 +/**************************************************
78 + **************************************************/
80 +static u32 bcma_core_pcie2_war_delay_perst_enab(struct bcma_drv_pcie2 *pcie2,
85 + /* restore back to default */
86 + val = pcie2_read32(pcie2, BCMA_CORE_PCIE2_CLK_CONTROL);
87 + val |= PCIE2_CLKC_DLYPERST;
88 + val &= ~PCIE2_CLKC_DISSPROMLD;
90 + val &= ~PCIE2_CLKC_DLYPERST;
91 + val |= PCIE2_CLKC_DISSPROMLD;
93 + pcie2_write32(pcie2, (BCMA_CORE_PCIE2_CLK_CONTROL), val);
95 + return pcie2_read32(pcie2, BCMA_CORE_PCIE2_CLK_CONTROL);
98 +static void bcma_core_pcie2_set_ltr_vals(struct bcma_drv_pcie2 *pcie2)
101 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, 0x844);
102 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, 0x883c883c);
104 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, 0x848);
105 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, 0x88648864);
107 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, 0x84C);
108 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, 0x90039003);
111 +static void bcma_core_pcie2_hw_ltr_war(struct bcma_drv_pcie2 *pcie2)
113 + u8 core_rev = pcie2->core->id.rev;
116 + if (core_rev < 2 || core_rev == 10 || core_rev > 13)
119 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR,
120 + PCIE2_CAP_DEVSTSCTRL2_OFFSET);
121 + devstsctr2 = pcie2_read32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA);
122 + if (devstsctr2 & PCIE2_CAP_DEVSTSCTRL2_LTRENAB) {
123 + /* force the right LTR values */
124 + bcma_core_pcie2_set_ltr_vals(pcie2);
127 + si_core_wrapperreg(pcie2, 3, 0x60, 0x8080, 0); */
129 + /* enable the LTR */
130 + devstsctr2 |= PCIE2_CAP_DEVSTSCTRL2_LTRENAB;
131 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR,
132 + PCIE2_CAP_DEVSTSCTRL2_OFFSET);
133 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, devstsctr2);
135 + /* set the LTR state to be active */
136 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_LTR_STATE,
138 + usleep_range(1000, 2000);
140 + /* set the LTR state to be sleep */
141 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_LTR_STATE,
143 + usleep_range(1000, 2000);
147 +static void pciedev_crwlpciegen2(struct bcma_drv_pcie2 *pcie2)
149 + u8 core_rev = pcie2->core->id.rev;
150 + bool pciewar160, pciewar162;
152 + pciewar160 = core_rev == 7 || core_rev == 9 || core_rev == 11;
153 + pciewar162 = core_rev == 5 || core_rev == 7 || core_rev == 8 ||
154 + core_rev == 9 || core_rev == 11;
156 + if (!pciewar160 && !pciewar162)
161 + pcie2_set32(pcie2, BCMA_CORE_PCIE2_CLK_CONTROL,
162 + PCIE_DISABLE_L1CLK_GATING);
164 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR,
165 + PCIEGEN2_COE_PVT_TL_CTRL_0);
166 + pcie2_mask32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA,
167 + ~(1 << COE_PVT_TL_CTRL_0_PM_DIS_L1_REENTRY_BIT));
172 +static void pciedev_crwlpciegen2_180(struct bcma_drv_pcie2 *pcie2)
174 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, PCIE2_PMCR_REFUP);
175 + pcie2_set32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, 0x1f);
178 +static void pciedev_crwlpciegen2_182(struct bcma_drv_pcie2 *pcie2)
180 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, PCIE2_SBMBX);
181 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, 1 << 0);
184 +static void pciedev_reg_pm_clk_period(struct bcma_drv_pcie2 *pcie2)
186 + struct bcma_drv_cc *drv_cc = &pcie2->core->bus->drv_cc;
187 + u8 core_rev = pcie2->core->id.rev;
188 + u32 alp_khz, pm_value;
190 + if (core_rev <= 13) {
191 + alp_khz = bcma_pmu_get_alp_clock(drv_cc) / 1000;
192 + pm_value = (1000000 * 2) / alp_khz;
193 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR,
194 + PCIE2_PVT_REG_PM_CLK_PERIOD);
195 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, pm_value);
199 +void bcma_core_pcie2_init(struct bcma_drv_pcie2 *pcie2)
201 + struct bcma_chipinfo *ci = &pcie2->core->bus->chipinfo;
204 + tmp = pcie2_read32(pcie2, BCMA_CORE_PCIE2_SPROM(54));
205 + if ((tmp & 0xe) >> 1 == 2)
206 + bcma_core_pcie2_cfg_write(pcie2, 0x4e0, 0x17);
208 + /* TODO: Do we need pcie_reqsize? */
210 + if (ci->id == BCMA_CHIP_ID_BCM4360 && ci->rev > 3)
211 + bcma_core_pcie2_war_delay_perst_enab(pcie2, true);
212 + bcma_core_pcie2_hw_ltr_war(pcie2);
213 + pciedev_crwlpciegen2(pcie2);
214 + pciedev_reg_pm_clk_period(pcie2);
215 + pciedev_crwlpciegen2_180(pcie2);
216 + pciedev_crwlpciegen2_182(pcie2);
218 --- a/drivers/bcma/host_pci.c
219 +++ b/drivers/bcma/host_pci.c
220 @@ -279,6 +279,7 @@ static const struct pci_device_id bcma_p
221 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4358) },
222 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4359) },
223 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4365) },
224 + { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x43a9) },
225 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4727) },
228 --- a/drivers/bcma/main.c
229 +++ b/drivers/bcma/main.c
230 @@ -132,6 +132,7 @@ static int bcma_register_cores(struct bc
231 case BCMA_CORE_CHIPCOMMON:
234 + case BCMA_CORE_PCIE2:
235 case BCMA_CORE_MIPS_74K:
236 case BCMA_CORE_4706_MAC_GBIT_COMMON:
238 @@ -281,6 +282,13 @@ int bcma_bus_register(struct bcma_bus *b
239 bcma_core_pci_init(&bus->drv_pci[1]);
242 + /* Init PCIe Gen 2 core */
243 + core = bcma_find_core_unit(bus, BCMA_CORE_PCIE2, 0);
245 + bus->drv_pcie2.core = core;
246 + bcma_core_pcie2_init(&bus->drv_pcie2);
249 /* Init GBIT MAC COMMON core */
250 core = bcma_find_core(bus, BCMA_CORE_4706_MAC_GBIT_COMMON);
252 --- a/drivers/bcma/sprom.c
253 +++ b/drivers/bcma/sprom.c
254 @@ -201,6 +201,23 @@ static int bcma_sprom_valid(struct bcma_
255 SPEX(_field[7], _offset + 14, _mask, _shift); \
258 +static s8 sprom_extract_antgain(const u16 *in, u16 offset, u16 mask, u16 shift)
263 + v = in[SPOFF(offset)];
264 + gain = (v & mask) >> shift;
265 + if (gain == 0xFF) {
266 + gain = 8; /* If unset use 2dBm */
268 + /* Q5.2 Fractional part is stored in 0xC0 */
269 + gain = ((gain & 0xC0) >> 6) | ((gain & 0x3F) << 2);
275 static void bcma_sprom_extract_r8(struct bcma_bus *bus, const u16 *sprom)
278 @@ -381,14 +398,22 @@ static void bcma_sprom_extract_r8(struct
279 SPEX32(ofdm5ghpo, SSB_SPROM8_OFDM5GHPO, ~0, 0);
281 /* Extract the antenna gain values. */
282 - SPEX(antenna_gain.a0, SSB_SPROM8_AGAIN01,
283 - SSB_SPROM8_AGAIN0, SSB_SPROM8_AGAIN0_SHIFT);
284 - SPEX(antenna_gain.a1, SSB_SPROM8_AGAIN01,
285 - SSB_SPROM8_AGAIN1, SSB_SPROM8_AGAIN1_SHIFT);
286 - SPEX(antenna_gain.a2, SSB_SPROM8_AGAIN23,
287 - SSB_SPROM8_AGAIN2, SSB_SPROM8_AGAIN2_SHIFT);
288 - SPEX(antenna_gain.a3, SSB_SPROM8_AGAIN23,
289 - SSB_SPROM8_AGAIN3, SSB_SPROM8_AGAIN3_SHIFT);
290 + bus->sprom.antenna_gain.a0 = sprom_extract_antgain(sprom,
291 + SSB_SPROM8_AGAIN01,
293 + SSB_SPROM8_AGAIN0_SHIFT);
294 + bus->sprom.antenna_gain.a1 = sprom_extract_antgain(sprom,
295 + SSB_SPROM8_AGAIN01,
297 + SSB_SPROM8_AGAIN1_SHIFT);
298 + bus->sprom.antenna_gain.a2 = sprom_extract_antgain(sprom,
299 + SSB_SPROM8_AGAIN23,
301 + SSB_SPROM8_AGAIN2_SHIFT);
302 + bus->sprom.antenna_gain.a3 = sprom_extract_antgain(sprom,
303 + SSB_SPROM8_AGAIN23,
305 + SSB_SPROM8_AGAIN3_SHIFT);
307 SPEX(leddc_on_time, SSB_SPROM8_LEDDC, SSB_SPROM8_LEDDC_ON,
308 SSB_SPROM8_LEDDC_ON_SHIFT);
309 @@ -509,6 +534,7 @@ static bool bcma_sprom_onchip_available(
310 /* for these chips OTP is always available */
313 + case BCMA_CHIP_ID_BCM43217:
314 case BCMA_CHIP_ID_BCM43227:
315 case BCMA_CHIP_ID_BCM43228:
316 case BCMA_CHIP_ID_BCM43428:
317 --- a/include/linux/bcma/bcma.h
318 +++ b/include/linux/bcma/bcma.h
321 #include <linux/bcma/bcma_driver_chipcommon.h>
322 #include <linux/bcma/bcma_driver_pci.h>
323 +#include <linux/bcma/bcma_driver_pcie2.h>
324 #include <linux/bcma/bcma_driver_mips.h>
325 #include <linux/bcma/bcma_driver_gmac_cmn.h>
326 #include <linux/ssb/ssb.h> /* SPROM sharing */
327 @@ -157,6 +158,8 @@ struct bcma_host_ops {
328 /* Chip IDs of PCIe devices */
329 #define BCMA_CHIP_ID_BCM4313 0x4313
330 #define BCMA_CHIP_ID_BCM43142 43142
331 +#define BCMA_CHIP_ID_BCM43217 43217
332 +#define BCMA_CHIP_ID_BCM43222 43222
333 #define BCMA_CHIP_ID_BCM43224 43224
334 #define BCMA_PKG_ID_BCM43224_FAB_CSM 0x8
335 #define BCMA_PKG_ID_BCM43224_FAB_SMIC 0xa
336 @@ -333,6 +336,7 @@ struct bcma_bus {
338 struct bcma_drv_cc drv_cc;
339 struct bcma_drv_pci drv_pci[2];
340 + struct bcma_drv_pcie2 drv_pcie2;
341 struct bcma_drv_mips drv_mips;
342 struct bcma_drv_gmac_cmn drv_gmac_cmn;
345 +++ b/include/linux/bcma/bcma_driver_pcie2.h
347 +#ifndef LINUX_BCMA_DRIVER_PCIE2_H_
348 +#define LINUX_BCMA_DRIVER_PCIE2_H_
350 +#define BCMA_CORE_PCIE2_CLK_CONTROL 0x0000
351 +#define PCIE2_CLKC_RST_OE 0x0001 /* When set, drives PCI_RESET out to pin */
352 +#define PCIE2_CLKC_RST 0x0002 /* Value driven out to pin */
353 +#define PCIE2_CLKC_SPERST 0x0004 /* SurvivePeRst */
354 +#define PCIE2_CLKC_DISABLE_L1CLK_GATING 0x0010
355 +#define PCIE2_CLKC_DLYPERST 0x0100 /* Delay PeRst to CoE Core */
356 +#define PCIE2_CLKC_DISSPROMLD 0x0200 /* DisableSpromLoadOnPerst */
357 +#define PCIE2_CLKC_WAKE_MODE_L2 0x1000 /* Wake on L2 */
358 +#define BCMA_CORE_PCIE2_RC_PM_CONTROL 0x0004
359 +#define BCMA_CORE_PCIE2_RC_PM_STATUS 0x0008
360 +#define BCMA_CORE_PCIE2_EP_PM_CONTROL 0x000C
361 +#define BCMA_CORE_PCIE2_EP_PM_STATUS 0x0010
362 +#define BCMA_CORE_PCIE2_EP_LTR_CONTROL 0x0014
363 +#define BCMA_CORE_PCIE2_EP_LTR_STATUS 0x0018
364 +#define BCMA_CORE_PCIE2_EP_OBFF_STATUS 0x001C
365 +#define BCMA_CORE_PCIE2_PCIE_ERR_STATUS 0x0020
366 +#define BCMA_CORE_PCIE2_RC_AXI_CONFIG 0x0100
367 +#define BCMA_CORE_PCIE2_EP_AXI_CONFIG 0x0104
368 +#define BCMA_CORE_PCIE2_RXDEBUG_STATUS0 0x0108
369 +#define BCMA_CORE_PCIE2_RXDEBUG_CONTROL0 0x010C
370 +#define BCMA_CORE_PCIE2_CONFIGINDADDR 0x0120
371 +#define BCMA_CORE_PCIE2_CONFIGINDDATA 0x0124
372 +#define BCMA_CORE_PCIE2_MDIOCONTROL 0x0128
373 +#define BCMA_CORE_PCIE2_MDIOWRDATA 0x012C
374 +#define BCMA_CORE_PCIE2_MDIORDDATA 0x0130
375 +#define BCMA_CORE_PCIE2_DATAINTF 0x0180
376 +#define BCMA_CORE_PCIE2_D2H_INTRLAZY_0 0x0188
377 +#define BCMA_CORE_PCIE2_H2D_INTRLAZY_0 0x018c
378 +#define BCMA_CORE_PCIE2_H2D_INTSTAT_0 0x0190
379 +#define BCMA_CORE_PCIE2_H2D_INTMASK_0 0x0194
380 +#define BCMA_CORE_PCIE2_D2H_INTSTAT_0 0x0198
381 +#define BCMA_CORE_PCIE2_D2H_INTMASK_0 0x019c
382 +#define BCMA_CORE_PCIE2_LTR_STATE 0x01A0 /* Latency Tolerance Reporting */
383 +#define PCIE2_LTR_ACTIVE 2
384 +#define PCIE2_LTR_ACTIVE_IDLE 1
385 +#define PCIE2_LTR_SLEEP 0
386 +#define PCIE2_LTR_FINAL_MASK 0x300
387 +#define PCIE2_LTR_FINAL_SHIFT 8
388 +#define BCMA_CORE_PCIE2_PWR_INT_STATUS 0x01A4
389 +#define BCMA_CORE_PCIE2_PWR_INT_MASK 0x01A8
390 +#define BCMA_CORE_PCIE2_CFG_ADDR 0x01F8
391 +#define BCMA_CORE_PCIE2_CFG_DATA 0x01FC
392 +#define BCMA_CORE_PCIE2_SYS_EQ_PAGE 0x0200
393 +#define BCMA_CORE_PCIE2_SYS_MSI_PAGE 0x0204
394 +#define BCMA_CORE_PCIE2_SYS_MSI_INTREN 0x0208
395 +#define BCMA_CORE_PCIE2_SYS_MSI_CTRL0 0x0210
396 +#define BCMA_CORE_PCIE2_SYS_MSI_CTRL1 0x0214
397 +#define BCMA_CORE_PCIE2_SYS_MSI_CTRL2 0x0218
398 +#define BCMA_CORE_PCIE2_SYS_MSI_CTRL3 0x021C
399 +#define BCMA_CORE_PCIE2_SYS_MSI_CTRL4 0x0220
400 +#define BCMA_CORE_PCIE2_SYS_MSI_CTRL5 0x0224
401 +#define BCMA_CORE_PCIE2_SYS_EQ_HEAD0 0x0250
402 +#define BCMA_CORE_PCIE2_SYS_EQ_TAIL0 0x0254
403 +#define BCMA_CORE_PCIE2_SYS_EQ_HEAD1 0x0258
404 +#define BCMA_CORE_PCIE2_SYS_EQ_TAIL1 0x025C
405 +#define BCMA_CORE_PCIE2_SYS_EQ_HEAD2 0x0260
406 +#define BCMA_CORE_PCIE2_SYS_EQ_TAIL2 0x0264
407 +#define BCMA_CORE_PCIE2_SYS_EQ_HEAD3 0x0268
408 +#define BCMA_CORE_PCIE2_SYS_EQ_TAIL3 0x026C
409 +#define BCMA_CORE_PCIE2_SYS_EQ_HEAD4 0x0270
410 +#define BCMA_CORE_PCIE2_SYS_EQ_TAIL4 0x0274
411 +#define BCMA_CORE_PCIE2_SYS_EQ_HEAD5 0x0278
412 +#define BCMA_CORE_PCIE2_SYS_EQ_TAIL5 0x027C
413 +#define BCMA_CORE_PCIE2_SYS_RC_INTX_EN 0x0330
414 +#define BCMA_CORE_PCIE2_SYS_RC_INTX_CSR 0x0334
415 +#define BCMA_CORE_PCIE2_SYS_MSI_REQ 0x0340
416 +#define BCMA_CORE_PCIE2_SYS_HOST_INTR_EN 0x0344
417 +#define BCMA_CORE_PCIE2_SYS_HOST_INTR_CSR 0x0348
418 +#define BCMA_CORE_PCIE2_SYS_HOST_INTR0 0x0350
419 +#define BCMA_CORE_PCIE2_SYS_HOST_INTR1 0x0354
420 +#define BCMA_CORE_PCIE2_SYS_HOST_INTR2 0x0358
421 +#define BCMA_CORE_PCIE2_SYS_HOST_INTR3 0x035C
422 +#define BCMA_CORE_PCIE2_SYS_EP_INT_EN0 0x0360
423 +#define BCMA_CORE_PCIE2_SYS_EP_INT_EN1 0x0364
424 +#define BCMA_CORE_PCIE2_SYS_EP_INT_CSR0 0x0370
425 +#define BCMA_CORE_PCIE2_SYS_EP_INT_CSR1 0x0374
426 +#define BCMA_CORE_PCIE2_SPROM(wordoffset) (0x0800 + ((wordoffset) * 2))
427 +#define BCMA_CORE_PCIE2_FUNC0_IMAP0_0 0x0C00
428 +#define BCMA_CORE_PCIE2_FUNC0_IMAP0_1 0x0C04
429 +#define BCMA_CORE_PCIE2_FUNC0_IMAP0_2 0x0C08
430 +#define BCMA_CORE_PCIE2_FUNC0_IMAP0_3 0x0C0C
431 +#define BCMA_CORE_PCIE2_FUNC0_IMAP0_4 0x0C10
432 +#define BCMA_CORE_PCIE2_FUNC0_IMAP0_5 0x0C14
433 +#define BCMA_CORE_PCIE2_FUNC0_IMAP0_6 0x0C18
434 +#define BCMA_CORE_PCIE2_FUNC0_IMAP0_7 0x0C1C
435 +#define BCMA_CORE_PCIE2_FUNC1_IMAP0_0 0x0C20
436 +#define BCMA_CORE_PCIE2_FUNC1_IMAP0_1 0x0C24
437 +#define BCMA_CORE_PCIE2_FUNC1_IMAP0_2 0x0C28
438 +#define BCMA_CORE_PCIE2_FUNC1_IMAP0_3 0x0C2C
439 +#define BCMA_CORE_PCIE2_FUNC1_IMAP0_4 0x0C30
440 +#define BCMA_CORE_PCIE2_FUNC1_IMAP0_5 0x0C34
441 +#define BCMA_CORE_PCIE2_FUNC1_IMAP0_6 0x0C38
442 +#define BCMA_CORE_PCIE2_FUNC1_IMAP0_7 0x0C3C
443 +#define BCMA_CORE_PCIE2_FUNC0_IMAP1 0x0C80
444 +#define BCMA_CORE_PCIE2_FUNC1_IMAP1 0x0C88
445 +#define BCMA_CORE_PCIE2_FUNC0_IMAP2 0x0CC0
446 +#define BCMA_CORE_PCIE2_FUNC1_IMAP2 0x0CC8
447 +#define BCMA_CORE_PCIE2_IARR0_LOWER 0x0D00
448 +#define BCMA_CORE_PCIE2_IARR0_UPPER 0x0D04
449 +#define BCMA_CORE_PCIE2_IARR1_LOWER 0x0D08
450 +#define BCMA_CORE_PCIE2_IARR1_UPPER 0x0D0C
451 +#define BCMA_CORE_PCIE2_IARR2_LOWER 0x0D10
452 +#define BCMA_CORE_PCIE2_IARR2_UPPER 0x0D14
453 +#define BCMA_CORE_PCIE2_OARR0 0x0D20
454 +#define BCMA_CORE_PCIE2_OARR1 0x0D28
455 +#define BCMA_CORE_PCIE2_OARR2 0x0D30
456 +#define BCMA_CORE_PCIE2_OMAP0_LOWER 0x0D40
457 +#define BCMA_CORE_PCIE2_OMAP0_UPPER 0x0D44
458 +#define BCMA_CORE_PCIE2_OMAP1_LOWER 0x0D48
459 +#define BCMA_CORE_PCIE2_OMAP1_UPPER 0x0D4C
460 +#define BCMA_CORE_PCIE2_OMAP2_LOWER 0x0D50
461 +#define BCMA_CORE_PCIE2_OMAP2_UPPER 0x0D54
462 +#define BCMA_CORE_PCIE2_FUNC1_IARR1_SIZE 0x0D58
463 +#define BCMA_CORE_PCIE2_FUNC1_IARR2_SIZE 0x0D5C
464 +#define BCMA_CORE_PCIE2_MEM_CONTROL 0x0F00
465 +#define BCMA_CORE_PCIE2_MEM_ECC_ERRLOG0 0x0F04
466 +#define BCMA_CORE_PCIE2_MEM_ECC_ERRLOG1 0x0F08
467 +#define BCMA_CORE_PCIE2_LINK_STATUS 0x0F0C
468 +#define BCMA_CORE_PCIE2_STRAP_STATUS 0x0F10
469 +#define BCMA_CORE_PCIE2_RESET_STATUS 0x0F14
470 +#define BCMA_CORE_PCIE2_RESETEN_IN_LINKDOWN 0x0F18
471 +#define BCMA_CORE_PCIE2_MISC_INTR_EN 0x0F1C
472 +#define BCMA_CORE_PCIE2_TX_DEBUG_CFG 0x0F20
473 +#define BCMA_CORE_PCIE2_MISC_CONFIG 0x0F24
474 +#define BCMA_CORE_PCIE2_MISC_STATUS 0x0F28
475 +#define BCMA_CORE_PCIE2_INTR_EN 0x0F30
476 +#define BCMA_CORE_PCIE2_INTR_CLEAR 0x0F34
477 +#define BCMA_CORE_PCIE2_INTR_STATUS 0x0F38
479 +/* PCIE gen2 config regs */
480 +#define PCIE2_INTSTATUS 0x090
481 +#define PCIE2_INTMASK 0x094
482 +#define PCIE2_SBMBX 0x098
484 +#define PCIE2_PMCR_REFUP 0x1814 /* Trefup time */
486 +#define PCIE2_CAP_DEVSTSCTRL2_OFFSET 0xD4
487 +#define PCIE2_CAP_DEVSTSCTRL2_LTRENAB 0x400
488 +#define PCIE2_PVT_REG_PM_CLK_PERIOD 0x184c
490 +struct bcma_drv_pcie2 {
491 + struct bcma_device *core;
494 +#define pcie2_read16(pcie2, offset) bcma_read16((pcie2)->core, offset)
495 +#define pcie2_read32(pcie2, offset) bcma_read32((pcie2)->core, offset)
496 +#define pcie2_write16(pcie2, offset, val) bcma_write16((pcie2)->core, offset, val)
497 +#define pcie2_write32(pcie2, offset, val) bcma_write32((pcie2)->core, offset, val)
499 +#define pcie2_set32(pcie2, offset, set) bcma_set32((pcie2)->core, offset, set)
500 +#define pcie2_mask32(pcie2, offset, mask) bcma_mask32((pcie2)->core, offset, mask)
502 +void bcma_core_pcie2_init(struct bcma_drv_pcie2 *pcie2);
504 +#endif /* LINUX_BCMA_DRIVER_PCIE2_H_ */