1 --- a/drivers/bcma/Makefile
2 +++ b/drivers/bcma/Makefile
4 bcma-y += main.o scan.o core.o sprom.o
5 bcma-y += driver_chipcommon.o driver_chipcommon_pmu.o
6 +bcma-y += driver_chipcommon_b.o
7 bcma-$(CONFIG_BCMA_SFLASH) += driver_chipcommon_sflash.o
8 bcma-$(CONFIG_BCMA_NFLASH) += driver_chipcommon_nflash.o
10 +bcma-y += driver_pcie2.o
11 bcma-$(CONFIG_BCMA_DRIVER_PCI_HOSTMODE) += driver_pci_host.o
12 bcma-$(CONFIG_BCMA_DRIVER_MIPS) += driver_mips.o
13 bcma-$(CONFIG_BCMA_DRIVER_GMAC_CMN) += driver_gmac_cmn.o
14 --- a/drivers/bcma/driver_chipcommon_pmu.c
15 +++ b/drivers/bcma/driver_chipcommon_pmu.c
16 @@ -603,6 +603,8 @@ void bcma_pmu_spuravoid_pllupdate(struct
17 tmp = BCMA_CC_PMU_CTL_PLL_UPD | BCMA_CC_PMU_CTL_NOILPONW;
20 + case BCMA_CHIP_ID_BCM43131:
21 + case BCMA_CHIP_ID_BCM43217:
22 case BCMA_CHIP_ID_BCM43227:
23 case BCMA_CHIP_ID_BCM43228:
24 case BCMA_CHIP_ID_BCM43428:
25 --- a/drivers/bcma/driver_gpio.c
26 +++ b/drivers/bcma/driver_gpio.c
27 @@ -76,7 +76,7 @@ static void bcma_gpio_free(struct gpio_c
28 bcma_chipco_gpio_pullup(cc, 1 << gpio, 0);
31 -#if IS_BUILTIN(CONFIG_BCMA_HOST_SOC)
32 +#if IS_BUILTIN(CONFIG_BCM47XX)
33 static int bcma_gpio_to_irq(struct gpio_chip *chip, unsigned gpio)
35 struct bcma_drv_cc *cc = bcma_gpio_get_cc(chip);
36 @@ -215,10 +215,22 @@ int bcma_gpio_init(struct bcma_drv_cc *c
37 chip->set = bcma_gpio_set_value;
38 chip->direction_input = bcma_gpio_direction_input;
39 chip->direction_output = bcma_gpio_direction_output;
40 -#if IS_BUILTIN(CONFIG_BCMA_HOST_SOC)
41 +#if IS_BUILTIN(CONFIG_BCM47XX)
42 chip->to_irq = bcma_gpio_to_irq;
45 +#if IS_BUILTIN(CONFIG_OF)
46 + if (cc->core->bus->hosttype == BCMA_HOSTTYPE_SOC)
47 + chip->of_node = cc->core->dev.of_node;
49 + switch (cc->core->bus->chipinfo.id) {
50 + case BCMA_CHIP_ID_BCM5357:
51 + case BCMA_CHIP_ID_BCM53572:
58 /* There is just one SoC in one device and its GPIO addresses should be
59 * deterministic to address them more easily. The other buses could get
60 * a random base number. */
62 +++ b/drivers/bcma/driver_pcie2.c
65 + * Broadcom specific AMBA
68 + * Copyright 2014, Broadcom Corporation
69 + * Copyright 2014, Rafał Miłecki <zajec5@gmail.com>
71 + * Licensed under the GNU/GPL. See COPYING for details.
74 +#include "bcma_private.h"
75 +#include <linux/bcma/bcma.h>
77 +/**************************************************
79 + **************************************************/
82 +static u32 bcma_core_pcie2_cfg_read(struct bcma_drv_pcie2 *pcie2, u32 addr)
84 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, addr);
85 + pcie2_read32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR);
86 + return pcie2_read32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA);
90 +static void bcma_core_pcie2_cfg_write(struct bcma_drv_pcie2 *pcie2, u32 addr,
93 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, addr);
94 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, val);
97 +/**************************************************
99 + **************************************************/
101 +static u32 bcma_core_pcie2_war_delay_perst_enab(struct bcma_drv_pcie2 *pcie2,
106 + /* restore back to default */
107 + val = pcie2_read32(pcie2, BCMA_CORE_PCIE2_CLK_CONTROL);
108 + val |= PCIE2_CLKC_DLYPERST;
109 + val &= ~PCIE2_CLKC_DISSPROMLD;
111 + val &= ~PCIE2_CLKC_DLYPERST;
112 + val |= PCIE2_CLKC_DISSPROMLD;
114 + pcie2_write32(pcie2, (BCMA_CORE_PCIE2_CLK_CONTROL), val);
116 + return pcie2_read32(pcie2, BCMA_CORE_PCIE2_CLK_CONTROL);
119 +static void bcma_core_pcie2_set_ltr_vals(struct bcma_drv_pcie2 *pcie2)
122 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, 0x844);
123 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, 0x883c883c);
125 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, 0x848);
126 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, 0x88648864);
128 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, 0x84C);
129 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, 0x90039003);
132 +static void bcma_core_pcie2_hw_ltr_war(struct bcma_drv_pcie2 *pcie2)
134 + u8 core_rev = pcie2->core->id.rev;
137 + if (core_rev < 2 || core_rev == 10 || core_rev > 13)
140 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR,
141 + PCIE2_CAP_DEVSTSCTRL2_OFFSET);
142 + devstsctr2 = pcie2_read32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA);
143 + if (devstsctr2 & PCIE2_CAP_DEVSTSCTRL2_LTRENAB) {
144 + /* force the right LTR values */
145 + bcma_core_pcie2_set_ltr_vals(pcie2);
148 + si_core_wrapperreg(pcie2, 3, 0x60, 0x8080, 0); */
150 + /* enable the LTR */
151 + devstsctr2 |= PCIE2_CAP_DEVSTSCTRL2_LTRENAB;
152 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR,
153 + PCIE2_CAP_DEVSTSCTRL2_OFFSET);
154 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, devstsctr2);
156 + /* set the LTR state to be active */
157 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_LTR_STATE,
159 + usleep_range(1000, 2000);
161 + /* set the LTR state to be sleep */
162 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_LTR_STATE,
164 + usleep_range(1000, 2000);
168 +static void pciedev_crwlpciegen2(struct bcma_drv_pcie2 *pcie2)
170 + u8 core_rev = pcie2->core->id.rev;
171 + bool pciewar160, pciewar162;
173 + pciewar160 = core_rev == 7 || core_rev == 9 || core_rev == 11;
174 + pciewar162 = core_rev == 5 || core_rev == 7 || core_rev == 8 ||
175 + core_rev == 9 || core_rev == 11;
177 + if (!pciewar160 && !pciewar162)
182 + pcie2_set32(pcie2, BCMA_CORE_PCIE2_CLK_CONTROL,
183 + PCIE_DISABLE_L1CLK_GATING);
185 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR,
186 + PCIEGEN2_COE_PVT_TL_CTRL_0);
187 + pcie2_mask32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA,
188 + ~(1 << COE_PVT_TL_CTRL_0_PM_DIS_L1_REENTRY_BIT));
193 +static void pciedev_crwlpciegen2_180(struct bcma_drv_pcie2 *pcie2)
195 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, PCIE2_PMCR_REFUP);
196 + pcie2_set32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, 0x1f);
199 +static void pciedev_crwlpciegen2_182(struct bcma_drv_pcie2 *pcie2)
201 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, PCIE2_SBMBX);
202 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, 1 << 0);
205 +static void pciedev_reg_pm_clk_period(struct bcma_drv_pcie2 *pcie2)
207 + struct bcma_drv_cc *drv_cc = &pcie2->core->bus->drv_cc;
208 + u8 core_rev = pcie2->core->id.rev;
209 + u32 alp_khz, pm_value;
211 + if (core_rev <= 13) {
212 + alp_khz = bcma_pmu_get_alp_clock(drv_cc) / 1000;
213 + pm_value = (1000000 * 2) / alp_khz;
214 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR,
215 + PCIE2_PVT_REG_PM_CLK_PERIOD);
216 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, pm_value);
220 +void bcma_core_pcie2_init(struct bcma_drv_pcie2 *pcie2)
222 + struct bcma_chipinfo *ci = &pcie2->core->bus->chipinfo;
225 + tmp = pcie2_read32(pcie2, BCMA_CORE_PCIE2_SPROM(54));
226 + if ((tmp & 0xe) >> 1 == 2)
227 + bcma_core_pcie2_cfg_write(pcie2, 0x4e0, 0x17);
229 + /* TODO: Do we need pcie_reqsize? */
231 + if (ci->id == BCMA_CHIP_ID_BCM4360 && ci->rev > 3)
232 + bcma_core_pcie2_war_delay_perst_enab(pcie2, true);
233 + bcma_core_pcie2_hw_ltr_war(pcie2);
234 + pciedev_crwlpciegen2(pcie2);
235 + pciedev_reg_pm_clk_period(pcie2);
236 + pciedev_crwlpciegen2_180(pcie2);
237 + pciedev_crwlpciegen2_182(pcie2);
239 --- a/drivers/bcma/host_pci.c
240 +++ b/drivers/bcma/host_pci.c
241 @@ -208,6 +208,9 @@ static int bcma_host_pci_probe(struct pc
242 bus->boardinfo.vendor = bus->host_pci->subsystem_vendor;
243 bus->boardinfo.type = bus->host_pci->subsystem_device;
245 + /* Initialize struct, detect chip */
246 + bcma_init_bus(bus);
249 err = bcma_bus_register(bus);
251 @@ -279,7 +282,10 @@ static const struct pci_device_id bcma_p
252 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4358) },
253 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4359) },
254 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4365) },
255 + { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x43a9) },
256 + { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x43aa) },
257 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4727) },
258 + { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 43227) }, /* 0xA8DB */
261 MODULE_DEVICE_TABLE(pci, bcma_pci_bridge_tbl);
262 --- a/drivers/bcma/main.c
263 +++ b/drivers/bcma/main.c
265 #include <linux/platform_device.h>
266 #include <linux/bcma/bcma.h>
267 #include <linux/slab.h>
268 +#include <linux/of_address.h>
270 MODULE_DESCRIPTION("Broadcom's specific AMBA driver");
271 MODULE_LICENSE("GPL");
272 @@ -120,56 +121,121 @@ static void bcma_release_core_dev(struct
276 -static int bcma_register_cores(struct bcma_bus *bus)
277 +static bool bcma_is_core_needed_early(u16 core_id)
280 + case BCMA_CORE_NS_NAND:
281 + case BCMA_CORE_NS_QSPI:
289 +static struct device_node *bcma_of_find_child_device(struct platform_device *parent,
290 + struct bcma_device *core)
292 + struct device_node *node;
296 + if (!parent || !parent->dev.of_node)
299 + for_each_child_of_node(parent->dev.of_node, node) {
300 + reg = of_get_address(node, 0, &size, NULL);
303 + if (of_translate_address(node, reg) == core->addr)
309 +static void bcma_of_fill_device(struct platform_device *parent,
310 + struct bcma_device *core)
312 + struct device_node *node;
314 + node = bcma_of_find_child_device(parent, core);
316 + core->dev.of_node = node;
319 +static void bcma_of_fill_device(struct platform_device *parent,
320 + struct bcma_device *core)
323 +#endif /* CONFIG_OF */
325 +static void bcma_register_core(struct bcma_bus *bus, struct bcma_device *core)
329 + core->dev.release = bcma_release_core_dev;
330 + core->dev.bus = &bcma_bus_type;
331 + dev_set_name(&core->dev, "bcma%d:%d", bus->num, core->core_index);
333 + switch (bus->hosttype) {
334 + case BCMA_HOSTTYPE_PCI:
335 + core->dev.parent = &bus->host_pci->dev;
336 + core->dma_dev = &bus->host_pci->dev;
337 + core->irq = bus->host_pci->irq;
339 + case BCMA_HOSTTYPE_SOC:
340 + core->dev.dma_mask = &core->dev.coherent_dma_mask;
341 + if (bus->host_pdev) {
342 + core->dma_dev = &bus->host_pdev->dev;
343 + core->dev.parent = &bus->host_pdev->dev;
344 + bcma_of_fill_device(bus->host_pdev, core);
346 + core->dma_dev = &core->dev;
349 + case BCMA_HOSTTYPE_SDIO:
353 + err = device_register(&core->dev);
355 + bcma_err(bus, "Could not register dev for core 0x%03X\n",
357 + put_device(&core->dev);
360 + core->dev_registered = true;
363 +static int bcma_register_devices(struct bcma_bus *bus)
365 struct bcma_device *core;
366 - int err, dev_id = 0;
369 list_for_each_entry(core, &bus->cores, list) {
370 /* We support that cores ourself */
371 switch (core->id.id) {
372 case BCMA_CORE_4706_CHIPCOMMON:
373 case BCMA_CORE_CHIPCOMMON:
374 + case BCMA_CORE_NS_CHIPCOMMON_B:
377 + case BCMA_CORE_PCIE2:
378 case BCMA_CORE_MIPS_74K:
379 case BCMA_CORE_4706_MAC_GBIT_COMMON:
383 + /* Early cores were already registered */
384 + if (bcma_is_core_needed_early(core->id.id))
387 /* Only first GMAC core on BCM4706 is connected and working */
388 if (core->id.id == BCMA_CORE_4706_MAC_GBIT &&
392 - core->dev.release = bcma_release_core_dev;
393 - core->dev.bus = &bcma_bus_type;
394 - dev_set_name(&core->dev, "bcma%d:%d", bus->num, dev_id);
396 - switch (bus->hosttype) {
397 - case BCMA_HOSTTYPE_PCI:
398 - core->dev.parent = &bus->host_pci->dev;
399 - core->dma_dev = &bus->host_pci->dev;
400 - core->irq = bus->host_pci->irq;
402 - case BCMA_HOSTTYPE_SOC:
403 - core->dev.dma_mask = &core->dev.coherent_dma_mask;
404 - core->dma_dev = &core->dev;
406 - case BCMA_HOSTTYPE_SDIO:
410 - err = device_register(&core->dev);
413 - "Could not register dev for core 0x%03X\n",
415 - put_device(&core->dev);
418 - core->dev_registered = true;
420 + bcma_register_core(bus, core);
423 #ifdef CONFIG_BCMA_DRIVER_MIPS
424 @@ -246,6 +312,12 @@ int bcma_bus_register(struct bcma_bus *b
425 bcma_core_chipcommon_early_init(&bus->drv_cc);
428 + /* Cores providing flash access go before SPROM init */
429 + list_for_each_entry(core, &bus->cores, list) {
430 + if (bcma_is_core_needed_early(core->id.id))
431 + bcma_register_core(bus, core);
434 /* Try to get SPROM */
435 err = bcma_sprom_get(bus);
436 if (err == -ENOENT) {
437 @@ -260,6 +332,13 @@ int bcma_bus_register(struct bcma_bus *b
438 bcma_core_chipcommon_init(&bus->drv_cc);
442 + core = bcma_find_core(bus, BCMA_CORE_NS_CHIPCOMMON_B);
444 + bus->drv_cc_b.core = core;
445 + bcma_core_chipcommon_b_init(&bus->drv_cc_b);
449 core = bcma_find_core(bus, BCMA_CORE_MIPS_74K);
451 @@ -281,6 +360,13 @@ int bcma_bus_register(struct bcma_bus *b
452 bcma_core_pci_init(&bus->drv_pci[1]);
455 + /* Init PCIe Gen 2 core */
456 + core = bcma_find_core_unit(bus, BCMA_CORE_PCIE2, 0);
458 + bus->drv_pcie2.core = core;
459 + bcma_core_pcie2_init(&bus->drv_pcie2);
462 /* Init GBIT MAC COMMON core */
463 core = bcma_find_core(bus, BCMA_CORE_4706_MAC_GBIT_COMMON);
465 @@ -289,7 +375,7 @@ int bcma_bus_register(struct bcma_bus *b
468 /* Register found cores */
469 - bcma_register_cores(bus);
470 + bcma_register_devices(bus);
472 bcma_info(bus, "Bus registered\n");
474 @@ -307,6 +393,8 @@ void bcma_bus_unregister(struct bcma_bus
476 bcma_err(bus, "Can not unregister GPIO driver: %i\n", err);
478 + bcma_core_chipcommon_b_free(&bus->drv_cc_b);
480 cores[0] = bcma_find_core(bus, BCMA_CORE_MIPS_74K);
481 cores[1] = bcma_find_core(bus, BCMA_CORE_PCIE);
482 cores[2] = bcma_find_core(bus, BCMA_CORE_4706_MAC_GBIT_COMMON);
483 @@ -326,8 +414,6 @@ int __init bcma_bus_early_register(struc
484 struct bcma_device *core;
485 struct bcma_device_id match;
487 - bcma_init_bus(bus);
489 match.manuf = BCMA_MANUF_BCM;
490 match.id = bcma_cc_core_id(bus);
491 match.class = BCMA_CL_SIM;
492 @@ -486,6 +572,11 @@ static int __init bcma_modinit(void)
496 + err = bcma_host_soc_register_driver();
498 + pr_err("SoC host initialization failed\n");
501 #ifdef CONFIG_BCMA_HOST_PCI
502 err = bcma_host_pci_init();
504 @@ -503,6 +594,7 @@ static void __exit bcma_modexit(void)
505 #ifdef CONFIG_BCMA_HOST_PCI
506 bcma_host_pci_exit();
508 + bcma_host_soc_unregister_driver();
509 bus_unregister(&bcma_bus_type);
511 module_exit(bcma_modexit)
512 --- a/drivers/bcma/sprom.c
513 +++ b/drivers/bcma/sprom.c
514 @@ -201,6 +201,23 @@ static int bcma_sprom_valid(struct bcma_
515 SPEX(_field[7], _offset + 14, _mask, _shift); \
518 +static s8 sprom_extract_antgain(const u16 *in, u16 offset, u16 mask, u16 shift)
523 + v = in[SPOFF(offset)];
524 + gain = (v & mask) >> shift;
525 + if (gain == 0xFF) {
526 + gain = 8; /* If unset use 2dBm */
528 + /* Q5.2 Fractional part is stored in 0xC0 */
529 + gain = ((gain & 0xC0) >> 6) | ((gain & 0x3F) << 2);
535 static void bcma_sprom_extract_r8(struct bcma_bus *bus, const u16 *sprom)
538 @@ -381,14 +398,22 @@ static void bcma_sprom_extract_r8(struct
539 SPEX32(ofdm5ghpo, SSB_SPROM8_OFDM5GHPO, ~0, 0);
541 /* Extract the antenna gain values. */
542 - SPEX(antenna_gain.a0, SSB_SPROM8_AGAIN01,
543 - SSB_SPROM8_AGAIN0, SSB_SPROM8_AGAIN0_SHIFT);
544 - SPEX(antenna_gain.a1, SSB_SPROM8_AGAIN01,
545 - SSB_SPROM8_AGAIN1, SSB_SPROM8_AGAIN1_SHIFT);
546 - SPEX(antenna_gain.a2, SSB_SPROM8_AGAIN23,
547 - SSB_SPROM8_AGAIN2, SSB_SPROM8_AGAIN2_SHIFT);
548 - SPEX(antenna_gain.a3, SSB_SPROM8_AGAIN23,
549 - SSB_SPROM8_AGAIN3, SSB_SPROM8_AGAIN3_SHIFT);
550 + bus->sprom.antenna_gain.a0 = sprom_extract_antgain(sprom,
551 + SSB_SPROM8_AGAIN01,
553 + SSB_SPROM8_AGAIN0_SHIFT);
554 + bus->sprom.antenna_gain.a1 = sprom_extract_antgain(sprom,
555 + SSB_SPROM8_AGAIN01,
557 + SSB_SPROM8_AGAIN1_SHIFT);
558 + bus->sprom.antenna_gain.a2 = sprom_extract_antgain(sprom,
559 + SSB_SPROM8_AGAIN23,
561 + SSB_SPROM8_AGAIN2_SHIFT);
562 + bus->sprom.antenna_gain.a3 = sprom_extract_antgain(sprom,
563 + SSB_SPROM8_AGAIN23,
565 + SSB_SPROM8_AGAIN3_SHIFT);
567 SPEX(leddc_on_time, SSB_SPROM8_LEDDC, SSB_SPROM8_LEDDC_ON,
568 SSB_SPROM8_LEDDC_ON_SHIFT);
569 @@ -509,6 +534,8 @@ static bool bcma_sprom_onchip_available(
570 /* for these chips OTP is always available */
573 + case BCMA_CHIP_ID_BCM43131:
574 + case BCMA_CHIP_ID_BCM43217:
575 case BCMA_CHIP_ID_BCM43227:
576 case BCMA_CHIP_ID_BCM43228:
577 case BCMA_CHIP_ID_BCM43428:
578 --- a/include/linux/bcma/bcma.h
579 +++ b/include/linux/bcma/bcma.h
582 #include <linux/bcma/bcma_driver_chipcommon.h>
583 #include <linux/bcma/bcma_driver_pci.h>
584 +#include <linux/bcma/bcma_driver_pcie2.h>
585 #include <linux/bcma/bcma_driver_mips.h>
586 #include <linux/bcma/bcma_driver_gmac_cmn.h>
587 #include <linux/ssb/ssb.h> /* SPROM sharing */
588 @@ -72,17 +73,17 @@ struct bcma_host_ops {
589 /* Core-ID values. */
590 #define BCMA_CORE_OOB_ROUTER 0x367 /* Out of band */
591 #define BCMA_CORE_4706_CHIPCOMMON 0x500
592 -#define BCMA_CORE_PCIEG2 0x501
593 -#define BCMA_CORE_DMA 0x502
594 -#define BCMA_CORE_SDIO3 0x503
595 -#define BCMA_CORE_USB20 0x504
596 -#define BCMA_CORE_USB30 0x505
597 -#define BCMA_CORE_A9JTAG 0x506
598 -#define BCMA_CORE_DDR23 0x507
599 -#define BCMA_CORE_ROM 0x508
600 -#define BCMA_CORE_NAND 0x509
601 -#define BCMA_CORE_QSPI 0x50A
602 -#define BCMA_CORE_CHIPCOMMON_B 0x50B
603 +#define BCMA_CORE_NS_PCIEG2 0x501
604 +#define BCMA_CORE_NS_DMA 0x502
605 +#define BCMA_CORE_NS_SDIO3 0x503
606 +#define BCMA_CORE_NS_USB20 0x504
607 +#define BCMA_CORE_NS_USB30 0x505
608 +#define BCMA_CORE_NS_A9JTAG 0x506
609 +#define BCMA_CORE_NS_DDR23 0x507
610 +#define BCMA_CORE_NS_ROM 0x508
611 +#define BCMA_CORE_NS_NAND 0x509
612 +#define BCMA_CORE_NS_QSPI 0x50A
613 +#define BCMA_CORE_NS_CHIPCOMMON_B 0x50B
614 #define BCMA_CORE_4706_SOC_RAM 0x50E
615 #define BCMA_CORE_ARMCA9 0x510
616 #define BCMA_CORE_4706_MAC_GBIT 0x52D
617 @@ -157,6 +158,9 @@ struct bcma_host_ops {
618 /* Chip IDs of PCIe devices */
619 #define BCMA_CHIP_ID_BCM4313 0x4313
620 #define BCMA_CHIP_ID_BCM43142 43142
621 +#define BCMA_CHIP_ID_BCM43131 43131
622 +#define BCMA_CHIP_ID_BCM43217 43217
623 +#define BCMA_CHIP_ID_BCM43222 43222
624 #define BCMA_CHIP_ID_BCM43224 43224
625 #define BCMA_PKG_ID_BCM43224_FAB_CSM 0x8
626 #define BCMA_PKG_ID_BCM43224_FAB_SMIC 0xa
627 @@ -263,7 +267,7 @@ struct bcma_device {
635 void __iomem *io_addr;
636 @@ -319,6 +323,8 @@ struct bcma_bus {
637 struct pci_dev *host_pci;
638 /* Pointer to the SDIO device (only for BCMA_HOSTTYPE_SDIO) */
639 struct sdio_func *host_sdio;
640 + /* Pointer to platform device (only for BCMA_HOSTTYPE_SOC) */
641 + struct platform_device *host_pdev;
644 struct bcma_chipinfo chipinfo;
645 @@ -328,11 +334,12 @@ struct bcma_bus {
646 struct bcma_device *mapped_core;
647 struct list_head cores;
652 struct bcma_drv_cc drv_cc;
653 + struct bcma_drv_cc_b drv_cc_b;
654 struct bcma_drv_pci drv_pci[2];
655 + struct bcma_drv_pcie2 drv_pcie2;
656 struct bcma_drv_mips drv_mips;
657 struct bcma_drv_gmac_cmn drv_gmac_cmn;
660 +++ b/include/linux/bcma/bcma_driver_pcie2.h
662 +#ifndef LINUX_BCMA_DRIVER_PCIE2_H_
663 +#define LINUX_BCMA_DRIVER_PCIE2_H_
665 +#define BCMA_CORE_PCIE2_CLK_CONTROL 0x0000
666 +#define PCIE2_CLKC_RST_OE 0x0001 /* When set, drives PCI_RESET out to pin */
667 +#define PCIE2_CLKC_RST 0x0002 /* Value driven out to pin */
668 +#define PCIE2_CLKC_SPERST 0x0004 /* SurvivePeRst */
669 +#define PCIE2_CLKC_DISABLE_L1CLK_GATING 0x0010
670 +#define PCIE2_CLKC_DLYPERST 0x0100 /* Delay PeRst to CoE Core */
671 +#define PCIE2_CLKC_DISSPROMLD 0x0200 /* DisableSpromLoadOnPerst */
672 +#define PCIE2_CLKC_WAKE_MODE_L2 0x1000 /* Wake on L2 */
673 +#define BCMA_CORE_PCIE2_RC_PM_CONTROL 0x0004
674 +#define BCMA_CORE_PCIE2_RC_PM_STATUS 0x0008
675 +#define BCMA_CORE_PCIE2_EP_PM_CONTROL 0x000C
676 +#define BCMA_CORE_PCIE2_EP_PM_STATUS 0x0010
677 +#define BCMA_CORE_PCIE2_EP_LTR_CONTROL 0x0014
678 +#define BCMA_CORE_PCIE2_EP_LTR_STATUS 0x0018
679 +#define BCMA_CORE_PCIE2_EP_OBFF_STATUS 0x001C
680 +#define BCMA_CORE_PCIE2_PCIE_ERR_STATUS 0x0020
681 +#define BCMA_CORE_PCIE2_RC_AXI_CONFIG 0x0100
682 +#define BCMA_CORE_PCIE2_EP_AXI_CONFIG 0x0104
683 +#define BCMA_CORE_PCIE2_RXDEBUG_STATUS0 0x0108
684 +#define BCMA_CORE_PCIE2_RXDEBUG_CONTROL0 0x010C
685 +#define BCMA_CORE_PCIE2_CONFIGINDADDR 0x0120
686 +#define BCMA_CORE_PCIE2_CONFIGINDDATA 0x0124
687 +#define BCMA_CORE_PCIE2_MDIOCONTROL 0x0128
688 +#define BCMA_CORE_PCIE2_MDIOWRDATA 0x012C
689 +#define BCMA_CORE_PCIE2_MDIORDDATA 0x0130
690 +#define BCMA_CORE_PCIE2_DATAINTF 0x0180
691 +#define BCMA_CORE_PCIE2_D2H_INTRLAZY_0 0x0188
692 +#define BCMA_CORE_PCIE2_H2D_INTRLAZY_0 0x018c
693 +#define BCMA_CORE_PCIE2_H2D_INTSTAT_0 0x0190
694 +#define BCMA_CORE_PCIE2_H2D_INTMASK_0 0x0194
695 +#define BCMA_CORE_PCIE2_D2H_INTSTAT_0 0x0198
696 +#define BCMA_CORE_PCIE2_D2H_INTMASK_0 0x019c
697 +#define BCMA_CORE_PCIE2_LTR_STATE 0x01A0 /* Latency Tolerance Reporting */
698 +#define PCIE2_LTR_ACTIVE 2
699 +#define PCIE2_LTR_ACTIVE_IDLE 1
700 +#define PCIE2_LTR_SLEEP 0
701 +#define PCIE2_LTR_FINAL_MASK 0x300
702 +#define PCIE2_LTR_FINAL_SHIFT 8
703 +#define BCMA_CORE_PCIE2_PWR_INT_STATUS 0x01A4
704 +#define BCMA_CORE_PCIE2_PWR_INT_MASK 0x01A8
705 +#define BCMA_CORE_PCIE2_CFG_ADDR 0x01F8
706 +#define BCMA_CORE_PCIE2_CFG_DATA 0x01FC
707 +#define BCMA_CORE_PCIE2_SYS_EQ_PAGE 0x0200
708 +#define BCMA_CORE_PCIE2_SYS_MSI_PAGE 0x0204
709 +#define BCMA_CORE_PCIE2_SYS_MSI_INTREN 0x0208
710 +#define BCMA_CORE_PCIE2_SYS_MSI_CTRL0 0x0210
711 +#define BCMA_CORE_PCIE2_SYS_MSI_CTRL1 0x0214
712 +#define BCMA_CORE_PCIE2_SYS_MSI_CTRL2 0x0218
713 +#define BCMA_CORE_PCIE2_SYS_MSI_CTRL3 0x021C
714 +#define BCMA_CORE_PCIE2_SYS_MSI_CTRL4 0x0220
715 +#define BCMA_CORE_PCIE2_SYS_MSI_CTRL5 0x0224
716 +#define BCMA_CORE_PCIE2_SYS_EQ_HEAD0 0x0250
717 +#define BCMA_CORE_PCIE2_SYS_EQ_TAIL0 0x0254
718 +#define BCMA_CORE_PCIE2_SYS_EQ_HEAD1 0x0258
719 +#define BCMA_CORE_PCIE2_SYS_EQ_TAIL1 0x025C
720 +#define BCMA_CORE_PCIE2_SYS_EQ_HEAD2 0x0260
721 +#define BCMA_CORE_PCIE2_SYS_EQ_TAIL2 0x0264
722 +#define BCMA_CORE_PCIE2_SYS_EQ_HEAD3 0x0268
723 +#define BCMA_CORE_PCIE2_SYS_EQ_TAIL3 0x026C
724 +#define BCMA_CORE_PCIE2_SYS_EQ_HEAD4 0x0270
725 +#define BCMA_CORE_PCIE2_SYS_EQ_TAIL4 0x0274
726 +#define BCMA_CORE_PCIE2_SYS_EQ_HEAD5 0x0278
727 +#define BCMA_CORE_PCIE2_SYS_EQ_TAIL5 0x027C
728 +#define BCMA_CORE_PCIE2_SYS_RC_INTX_EN 0x0330
729 +#define BCMA_CORE_PCIE2_SYS_RC_INTX_CSR 0x0334
730 +#define BCMA_CORE_PCIE2_SYS_MSI_REQ 0x0340
731 +#define BCMA_CORE_PCIE2_SYS_HOST_INTR_EN 0x0344
732 +#define BCMA_CORE_PCIE2_SYS_HOST_INTR_CSR 0x0348
733 +#define BCMA_CORE_PCIE2_SYS_HOST_INTR0 0x0350
734 +#define BCMA_CORE_PCIE2_SYS_HOST_INTR1 0x0354
735 +#define BCMA_CORE_PCIE2_SYS_HOST_INTR2 0x0358
736 +#define BCMA_CORE_PCIE2_SYS_HOST_INTR3 0x035C
737 +#define BCMA_CORE_PCIE2_SYS_EP_INT_EN0 0x0360
738 +#define BCMA_CORE_PCIE2_SYS_EP_INT_EN1 0x0364
739 +#define BCMA_CORE_PCIE2_SYS_EP_INT_CSR0 0x0370
740 +#define BCMA_CORE_PCIE2_SYS_EP_INT_CSR1 0x0374
741 +#define BCMA_CORE_PCIE2_SPROM(wordoffset) (0x0800 + ((wordoffset) * 2))
742 +#define BCMA_CORE_PCIE2_FUNC0_IMAP0_0 0x0C00
743 +#define BCMA_CORE_PCIE2_FUNC0_IMAP0_1 0x0C04
744 +#define BCMA_CORE_PCIE2_FUNC0_IMAP0_2 0x0C08
745 +#define BCMA_CORE_PCIE2_FUNC0_IMAP0_3 0x0C0C
746 +#define BCMA_CORE_PCIE2_FUNC0_IMAP0_4 0x0C10
747 +#define BCMA_CORE_PCIE2_FUNC0_IMAP0_5 0x0C14
748 +#define BCMA_CORE_PCIE2_FUNC0_IMAP0_6 0x0C18
749 +#define BCMA_CORE_PCIE2_FUNC0_IMAP0_7 0x0C1C
750 +#define BCMA_CORE_PCIE2_FUNC1_IMAP0_0 0x0C20
751 +#define BCMA_CORE_PCIE2_FUNC1_IMAP0_1 0x0C24
752 +#define BCMA_CORE_PCIE2_FUNC1_IMAP0_2 0x0C28
753 +#define BCMA_CORE_PCIE2_FUNC1_IMAP0_3 0x0C2C
754 +#define BCMA_CORE_PCIE2_FUNC1_IMAP0_4 0x0C30
755 +#define BCMA_CORE_PCIE2_FUNC1_IMAP0_5 0x0C34
756 +#define BCMA_CORE_PCIE2_FUNC1_IMAP0_6 0x0C38
757 +#define BCMA_CORE_PCIE2_FUNC1_IMAP0_7 0x0C3C
758 +#define BCMA_CORE_PCIE2_FUNC0_IMAP1 0x0C80
759 +#define BCMA_CORE_PCIE2_FUNC1_IMAP1 0x0C88
760 +#define BCMA_CORE_PCIE2_FUNC0_IMAP2 0x0CC0
761 +#define BCMA_CORE_PCIE2_FUNC1_IMAP2 0x0CC8
762 +#define BCMA_CORE_PCIE2_IARR0_LOWER 0x0D00
763 +#define BCMA_CORE_PCIE2_IARR0_UPPER 0x0D04
764 +#define BCMA_CORE_PCIE2_IARR1_LOWER 0x0D08
765 +#define BCMA_CORE_PCIE2_IARR1_UPPER 0x0D0C
766 +#define BCMA_CORE_PCIE2_IARR2_LOWER 0x0D10
767 +#define BCMA_CORE_PCIE2_IARR2_UPPER 0x0D14
768 +#define BCMA_CORE_PCIE2_OARR0 0x0D20
769 +#define BCMA_CORE_PCIE2_OARR1 0x0D28
770 +#define BCMA_CORE_PCIE2_OARR2 0x0D30
771 +#define BCMA_CORE_PCIE2_OMAP0_LOWER 0x0D40
772 +#define BCMA_CORE_PCIE2_OMAP0_UPPER 0x0D44
773 +#define BCMA_CORE_PCIE2_OMAP1_LOWER 0x0D48
774 +#define BCMA_CORE_PCIE2_OMAP1_UPPER 0x0D4C
775 +#define BCMA_CORE_PCIE2_OMAP2_LOWER 0x0D50
776 +#define BCMA_CORE_PCIE2_OMAP2_UPPER 0x0D54
777 +#define BCMA_CORE_PCIE2_FUNC1_IARR1_SIZE 0x0D58
778 +#define BCMA_CORE_PCIE2_FUNC1_IARR2_SIZE 0x0D5C
779 +#define BCMA_CORE_PCIE2_MEM_CONTROL 0x0F00
780 +#define BCMA_CORE_PCIE2_MEM_ECC_ERRLOG0 0x0F04
781 +#define BCMA_CORE_PCIE2_MEM_ECC_ERRLOG1 0x0F08
782 +#define BCMA_CORE_PCIE2_LINK_STATUS 0x0F0C
783 +#define BCMA_CORE_PCIE2_STRAP_STATUS 0x0F10
784 +#define BCMA_CORE_PCIE2_RESET_STATUS 0x0F14
785 +#define BCMA_CORE_PCIE2_RESETEN_IN_LINKDOWN 0x0F18
786 +#define BCMA_CORE_PCIE2_MISC_INTR_EN 0x0F1C
787 +#define BCMA_CORE_PCIE2_TX_DEBUG_CFG 0x0F20
788 +#define BCMA_CORE_PCIE2_MISC_CONFIG 0x0F24
789 +#define BCMA_CORE_PCIE2_MISC_STATUS 0x0F28
790 +#define BCMA_CORE_PCIE2_INTR_EN 0x0F30
791 +#define BCMA_CORE_PCIE2_INTR_CLEAR 0x0F34
792 +#define BCMA_CORE_PCIE2_INTR_STATUS 0x0F38
794 +/* PCIE gen2 config regs */
795 +#define PCIE2_INTSTATUS 0x090
796 +#define PCIE2_INTMASK 0x094
797 +#define PCIE2_SBMBX 0x098
799 +#define PCIE2_PMCR_REFUP 0x1814 /* Trefup time */
801 +#define PCIE2_CAP_DEVSTSCTRL2_OFFSET 0xD4
802 +#define PCIE2_CAP_DEVSTSCTRL2_LTRENAB 0x400
803 +#define PCIE2_PVT_REG_PM_CLK_PERIOD 0x184c
805 +struct bcma_drv_pcie2 {
806 + struct bcma_device *core;
809 +#define pcie2_read16(pcie2, offset) bcma_read16((pcie2)->core, offset)
810 +#define pcie2_read32(pcie2, offset) bcma_read32((pcie2)->core, offset)
811 +#define pcie2_write16(pcie2, offset, val) bcma_write16((pcie2)->core, offset, val)
812 +#define pcie2_write32(pcie2, offset, val) bcma_write32((pcie2)->core, offset, val)
814 +#define pcie2_set32(pcie2, offset, set) bcma_set32((pcie2)->core, offset, set)
815 +#define pcie2_mask32(pcie2, offset, mask) bcma_mask32((pcie2)->core, offset, mask)
817 +void bcma_core_pcie2_init(struct bcma_drv_pcie2 *pcie2);
819 +#endif /* LINUX_BCMA_DRIVER_PCIE2_H_ */
820 --- a/drivers/bcma/scan.c
821 +++ b/drivers/bcma/scan.c
822 @@ -32,17 +32,17 @@ static const struct bcma_device_id_name
823 { BCMA_CORE_4706_CHIPCOMMON, "BCM4706 ChipCommon" },
824 { BCMA_CORE_4706_SOC_RAM, "BCM4706 SOC RAM" },
825 { BCMA_CORE_4706_MAC_GBIT, "BCM4706 GBit MAC" },
826 - { BCMA_CORE_PCIEG2, "PCIe Gen 2" },
827 - { BCMA_CORE_DMA, "DMA" },
828 - { BCMA_CORE_SDIO3, "SDIO3" },
829 - { BCMA_CORE_USB20, "USB 2.0" },
830 - { BCMA_CORE_USB30, "USB 3.0" },
831 - { BCMA_CORE_A9JTAG, "ARM Cortex A9 JTAG" },
832 - { BCMA_CORE_DDR23, "Denali DDR2/DDR3 memory controller" },
833 - { BCMA_CORE_ROM, "ROM" },
834 - { BCMA_CORE_NAND, "NAND flash controller" },
835 - { BCMA_CORE_QSPI, "SPI flash controller" },
836 - { BCMA_CORE_CHIPCOMMON_B, "Chipcommon B" },
837 + { BCMA_CORE_NS_PCIEG2, "PCIe Gen 2" },
838 + { BCMA_CORE_NS_DMA, "DMA" },
839 + { BCMA_CORE_NS_SDIO3, "SDIO3" },
840 + { BCMA_CORE_NS_USB20, "USB 2.0" },
841 + { BCMA_CORE_NS_USB30, "USB 3.0" },
842 + { BCMA_CORE_NS_A9JTAG, "ARM Cortex A9 JTAG" },
843 + { BCMA_CORE_NS_DDR23, "Denali DDR2/DDR3 memory controller" },
844 + { BCMA_CORE_NS_ROM, "ROM" },
845 + { BCMA_CORE_NS_NAND, "NAND flash controller" },
846 + { BCMA_CORE_NS_QSPI, "SPI flash controller" },
847 + { BCMA_CORE_NS_CHIPCOMMON_B, "Chipcommon B" },
848 { BCMA_CORE_ARMCA9, "ARM Cortex A9 core (ihost)" },
849 { BCMA_CORE_AMEMC, "AMEMC (DDR)" },
850 { BCMA_CORE_ALTA, "ALTA (I2S)" },
851 @@ -276,7 +276,7 @@ static int bcma_get_next_core(struct bcm
852 struct bcma_device *core)
858 u8 ports[2], wrappers[2];
860 @@ -314,6 +314,7 @@ static int bcma_get_next_core(struct bcm
861 /* Some specific cores don't need wrappers */
862 switch (core->id.id) {
863 case BCMA_CORE_4706_MAC_GBIT_COMMON:
864 + case BCMA_CORE_NS_CHIPCOMMON_B:
865 /* Not used yet: case BCMA_CORE_OOB_ROUTER: */
868 @@ -367,6 +368,7 @@ static int bcma_get_next_core(struct bcm
871 /* get & parse slave ports */
873 for (i = 0; i < ports[1]; i++) {
875 tmp = bcma_erom_get_addr_desc(bus, eromptr,
876 @@ -376,9 +378,9 @@ static int bcma_get_next_core(struct bcm
877 /* pr_debug("erom: slave port %d "
878 * "has %d descriptors\n", i, j); */
881 - if (i == 0 && j == 0)
883 + } else if (k < ARRAY_SIZE(core->addr_s)) {
884 + core->addr_s[k] = tmp;
889 @@ -421,10 +423,13 @@ static int bcma_get_next_core(struct bcm
890 core->io_addr = ioremap_nocache(core->addr, BCMA_CORE_SIZE);
893 - core->io_wrap = ioremap_nocache(core->wrap, BCMA_CORE_SIZE);
894 - if (!core->io_wrap) {
895 - iounmap(core->io_addr);
898 + core->io_wrap = ioremap_nocache(core->wrap,
900 + if (!core->io_wrap) {
901 + iounmap(core->io_addr);
907 @@ -434,9 +439,7 @@ void bcma_init_bus(struct bcma_bus *bus)
910 struct bcma_chipinfo *chipinfo = &(bus->chipinfo);
912 - if (bus->init_done)
916 INIT_LIST_HEAD(&bus->cores);
918 @@ -447,10 +450,11 @@ void bcma_init_bus(struct bcma_bus *bus)
919 chipinfo->id = (tmp & BCMA_CC_ID_ID) >> BCMA_CC_ID_ID_SHIFT;
920 chipinfo->rev = (tmp & BCMA_CC_ID_REV) >> BCMA_CC_ID_REV_SHIFT;
921 chipinfo->pkg = (tmp & BCMA_CC_ID_PKG) >> BCMA_CC_ID_PKG_SHIFT;
922 - bcma_info(bus, "Found chip with id 0x%04X, rev 0x%02X and package 0x%02X\n",
923 - chipinfo->id, chipinfo->rev, chipinfo->pkg);
925 - bus->init_done = true;
926 + snprintf(chip_id, ARRAY_SIZE(chip_id),
927 + (chipinfo->id > 0x9999) ? "%d" : "0x%04X", chipinfo->id);
928 + bcma_info(bus, "Found chip with id %s, rev 0x%02X and package 0x%02X\n",
929 + chip_id, chipinfo->rev, chipinfo->pkg);
932 int bcma_bus_scan(struct bcma_bus *bus)
933 @@ -460,8 +464,6 @@ int bcma_bus_scan(struct bcma_bus *bus)
935 int err, core_num = 0;
937 - bcma_init_bus(bus);
939 erombase = bcma_scan_read32(bus, 0, BCMA_CC_EROM);
940 if (bus->hosttype == BCMA_HOSTTYPE_SOC) {
941 eromptr = ioremap_nocache(erombase, BCMA_CORE_SIZE);
942 --- a/drivers/bcma/host_soc.c
943 +++ b/drivers/bcma/host_soc.c
946 #include "bcma_private.h"
948 +#include <linux/slab.h>
949 +#include <linux/module.h>
950 +#include <linux/of_address.h>
951 #include <linux/bcma/bcma.h>
952 #include <linux/bcma/bcma_soc.h>
954 @@ -134,12 +137,16 @@ static void bcma_host_soc_block_write(st
956 static u32 bcma_host_soc_aread32(struct bcma_device *core, u16 offset)
958 + if (WARN_ONCE(!core->io_wrap, "Accessed core has no wrapper/agent\n"))
960 return readl(core->io_wrap + offset);
963 static void bcma_host_soc_awrite32(struct bcma_device *core, u16 offset,
966 + if (WARN_ONCE(!core->io_wrap, "Accessed core has no wrapper/agent\n"))
968 writel(value, core->io_wrap + offset);
971 @@ -161,7 +168,6 @@ static const struct bcma_host_ops bcma_h
972 int __init bcma_host_soc_register(struct bcma_soc *soc)
974 struct bcma_bus *bus = &soc->bus;
977 /* iomap only first core. We have to read some register on this core
979 @@ -173,11 +179,100 @@ int __init bcma_host_soc_register(struct
981 bus->hosttype = BCMA_HOSTTYPE_SOC;
982 bus->ops = &bcma_host_soc_ops;
983 + bus->host_pdev = NULL;
986 + /* Initialize struct, detect chip */
987 + bcma_init_bus(bus);
992 +int __init bcma_host_soc_init(struct bcma_soc *soc)
994 + struct bcma_bus *bus = &soc->bus;
997 + /* Scan bus and initialize it */
998 err = bcma_bus_early_register(bus, &soc->core_cc, &soc->core_mips);
1006 +static int bcma_host_soc_probe(struct platform_device *pdev)
1008 + struct device *dev = &pdev->dev;
1009 + struct device_node *np = dev->of_node;
1010 + struct bcma_bus *bus;
1014 + bus = devm_kzalloc(dev, sizeof(*bus), GFP_KERNEL);
1019 + bus->mmio = of_iomap(np, 0);
1023 + /* Host specific */
1024 + bus->hosttype = BCMA_HOSTTYPE_SOC;
1025 + bus->ops = &bcma_host_soc_ops;
1026 + bus->host_pdev = pdev;
1028 + /* Initialize struct, detect chip */
1029 + bcma_init_bus(bus);
1032 + err = bcma_bus_register(bus);
1034 + goto err_unmap_mmio;
1036 + platform_set_drvdata(pdev, bus);
1041 + iounmap(bus->mmio);
1045 +static int bcma_host_soc_remove(struct platform_device *pdev)
1047 + struct bcma_bus *bus = platform_get_drvdata(pdev);
1049 + bcma_bus_unregister(bus);
1050 + iounmap(bus->mmio);
1051 + platform_set_drvdata(pdev, NULL);
1056 +static const struct of_device_id bcma_host_soc_of_match[] = {
1057 + { .compatible = "brcm,bus-axi", },
1060 +MODULE_DEVICE_TABLE(of, bcma_host_soc_of_match);
1062 +static struct platform_driver bcma_host_soc_driver = {
1064 + .name = "bcma-host-soc",
1065 + .of_match_table = bcma_host_soc_of_match,
1067 + .probe = bcma_host_soc_probe,
1068 + .remove = bcma_host_soc_remove,
1071 +int __init bcma_host_soc_register_driver(void)
1073 + return platform_driver_register(&bcma_host_soc_driver);
1076 +void __exit bcma_host_soc_unregister_driver(void)
1078 + platform_driver_unregister(&bcma_host_soc_driver);
1080 +#endif /* CONFIG_OF */
1081 --- a/drivers/bcma/driver_mips.c
1082 +++ b/drivers/bcma/driver_mips.c
1084 #include <linux/serial_reg.h>
1085 #include <linux/time.h>
1087 +enum bcma_boot_dev {
1088 + BCMA_BOOT_DEV_UNK = 0,
1089 + BCMA_BOOT_DEV_ROM,
1090 + BCMA_BOOT_DEV_PARALLEL,
1091 + BCMA_BOOT_DEV_SERIAL,
1092 + BCMA_BOOT_DEV_NAND,
1095 static const char * const part_probes[] = { "bcm47xxpart", NULL };
1097 static struct physmap_flash_data bcma_pflash_data = {
1098 @@ -229,11 +237,51 @@ u32 bcma_cpu_clock(struct bcma_drv_mips
1100 EXPORT_SYMBOL(bcma_cpu_clock);
1102 +static enum bcma_boot_dev bcma_boot_dev(struct bcma_bus *bus)
1104 + struct bcma_drv_cc *cc = &bus->drv_cc;
1105 + u8 cc_rev = cc->core->id.rev;
1107 + if (cc_rev == 42) {
1108 + struct bcma_device *core;
1110 + core = bcma_find_core(bus, BCMA_CORE_NS_ROM);
1112 + switch (bcma_aread32(core, BCMA_IOST) &
1113 + BCMA_NS_ROM_IOST_BOOT_DEV_MASK) {
1114 + case BCMA_NS_ROM_IOST_BOOT_DEV_NOR:
1115 + return BCMA_BOOT_DEV_SERIAL;
1116 + case BCMA_NS_ROM_IOST_BOOT_DEV_NAND:
1117 + return BCMA_BOOT_DEV_NAND;
1118 + case BCMA_NS_ROM_IOST_BOOT_DEV_ROM:
1120 + return BCMA_BOOT_DEV_ROM;
1124 + if (cc_rev == 38) {
1125 + if (cc->status & BCMA_CC_CHIPST_5357_NAND_BOOT)
1126 + return BCMA_BOOT_DEV_NAND;
1127 + else if (cc->status & BIT(5))
1128 + return BCMA_BOOT_DEV_ROM;
1131 + if ((cc->capabilities & BCMA_CC_CAP_FLASHT) ==
1132 + BCMA_CC_FLASHT_PARA)
1133 + return BCMA_BOOT_DEV_PARALLEL;
1135 + return BCMA_BOOT_DEV_SERIAL;
1138 + return BCMA_BOOT_DEV_SERIAL;
1141 static void bcma_core_mips_flash_detect(struct bcma_drv_mips *mcore)
1143 struct bcma_bus *bus = mcore->core->bus;
1144 struct bcma_drv_cc *cc = &bus->drv_cc;
1145 struct bcma_pflash *pflash = &cc->pflash;
1146 + enum bcma_boot_dev boot_dev;
1148 switch (cc->capabilities & BCMA_CC_CAP_FLASHT) {
1149 case BCMA_CC_FLASHT_STSER:
1150 @@ -269,6 +317,20 @@ static void bcma_core_mips_flash_detect(
1151 bcma_nflash_init(cc);
1155 + /* Determine flash type this SoC boots from */
1156 + boot_dev = bcma_boot_dev(bus);
1157 + switch (boot_dev) {
1158 + case BCMA_BOOT_DEV_PARALLEL:
1159 + case BCMA_BOOT_DEV_SERIAL:
1160 + /* TODO: Init NVRAM using BCMA_SOC_FLASH2 window */
1162 + case BCMA_BOOT_DEV_NAND:
1163 + /* TODO: Init NVRAM using BCMA_SOC_FLASH1 window */
1170 void bcma_core_mips_early_init(struct bcma_drv_mips *mcore)
1171 --- a/include/linux/bcma/bcma_regs.h
1172 +++ b/include/linux/bcma/bcma_regs.h
1174 #define BCMA_RESET_CTL_RESET 0x0001
1175 #define BCMA_RESET_ST 0x0804
1177 +#define BCMA_NS_ROM_IOST_BOOT_DEV_MASK 0x0003
1178 +#define BCMA_NS_ROM_IOST_BOOT_DEV_NOR 0x0000
1179 +#define BCMA_NS_ROM_IOST_BOOT_DEV_NAND 0x0001
1180 +#define BCMA_NS_ROM_IOST_BOOT_DEV_ROM 0x0002
1182 /* BCMA PCI config space registers. */
1183 #define BCMA_PCI_PMCSR 0x44
1184 #define BCMA_PCI_PE 0x100
1185 --- a/drivers/usb/host/bcma-hcd.c
1186 +++ b/drivers/usb/host/bcma-hcd.c
1187 @@ -237,7 +237,7 @@ static int bcma_hcd_probe(struct bcma_de
1188 bcma_hcd_init_chip(dev);
1190 /* In AI chips EHCI is addrspace 0, OHCI is 1 */
1191 - ohci_addr = dev->addr1;
1192 + ohci_addr = dev->addr_s[0];
1193 if ((chipinfo->id == 0x5357 || chipinfo->id == 0x4749)
1194 && chipinfo->rev == 0)
1195 ohci_addr = 0x18009000;
1196 --- a/drivers/bcma/bcma_private.h
1197 +++ b/drivers/bcma/bcma_private.h
1198 @@ -50,6 +50,10 @@ void bcma_chipco_serial_init(struct bcma
1199 extern struct platform_device bcma_pflash_dev;
1200 #endif /* CONFIG_BCMA_DRIVER_MIPS */
1202 +/* driver_chipcommon_b.c */
1203 +int bcma_core_chipcommon_b_init(struct bcma_drv_cc_b *ccb);
1204 +void bcma_core_chipcommon_b_free(struct bcma_drv_cc_b *ccb);
1206 /* driver_chipcommon_pmu.c */
1207 u32 bcma_pmu_get_alp_clock(struct bcma_drv_cc *cc);
1208 u32 bcma_pmu_get_cpu_clock(struct bcma_drv_cc *cc);
1209 @@ -84,6 +88,20 @@ extern int __init bcma_host_pci_init(voi
1210 extern void __exit bcma_host_pci_exit(void);
1211 #endif /* CONFIG_BCMA_HOST_PCI */
1214 +#if defined(CONFIG_BCMA_HOST_SOC) && defined(CONFIG_OF)
1215 +extern int __init bcma_host_soc_register_driver(void);
1216 +extern void __exit bcma_host_soc_unregister_driver(void);
1218 +static inline int __init bcma_host_soc_register_driver(void)
1222 +static inline void __exit bcma_host_soc_unregister_driver(void)
1225 +#endif /* CONFIG_BCMA_HOST_SOC && CONFIG_OF */
1228 u32 bcma_pcie_read(struct bcma_drv_pci *pc, u32 address);
1231 +++ b/drivers/bcma/driver_chipcommon_b.c
1234 + * Broadcom specific AMBA
1235 + * ChipCommon B Unit driver
1237 + * Copyright 2014, Hauke Mehrtens <hauke@hauke-m.de>
1239 + * Licensed under the GNU/GPL. See COPYING for details.
1242 +#include "bcma_private.h"
1243 +#include <linux/export.h>
1244 +#include <linux/bcma/bcma.h>
1246 +static bool bcma_wait_reg(struct bcma_bus *bus, void __iomem *addr, u32 mask,
1247 + u32 value, int timeout)
1249 + unsigned long deadline = jiffies + timeout;
1253 + val = readl(addr);
1254 + if ((val & mask) == value)
1258 + } while (!time_after_eq(jiffies, deadline));
1260 + bcma_err(bus, "Timeout waiting for register %p\n", addr);
1265 +void bcma_chipco_b_mii_write(struct bcma_drv_cc_b *ccb, u32 offset, u32 value)
1267 + struct bcma_bus *bus = ccb->core->bus;
1269 + writel(offset, ccb->mii + 0x00);
1270 + bcma_wait_reg(bus, ccb->mii + 0x00, 0x0100, 0x0000, 100);
1271 + writel(value, ccb->mii + 0x04);
1272 + bcma_wait_reg(bus, ccb->mii + 0x00, 0x0100, 0x0000, 100);
1274 +EXPORT_SYMBOL_GPL(bcma_chipco_b_mii_write);
1276 +int bcma_core_chipcommon_b_init(struct bcma_drv_cc_b *ccb)
1278 + if (ccb->setup_done)
1281 + ccb->setup_done = 1;
1282 + ccb->mii = ioremap_nocache(ccb->core->addr_s[1], BCMA_CORE_SIZE);
1289 +void bcma_core_chipcommon_b_free(struct bcma_drv_cc_b *ccb)
1292 + iounmap(ccb->mii);
1294 --- a/include/linux/bcma/bcma_driver_chipcommon.h
1295 +++ b/include/linux/bcma/bcma_driver_chipcommon.h
1296 @@ -644,6 +644,12 @@ struct bcma_drv_cc {
1300 +struct bcma_drv_cc_b {
1301 + struct bcma_device *core;
1303 + void __iomem *mii;
1306 /* Register access */
1307 #define bcma_cc_read32(cc, offset) \
1308 bcma_read32((cc)->core, offset)
1309 @@ -699,4 +705,6 @@ extern void bcma_pmu_spuravoid_pllupdate
1311 extern u32 bcma_pmu_get_bus_clock(struct bcma_drv_cc *cc);
1313 +void bcma_chipco_b_mii_write(struct bcma_drv_cc_b *ccb, u32 offset, u32 value);
1315 #endif /* LINUX_BCMA_DRIVER_CC_H_ */
1316 --- a/arch/mips/bcm47xx/setup.c
1317 +++ b/arch/mips/bcm47xx/setup.c
1318 @@ -202,6 +202,10 @@ static void __init bcm47xx_register_bcma
1320 err = bcma_host_soc_register(&bcm47xx_bus.bcma);
1322 + panic("Failed to register BCMA bus (err %d)", err);
1324 + err = bcma_host_soc_init(&bcm47xx_bus.bcma);
1326 panic("Failed to initialize BCMA bus (err %d)", err);
1328 bcm47xx_fill_bcma_boardinfo(&bcm47xx_bus.bcma.bus.boardinfo, NULL);
1329 --- a/include/linux/bcma/bcma_soc.h
1330 +++ b/include/linux/bcma/bcma_soc.h
1331 @@ -10,6 +10,7 @@ struct bcma_soc {
1334 int __init bcma_host_soc_register(struct bcma_soc *soc);
1335 +int __init bcma_host_soc_init(struct bcma_soc *soc);
1337 int bcma_bus_register(struct bcma_bus *bus);
1340 +++ b/Documentation/devicetree/bindings/bus/bcma.txt
1342 +Driver for ARM AXI Bus with Broadcom Plugins (bcma)
1344 +Required properties:
1346 +- compatible : brcm,bus-axi
1348 +- reg : iomem address range of chipcommon core
1350 +The cores on the AXI bus are automatically detected by bcma with the
1351 +memory ranges they are using and they get registered afterwards.
1353 +The top-level axi bus may contain children representing attached cores
1354 +(devices). This is needed since some hardware details can't be auto
1355 +detected (e.g. IRQ numbers). Also some of the cores may be responsible
1356 +for extra things, e.g. ChipCommon providing access to the GPIO chip.
1361 + compatible = "brcm,bus-axi";
1362 + reg = <0x18000000 0x1000>;
1363 + ranges = <0x00000000 0x18000000 0x00100000>;
1364 + #address-cells = <1>;
1365 + #size-cells = <1>;
1368 + reg = <0x00000000 0x1000>;
1371 + #gpio-cells = <2>;