1 --- a/drivers/bcma/Kconfig
2 +++ b/drivers/bcma/Kconfig
3 @@ -26,6 +26,7 @@ config BCMA_HOST_PCI_POSSIBLE
5 bool "Support for BCMA on PCI-host bus"
6 depends on BCMA_HOST_PCI_POSSIBLE
9 config BCMA_DRIVER_PCI_HOSTMODE
10 bool "Driver for PCI core working in hostmode"
11 --- a/drivers/bcma/bcma_private.h
12 +++ b/drivers/bcma/bcma_private.h
17 +bool bcma_wait_value(struct bcma_device *core, u16 reg, u32 mask, u32 value,
19 int bcma_bus_register(struct bcma_bus *bus);
20 void bcma_bus_unregister(struct bcma_bus *bus);
21 int __init bcma_bus_early_register(struct bcma_bus *bus,
22 --- a/drivers/bcma/core.c
23 +++ b/drivers/bcma/core.c
25 #include <linux/export.h>
26 #include <linux/bcma/bcma.h>
28 +static bool bcma_core_wait_value(struct bcma_device *core, u16 reg, u32 mask,
29 + u32 value, int timeout)
31 + unsigned long deadline = jiffies + timeout;
35 + val = bcma_aread32(core, reg);
36 + if ((val & mask) == value)
40 + } while (!time_after_eq(jiffies, deadline));
42 + bcma_warn(core->bus, "Timeout waiting for register 0x%04X!\n", reg);
47 bool bcma_core_is_enabled(struct bcma_device *core)
49 if ((bcma_aread32(core, BCMA_IOCTL) & (BCMA_IOCTL_CLK | BCMA_IOCTL_FGC))
50 @@ -25,13 +44,15 @@ void bcma_core_disable(struct bcma_devic
51 if (bcma_aread32(core, BCMA_RESET_CTL) & BCMA_RESET_CTL_RESET)
54 - bcma_awrite32(core, BCMA_IOCTL, flags);
55 - bcma_aread32(core, BCMA_IOCTL);
57 + bcma_core_wait_value(core, BCMA_RESET_ST, ~0, 0, 300);
59 bcma_awrite32(core, BCMA_RESET_CTL, BCMA_RESET_CTL_RESET);
60 bcma_aread32(core, BCMA_RESET_CTL);
63 + bcma_awrite32(core, BCMA_IOCTL, flags);
64 + bcma_aread32(core, BCMA_IOCTL);
67 EXPORT_SYMBOL_GPL(bcma_core_disable);
69 @@ -43,6 +64,7 @@ int bcma_core_enable(struct bcma_device
70 bcma_aread32(core, BCMA_IOCTL);
72 bcma_awrite32(core, BCMA_RESET_CTL, 0);
73 + bcma_aread32(core, BCMA_RESET_CTL);
76 bcma_awrite32(core, BCMA_IOCTL, (BCMA_IOCTL_CLK | flags));
77 --- a/drivers/bcma/driver_chipcommon.c
78 +++ b/drivers/bcma/driver_chipcommon.c
79 @@ -140,8 +140,15 @@ void bcma_core_chipcommon_init(struct bc
80 bcma_core_chipcommon_early_init(cc);
82 if (cc->core->id.rev >= 20) {
83 - bcma_cc_write32(cc, BCMA_CC_GPIOPULLUP, 0);
84 - bcma_cc_write32(cc, BCMA_CC_GPIOPULLDOWN, 0);
85 + u32 pullup = 0, pulldown = 0;
87 + if (cc->core->bus->chipinfo.id == BCMA_CHIP_ID_BCM43142) {
92 + bcma_cc_write32(cc, BCMA_CC_GPIOPULLUP, pullup);
93 + bcma_cc_write32(cc, BCMA_CC_GPIOPULLDOWN, pulldown);
96 if (cc->capabilities & BCMA_CC_CAP_PMU)
97 --- a/drivers/bcma/driver_chipcommon_pmu.c
98 +++ b/drivers/bcma/driver_chipcommon_pmu.c
99 @@ -56,6 +56,109 @@ void bcma_chipco_regctl_maskset(struct b
101 EXPORT_SYMBOL_GPL(bcma_chipco_regctl_maskset);
103 +static u32 bcma_pmu_xtalfreq(struct bcma_drv_cc *cc)
105 + u32 ilp_ctl, alp_hz;
107 + if (!(bcma_cc_read32(cc, BCMA_CC_PMU_STAT) &
108 + BCMA_CC_PMU_STAT_EXT_LPO_AVAIL))
111 + bcma_cc_write32(cc, BCMA_CC_PMU_XTAL_FREQ,
112 + BIT(BCMA_CC_PMU_XTAL_FREQ_MEASURE_SHIFT));
113 + usleep_range(1000, 2000);
115 + ilp_ctl = bcma_cc_read32(cc, BCMA_CC_PMU_XTAL_FREQ);
116 + ilp_ctl &= BCMA_CC_PMU_XTAL_FREQ_ILPCTL_MASK;
118 + bcma_cc_write32(cc, BCMA_CC_PMU_XTAL_FREQ, 0);
120 + alp_hz = ilp_ctl * 32768 / 4;
121 + return (alp_hz + 50000) / 100000 * 100;
124 +static void bcma_pmu2_pll_init0(struct bcma_drv_cc *cc, u32 xtalfreq)
126 + struct bcma_bus *bus = cc->core->bus;
127 + u32 freq_tgt_target = 0, freq_tgt_current;
130 + switch (bus->chipinfo.id) {
131 + case BCMA_CHIP_ID_BCM43142:
132 + /* pmu2_xtaltab0_adfll_485 */
133 + switch (xtalfreq) {
135 + freq_tgt_target = 0x50D52;
138 + freq_tgt_target = 0x307FE;
141 + freq_tgt_target = 0x254EA;
144 + freq_tgt_target = 0x19EF8;
147 + freq_tgt_target = 0x12A75;
153 + if (!freq_tgt_target) {
154 + bcma_err(bus, "Unknown TGT frequency for xtalfreq %d\n",
159 + pll0 = bcma_chipco_pll_read(cc, BCMA_CC_PMU15_PLL_PLLCTL0);
160 + freq_tgt_current = (pll0 & BCMA_CC_PMU15_PLL_PC0_FREQTGT_MASK) >>
161 + BCMA_CC_PMU15_PLL_PC0_FREQTGT_SHIFT;
163 + if (freq_tgt_current == freq_tgt_target) {
164 + bcma_debug(bus, "Target TGT frequency already set\n");
169 + switch (bus->chipinfo.id) {
170 + case BCMA_CHIP_ID_BCM43142:
171 + mask = (u32)~(BCMA_RES_4314_HT_AVAIL |
172 + BCMA_RES_4314_MACPHY_CLK_AVAIL);
174 + bcma_cc_mask32(cc, BCMA_CC_PMU_MINRES_MSK, mask);
175 + bcma_cc_mask32(cc, BCMA_CC_PMU_MAXRES_MSK, mask);
176 + bcma_wait_value(cc->core, BCMA_CLKCTLST,
177 + BCMA_CLKCTLST_HAVEHT, 0, 20000);
181 + pll0 &= ~BCMA_CC_PMU15_PLL_PC0_FREQTGT_MASK;
182 + pll0 |= freq_tgt_target << BCMA_CC_PMU15_PLL_PC0_FREQTGT_SHIFT;
183 + bcma_chipco_pll_write(cc, BCMA_CC_PMU15_PLL_PLLCTL0, pll0);
186 + if (cc->pmu.rev >= 2)
187 + bcma_cc_set32(cc, BCMA_CC_PMU_CTL, BCMA_CC_PMU_CTL_PLL_UPD);
189 + /* TODO: Do we need to update OTP? */
192 +static void bcma_pmu_pll_init(struct bcma_drv_cc *cc)
194 + struct bcma_bus *bus = cc->core->bus;
195 + u32 xtalfreq = bcma_pmu_xtalfreq(cc);
197 + switch (bus->chipinfo.id) {
198 + case BCMA_CHIP_ID_BCM43142:
201 + bcma_pmu2_pll_init0(cc, xtalfreq);
206 static void bcma_pmu_resources_init(struct bcma_drv_cc *cc)
208 struct bcma_bus *bus = cc->core->bus;
209 @@ -66,6 +169,25 @@ static void bcma_pmu_resources_init(stru
213 + case BCMA_CHIP_ID_BCM43142:
214 + min_msk = BCMA_RES_4314_LPLDO_PU |
215 + BCMA_RES_4314_PMU_SLEEP_DIS |
216 + BCMA_RES_4314_PMU_BG_PU |
217 + BCMA_RES_4314_CBUCK_LPOM_PU |
218 + BCMA_RES_4314_CBUCK_PFM_PU |
219 + BCMA_RES_4314_CLDO_PU |
220 + BCMA_RES_4314_LPLDO2_LVM |
221 + BCMA_RES_4314_WL_PMU_PU |
222 + BCMA_RES_4314_LDO3P3_PU |
223 + BCMA_RES_4314_OTP_PU |
224 + BCMA_RES_4314_WL_PWRSW_PU |
225 + BCMA_RES_4314_LQ_AVAIL |
226 + BCMA_RES_4314_LOGIC_RET |
227 + BCMA_RES_4314_MEM_SLEEP |
228 + BCMA_RES_4314_MACPHY_RET |
229 + BCMA_RES_4314_WL_CORE_READY;
230 + max_msk = 0x3FFFFFFF;
233 bcma_debug(bus, "PMU resource config unknown or not needed for device 0x%04X\n",
235 @@ -165,6 +287,7 @@ void bcma_pmu_init(struct bcma_drv_cc *c
236 bcma_cc_set32(cc, BCMA_CC_PMU_CTL,
237 BCMA_CC_PMU_CTL_NOILPONW);
239 + bcma_pmu_pll_init(cc);
240 bcma_pmu_resources_init(cc);
241 bcma_pmu_workarounds(cc);
243 --- a/drivers/bcma/driver_chipcommon_sflash.c
244 +++ b/drivers/bcma/driver_chipcommon_sflash.c
245 @@ -30,7 +30,7 @@ struct bcma_sflash_tbl_e {
249 -static struct bcma_sflash_tbl_e bcma_sflash_st_tbl[] = {
250 +static const struct bcma_sflash_tbl_e bcma_sflash_st_tbl[] = {
251 { "M25P20", 0x11, 0x10000, 4, },
252 { "M25P40", 0x12, 0x10000, 8, },
254 @@ -41,7 +41,7 @@ static struct bcma_sflash_tbl_e bcma_sfl
258 -static struct bcma_sflash_tbl_e bcma_sflash_sst_tbl[] = {
259 +static const struct bcma_sflash_tbl_e bcma_sflash_sst_tbl[] = {
260 { "SST25WF512", 1, 0x1000, 16, },
261 { "SST25VF512", 0x48, 0x1000, 16, },
262 { "SST25WF010", 2, 0x1000, 32, },
263 @@ -59,7 +59,7 @@ static struct bcma_sflash_tbl_e bcma_sfl
267 -static struct bcma_sflash_tbl_e bcma_sflash_at_tbl[] = {
268 +static const struct bcma_sflash_tbl_e bcma_sflash_at_tbl[] = {
269 { "AT45DB011", 0xc, 256, 512, },
270 { "AT45DB021", 0x14, 256, 1024, },
271 { "AT45DB041", 0x1c, 256, 2048, },
272 @@ -89,7 +89,7 @@ int bcma_sflash_init(struct bcma_drv_cc
274 struct bcma_bus *bus = cc->core->bus;
275 struct bcma_sflash *sflash = &cc->sflash;
276 - struct bcma_sflash_tbl_e *e;
277 + const struct bcma_sflash_tbl_e *e;
280 switch (cc->capabilities & BCMA_CC_CAP_FLASHT) {
281 --- a/drivers/bcma/host_pci.c
282 +++ b/drivers/bcma/host_pci.c
283 @@ -275,6 +275,7 @@ static DEFINE_PCI_DEVICE_TABLE(bcma_pci_
284 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4357) },
285 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4358) },
286 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4359) },
287 + { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4365) },
288 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4727) },
291 --- a/drivers/bcma/main.c
292 +++ b/drivers/bcma/main.c
293 @@ -93,6 +93,25 @@ struct bcma_device *bcma_find_core_unit(
297 +bool bcma_wait_value(struct bcma_device *core, u16 reg, u32 mask, u32 value,
300 + unsigned long deadline = jiffies + timeout;
304 + val = bcma_read32(core, reg);
305 + if ((val & mask) == value)
309 + } while (!time_after_eq(jiffies, deadline));
311 + bcma_warn(core->bus, "Timeout waiting for register 0x%04X!\n", reg);
316 static void bcma_release_core_dev(struct device *dev)
318 struct bcma_device *core = container_of(dev, struct bcma_device, dev);
319 --- a/drivers/bcma/sprom.c
320 +++ b/drivers/bcma/sprom.c
321 @@ -72,12 +72,12 @@ fail:
323 **************************************************/
325 -static void bcma_sprom_read(struct bcma_bus *bus, u16 offset, u16 *sprom)
326 +static void bcma_sprom_read(struct bcma_bus *bus, u16 offset, u16 *sprom,
330 - for (i = 0; i < SSB_SPROMSIZE_WORDS_R4; i++)
331 - sprom[i] = bcma_read16(bus->drv_cc.core,
333 + for (i = 0; i < words; i++)
334 + sprom[i] = bcma_read16(bus->drv_cc.core, offset + (i * 2));
337 /**************************************************
338 @@ -124,29 +124,29 @@ static inline u8 bcma_crc8(u8 crc, u8 da
339 return t[crc ^ data];
342 -static u8 bcma_sprom_crc(const u16 *sprom)
343 +static u8 bcma_sprom_crc(const u16 *sprom, size_t words)
348 - for (word = 0; word < SSB_SPROMSIZE_WORDS_R4 - 1; word++) {
349 + for (word = 0; word < words - 1; word++) {
350 crc = bcma_crc8(crc, sprom[word] & 0x00FF);
351 crc = bcma_crc8(crc, (sprom[word] & 0xFF00) >> 8);
353 - crc = bcma_crc8(crc, sprom[SSB_SPROMSIZE_WORDS_R4 - 1] & 0x00FF);
354 + crc = bcma_crc8(crc, sprom[words - 1] & 0x00FF);
360 -static int bcma_sprom_check_crc(const u16 *sprom)
361 +static int bcma_sprom_check_crc(const u16 *sprom, size_t words)
367 - crc = bcma_sprom_crc(sprom);
368 - tmp = sprom[SSB_SPROMSIZE_WORDS_R4 - 1] & SSB_SPROM_REVISION_CRC;
369 + crc = bcma_sprom_crc(sprom, words);
370 + tmp = sprom[words - 1] & SSB_SPROM_REVISION_CRC;
371 expected_crc = tmp >> SSB_SPROM_REVISION_CRC_SHIFT;
372 if (crc != expected_crc)
374 @@ -154,21 +154,25 @@ static int bcma_sprom_check_crc(const u1
378 -static int bcma_sprom_valid(const u16 *sprom)
379 +static int bcma_sprom_valid(struct bcma_bus *bus, const u16 *sprom,
385 - err = bcma_sprom_check_crc(sprom);
386 + err = bcma_sprom_check_crc(sprom, words);
390 - revision = sprom[SSB_SPROMSIZE_WORDS_R4 - 1] & SSB_SPROM_REVISION_REV;
391 - if (revision != 8 && revision != 9) {
392 + revision = sprom[words - 1] & SSB_SPROM_REVISION_REV;
393 + if (revision != 8 && revision != 9 && revision != 10) {
394 pr_err("Unsupported SPROM revision: %d\n", revision);
398 + bus->sprom.revision = revision;
399 + bcma_debug(bus, "Found SPROM revision %d\n", revision);
404 @@ -208,9 +212,6 @@ static void bcma_sprom_extract_r8(struct
405 BUILD_BUG_ON(ARRAY_SIZE(pwr_info_offset) !=
406 ARRAY_SIZE(bus->sprom.core_pwr_info));
408 - bus->sprom.revision = sprom[SSB_SPROMSIZE_WORDS_R4 - 1] &
409 - SSB_SPROM_REVISION_REV;
411 for (i = 0; i < 3; i++) {
412 v = sprom[SPOFF(SSB_SPROM8_IL0MAC) + i];
413 *(((__be16 *)bus->sprom.il0mac) + i) = cpu_to_be16(v);
414 @@ -502,7 +503,7 @@ static bool bcma_sprom_onchip_available(
415 case BCMA_CHIP_ID_BCM4331:
416 present = chip_status & BCMA_CC_CHIPST_4331_OTP_PRESENT;
419 + case BCMA_CHIP_ID_BCM43142:
420 case BCMA_CHIP_ID_BCM43224:
421 case BCMA_CHIP_ID_BCM43225:
422 /* for these chips OTP is always available */
423 @@ -550,7 +551,9 @@ int bcma_sprom_get(struct bcma_bus *bus)
425 u16 offset = BCMA_CC_SPROM;
428 + size_t sprom_sizes[] = { SSB_SPROMSIZE_WORDS_R4,
429 + SSB_SPROMSIZE_WORDS_R10, };
432 if (!bus->drv_cc.core)
434 @@ -579,32 +582,37 @@ int bcma_sprom_get(struct bcma_bus *bus)
438 - sprom = kcalloc(SSB_SPROMSIZE_WORDS_R4, sizeof(u16),
443 if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4331 ||
444 bus->chipinfo.id == BCMA_CHIP_ID_BCM43431)
445 bcma_chipco_bcm4331_ext_pa_lines_ctl(&bus->drv_cc, false);
447 bcma_debug(bus, "SPROM offset 0x%x\n", offset);
448 - bcma_sprom_read(bus, offset, sprom);
449 + for (i = 0; i < ARRAY_SIZE(sprom_sizes); i++) {
450 + size_t words = sprom_sizes[i];
452 + sprom = kcalloc(words, sizeof(u16), GFP_KERNEL);
456 + bcma_sprom_read(bus, offset, sprom, words);
457 + err = bcma_sprom_valid(bus, sprom, words);
464 if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4331 ||
465 bus->chipinfo.id == BCMA_CHIP_ID_BCM43431)
466 bcma_chipco_bcm4331_ext_pa_lines_ctl(&bus->drv_cc, true);
468 - err = bcma_sprom_valid(sprom);
470 - bcma_warn(bus, "invalid sprom read from the PCIe card, try to use fallback sprom\n");
471 + bcma_warn(bus, "Invalid SPROM read from the PCIe card, trying to use fallback SPROM\n");
472 err = bcma_fill_sprom_with_fallback(bus, &bus->sprom);
475 + bcma_sprom_extract_r8(bus, sprom);
479 - bcma_sprom_extract_r8(bus, sprom);
485 --- a/include/linux/bcma/bcma.h
486 +++ b/include/linux/bcma/bcma.h
487 @@ -144,6 +144,7 @@ struct bcma_host_ops {
489 /* Chip IDs of PCIe devices */
490 #define BCMA_CHIP_ID_BCM4313 0x4313
491 +#define BCMA_CHIP_ID_BCM43142 43142
492 #define BCMA_CHIP_ID_BCM43224 43224
493 #define BCMA_PKG_ID_BCM43224_FAB_CSM 0x8
494 #define BCMA_PKG_ID_BCM43224_FAB_SMIC 0xa
495 --- a/include/linux/bcma/bcma_driver_chipcommon.h
496 +++ b/include/linux/bcma/bcma_driver_chipcommon.h
498 #define BCMA_CC_PMU_CAP 0x0604 /* PMU capabilities */
499 #define BCMA_CC_PMU_CAP_REVISION 0x000000FF /* Revision mask */
500 #define BCMA_CC_PMU_STAT 0x0608 /* PMU status */
501 +#define BCMA_CC_PMU_STAT_EXT_LPO_AVAIL 0x00000100
502 +#define BCMA_CC_PMU_STAT_WDRESET 0x00000080
503 #define BCMA_CC_PMU_STAT_INTPEND 0x00000040 /* Interrupt pending */
504 #define BCMA_CC_PMU_STAT_SBCLKST 0x00000030 /* Backplane clock status? */
505 #define BCMA_CC_PMU_STAT_HAVEALP 0x00000008 /* ALP available */
507 #define BCMA_CC_REGCTL_DATA 0x065C
508 #define BCMA_CC_PLLCTL_ADDR 0x0660
509 #define BCMA_CC_PLLCTL_DATA 0x0664
510 +#define BCMA_CC_PMU_STRAPOPT 0x0668 /* (corerev >= 28) */
511 +#define BCMA_CC_PMU_XTAL_FREQ 0x066C /* (pmurev >= 10) */
512 +#define BCMA_CC_PMU_XTAL_FREQ_ILPCTL_MASK 0x00001FFF
513 +#define BCMA_CC_PMU_XTAL_FREQ_MEASURE_MASK 0x80000000
514 +#define BCMA_CC_PMU_XTAL_FREQ_MEASURE_SHIFT 31
515 #define BCMA_CC_SPROM 0x0800 /* SPROM beginning */
516 /* NAND flash MLC controller registers (corerev >= 38) */
517 #define BCMA_CC_NAND_REVISION 0x0C00
519 #define BCMA_CC_PMU6_4706_PROC_NDIV_MODE_MASK 0x00000007
520 #define BCMA_CC_PMU6_4706_PROC_NDIV_MODE_SHIFT 0
523 +#define BCMA_CC_PMU15_PLL_PLLCTL0 0
524 +#define BCMA_CC_PMU15_PLL_PC0_CLKSEL_MASK 0x00000003
525 +#define BCMA_CC_PMU15_PLL_PC0_CLKSEL_SHIFT 0
526 +#define BCMA_CC_PMU15_PLL_PC0_FREQTGT_MASK 0x003FFFFC
527 +#define BCMA_CC_PMU15_PLL_PC0_FREQTGT_SHIFT 2
528 +#define BCMA_CC_PMU15_PLL_PC0_PRESCALE_MASK 0x00C00000
529 +#define BCMA_CC_PMU15_PLL_PC0_PRESCALE_SHIFT 22
530 +#define BCMA_CC_PMU15_PLL_PC0_KPCTRL_MASK 0x07000000
531 +#define BCMA_CC_PMU15_PLL_PC0_KPCTRL_SHIFT 24
532 +#define BCMA_CC_PMU15_PLL_PC0_FCNTCTRL_MASK 0x38000000
533 +#define BCMA_CC_PMU15_PLL_PC0_FCNTCTRL_SHIFT 27
534 +#define BCMA_CC_PMU15_PLL_PC0_FDCMODE_MASK 0x40000000
535 +#define BCMA_CC_PMU15_PLL_PC0_FDCMODE_SHIFT 30
536 +#define BCMA_CC_PMU15_PLL_PC0_CTRLBIAS_MASK 0x80000000
537 +#define BCMA_CC_PMU15_PLL_PC0_CTRLBIAS_SHIFT 31
539 /* ALP clock on pre-PMU chips */
540 #define BCMA_CC_PMU_ALP_CLOCK 20000000
541 /* HT clock for systems with PMU-enabled chipcommon */
543 #define BCMA_CHIPCTL_5357_I2S_PINS_ENABLE BIT(18)
544 #define BCMA_CHIPCTL_5357_I2CSPI_PINS_ENABLE BIT(19)
546 +#define BCMA_RES_4314_LPLDO_PU BIT(0)
547 +#define BCMA_RES_4314_PMU_SLEEP_DIS BIT(1)
548 +#define BCMA_RES_4314_PMU_BG_PU BIT(2)
549 +#define BCMA_RES_4314_CBUCK_LPOM_PU BIT(3)
550 +#define BCMA_RES_4314_CBUCK_PFM_PU BIT(4)
551 +#define BCMA_RES_4314_CLDO_PU BIT(5)
552 +#define BCMA_RES_4314_LPLDO2_LVM BIT(6)
553 +#define BCMA_RES_4314_WL_PMU_PU BIT(7)
554 +#define BCMA_RES_4314_LNLDO_PU BIT(8)
555 +#define BCMA_RES_4314_LDO3P3_PU BIT(9)
556 +#define BCMA_RES_4314_OTP_PU BIT(10)
557 +#define BCMA_RES_4314_XTAL_PU BIT(11)
558 +#define BCMA_RES_4314_WL_PWRSW_PU BIT(12)
559 +#define BCMA_RES_4314_LQ_AVAIL BIT(13)
560 +#define BCMA_RES_4314_LOGIC_RET BIT(14)
561 +#define BCMA_RES_4314_MEM_SLEEP BIT(15)
562 +#define BCMA_RES_4314_MACPHY_RET BIT(16)
563 +#define BCMA_RES_4314_WL_CORE_READY BIT(17)
564 +#define BCMA_RES_4314_ILP_REQ BIT(18)
565 +#define BCMA_RES_4314_ALP_AVAIL BIT(19)
566 +#define BCMA_RES_4314_MISC_PWRSW_PU BIT(20)
567 +#define BCMA_RES_4314_SYNTH_PWRSW_PU BIT(21)
568 +#define BCMA_RES_4314_RX_PWRSW_PU BIT(22)
569 +#define BCMA_RES_4314_RADIO_PU BIT(23)
570 +#define BCMA_RES_4314_VCO_LDO_PU BIT(24)
571 +#define BCMA_RES_4314_AFE_LDO_PU BIT(25)
572 +#define BCMA_RES_4314_RX_LDO_PU BIT(26)
573 +#define BCMA_RES_4314_TX_LDO_PU BIT(27)
574 +#define BCMA_RES_4314_HT_AVAIL BIT(28)
575 +#define BCMA_RES_4314_MACPHY_CLK_AVAIL BIT(29)
577 /* Data for the PMU, if available.
578 * Check availability with ((struct bcma_chipcommon)->capabilities & BCMA_CC_CAP_PMU)