1 --- a/drivers/ssb/b43_pci_bridge.c
2 +++ b/drivers/ssb/b43_pci_bridge.c
4 * because of its small size we include it in the SSB core
5 * instead of creating a standalone module.
7 - * Copyright 2007 Michael Buesch <mb@bu3sch.de>
8 + * Copyright 2007 Michael Buesch <m@bues.ch>
10 * Licensed under the GNU/GPL. See COPYING for details.
13 #include <linux/pci.h>
14 +#include <linux/module.h>
15 #include <linux/ssb/ssb.h>
17 #include "ssb_private.h"
18 --- a/drivers/ssb/driver_chipcommon.c
19 +++ b/drivers/ssb/driver_chipcommon.c
21 * Broadcom ChipCommon core driver
23 * Copyright 2005, Broadcom Corporation
24 - * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de>
25 + * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
27 * Licensed under the GNU/GPL. See COPYING for details.
29 --- a/drivers/ssb/driver_chipcommon_pmu.c
30 +++ b/drivers/ssb/driver_chipcommon_pmu.c
32 * Sonics Silicon Backplane
33 * Broadcom ChipCommon Power Management Unit driver
35 - * Copyright 2009, Michael Buesch <mb@bu3sch.de>
36 + * Copyright 2009, Michael Buesch <m@bues.ch>
37 * Copyright 2007, Broadcom Corporation
39 * Licensed under the GNU/GPL. See COPYING for details.
41 #include <linux/ssb/ssb_regs.h>
42 #include <linux/ssb/ssb_driver_chipcommon.h>
43 #include <linux/delay.h>
44 +#ifdef CONFIG_BCM47XX
45 +#include <asm/mach-bcm47xx/nvram.h>
48 #include "ssb_private.h"
50 @@ -91,10 +94,6 @@ static void ssb_pmu0_pllinit_r0(struct s
51 u32 pmuctl, tmp, pllctl;
54 - if ((bus->chip_id == 0x5354) && !crystalfreq) {
55 - /* The 5354 crystal freq is 25MHz */
56 - crystalfreq = 25000;
59 e = pmu0_plltab_find_entry(crystalfreq);
61 @@ -320,7 +319,11 @@ static void ssb_pmu_pll_init(struct ssb_
62 u32 crystalfreq = 0; /* in kHz. 0 = keep default freq. */
64 if (bus->bustype == SSB_BUSTYPE_SSB) {
65 - /* TODO: The user may override the crystal frequency. */
66 +#ifdef CONFIG_BCM47XX
68 + if (nvram_getenv("xtalfreq", buf, sizeof(buf)) >= 0)
69 + crystalfreq = simple_strtoul(buf, NULL, 0);
73 switch (bus->chip_id) {
74 @@ -329,7 +332,11 @@ static void ssb_pmu_pll_init(struct ssb_
75 ssb_pmu1_pllinit_r0(cc, crystalfreq);
78 + ssb_pmu0_pllinit_r0(cc, crystalfreq);
81 + if (crystalfreq == 0)
82 + crystalfreq = 25000;
83 ssb_pmu0_pllinit_r0(cc, crystalfreq);
86 @@ -417,9 +424,9 @@ static void ssb_pmu_resources_init(struc
87 u32 min_msk = 0, max_msk = 0;
89 const struct pmu_res_updown_tab_entry *updown_tab = NULL;
90 - unsigned int updown_tab_size;
91 + unsigned int updown_tab_size = 0;
92 const struct pmu_res_depend_tab_entry *depend_tab = NULL;
93 - unsigned int depend_tab_size;
94 + unsigned int depend_tab_size = 0;
96 switch (bus->chip_id) {
98 @@ -606,3 +613,34 @@ void ssb_pmu_set_ldo_paref(struct ssb_ch
100 EXPORT_SYMBOL(ssb_pmu_set_ldo_voltage);
101 EXPORT_SYMBOL(ssb_pmu_set_ldo_paref);
103 +u32 ssb_pmu_get_cpu_clock(struct ssb_chipcommon *cc)
105 + struct ssb_bus *bus = cc->dev->bus;
107 + switch (bus->chip_id) {
109 + /* 5354 chip uses a non programmable PLL of frequency 240MHz */
112 + ssb_printk(KERN_ERR PFX
113 + "ERROR: PMU cpu clock unknown for device %04X\n",
119 +u32 ssb_pmu_get_controlclock(struct ssb_chipcommon *cc)
121 + struct ssb_bus *bus = cc->dev->bus;
123 + switch (bus->chip_id) {
127 + ssb_printk(KERN_ERR PFX
128 + "ERROR: PMU controlclock unknown for device %04X\n",
133 --- a/drivers/ssb/driver_extif.c
134 +++ b/drivers/ssb/driver_extif.c
136 * Broadcom EXTIF core driver
138 * Copyright 2005, Broadcom Corporation
139 - * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de>
140 + * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
141 * Copyright 2006, 2007, Felix Fietkau <nbd@openwrt.org>
142 * Copyright 2007, Aurelien Jarno <aurelien@aurel32.net>
144 --- a/drivers/ssb/driver_gige.c
145 +++ b/drivers/ssb/driver_gige.c
147 * Broadcom Gigabit Ethernet core driver
149 * Copyright 2008, Broadcom Corporation
150 - * Copyright 2008, Michael Buesch <mb@bu3sch.de>
151 + * Copyright 2008, Michael Buesch <m@bues.ch>
153 * Licensed under the GNU/GPL. See COPYING for details.
155 @@ -106,8 +106,9 @@ void gige_pcicfg_write32(struct ssb_gige
156 gige_write32(dev, SSB_GIGE_PCICFG + offset, value);
159 -static int ssb_gige_pci_read_config(struct pci_bus *bus, unsigned int devfn,
160 - int reg, int size, u32 *val)
161 +static int __devinit ssb_gige_pci_read_config(struct pci_bus *bus,
162 + unsigned int devfn, int reg,
163 + int size, u32 *val)
165 struct ssb_gige *dev = container_of(bus->ops, struct ssb_gige, pci_ops);
167 @@ -136,8 +137,9 @@ static int ssb_gige_pci_read_config(stru
168 return PCIBIOS_SUCCESSFUL;
171 -static int ssb_gige_pci_write_config(struct pci_bus *bus, unsigned int devfn,
172 - int reg, int size, u32 val)
173 +static int __devinit ssb_gige_pci_write_config(struct pci_bus *bus,
174 + unsigned int devfn, int reg,
177 struct ssb_gige *dev = container_of(bus->ops, struct ssb_gige, pci_ops);
179 @@ -166,7 +168,8 @@ static int ssb_gige_pci_write_config(str
180 return PCIBIOS_SUCCESSFUL;
183 -static int ssb_gige_probe(struct ssb_device *sdev, const struct ssb_device_id *id)
184 +static int __devinit ssb_gige_probe(struct ssb_device *sdev,
185 + const struct ssb_device_id *id)
187 struct ssb_gige *dev;
188 u32 base, tmslow, tmshigh;
189 --- a/drivers/ssb/driver_mipscore.c
190 +++ b/drivers/ssb/driver_mipscore.c
192 * Broadcom MIPS core driver
194 * Copyright 2005, Broadcom Corporation
195 - * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de>
196 + * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
198 * Licensed under the GNU/GPL. See COPYING for details.
200 @@ -208,6 +208,9 @@ u32 ssb_cpu_clock(struct ssb_mipscore *m
201 struct ssb_bus *bus = mcore->dev->bus;
202 u32 pll_type, n, m, rate = 0;
204 + if (bus->chipco.capabilities & SSB_CHIPCO_CAP_PMU)
205 + return ssb_pmu_get_cpu_clock(&bus->chipco);
207 if (bus->extif.dev) {
208 ssb_extif_get_clockcontrol(&bus->extif, &pll_type, &n, &m);
209 } else if (bus->chipco.dev) {
210 --- a/drivers/ssb/driver_pcicore.c
211 +++ b/drivers/ssb/driver_pcicore.c
213 * Broadcom PCI-core driver
215 * Copyright 2005, Broadcom Corporation
216 - * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de>
217 + * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
219 * Licensed under the GNU/GPL. See COPYING for details.
221 @@ -74,7 +74,7 @@ static u32 get_cfgspace_addr(struct ssb_
224 /* We do only have one cardbus device behind the bridge. */
225 - if (pc->cardbusmode && (dev >= 1))
226 + if (pc->cardbusmode && (dev > 1))
230 @@ -314,7 +314,7 @@ int ssb_pcicore_pcibios_map_irq(const st
231 return ssb_mips_irq(extpci_core->dev) + 2;
234 -static void ssb_pcicore_init_hostmode(struct ssb_pcicore *pc)
235 +static void __devinit ssb_pcicore_init_hostmode(struct ssb_pcicore *pc)
239 @@ -379,7 +379,7 @@ static void ssb_pcicore_init_hostmode(st
240 register_pci_controller(&ssb_pcicore_controller);
243 -static int pcicore_is_in_hostmode(struct ssb_pcicore *pc)
244 +static int __devinit pcicore_is_in_hostmode(struct ssb_pcicore *pc)
246 struct ssb_bus *bus = pc->dev->bus;
248 @@ -412,7 +412,7 @@ static int pcicore_is_in_hostmode(struct
250 **************************************************/
252 -static void ssb_pcicore_fix_sprom_core_index(struct ssb_pcicore *pc)
253 +static void __devinit ssb_pcicore_fix_sprom_core_index(struct ssb_pcicore *pc)
255 u16 tmp = pcicore_read16(pc, SSB_PCICORE_SPROM(0));
256 if (((tmp & 0xF000) >> 12) != pc->dev->core_index) {
257 @@ -514,7 +514,7 @@ static void ssb_pcicore_pcie_setup_worka
258 * Generic and Clientmode operation code.
259 **************************************************/
261 -static void ssb_pcicore_init_clientmode(struct ssb_pcicore *pc)
262 +static void __devinit ssb_pcicore_init_clientmode(struct ssb_pcicore *pc)
264 struct ssb_device *pdev = pc->dev;
265 struct ssb_bus *bus = pdev->bus;
266 --- a/drivers/ssb/embedded.c
267 +++ b/drivers/ssb/embedded.c
269 * Embedded systems support code
271 * Copyright 2005-2008, Broadcom Corporation
272 - * Copyright 2006-2008, Michael Buesch <mb@bu3sch.de>
273 + * Copyright 2006-2008, Michael Buesch <m@bues.ch>
275 * Licensed under the GNU/GPL. See COPYING for details.
277 --- a/drivers/ssb/main.c
278 +++ b/drivers/ssb/main.c
282 * Copyright 2005, Broadcom Corporation
283 - * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de>
284 + * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
286 * Licensed under the GNU/GPL. See COPYING for details.
290 #include <linux/delay.h>
291 #include <linux/io.h>
292 +#include <linux/module.h>
293 #include <linux/ssb/ssb.h>
294 #include <linux/ssb/ssb_regs.h>
295 #include <linux/ssb/ssb_driver_gige.h>
296 @@ -139,19 +140,6 @@ static void ssb_device_put(struct ssb_de
297 put_device(dev->dev);
300 -static inline struct ssb_driver *ssb_driver_get(struct ssb_driver *drv)
303 - get_driver(&drv->drv);
307 -static inline void ssb_driver_put(struct ssb_driver *drv)
310 - put_driver(&drv->drv);
313 static int ssb_device_resume(struct device *dev)
315 struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
316 @@ -249,11 +237,9 @@ int ssb_devices_freeze(struct ssb_bus *b
317 ssb_device_put(sdev);
320 - sdrv = ssb_driver_get(drv_to_ssb_drv(sdev->dev->driver));
321 - if (!sdrv || SSB_WARN_ON(!sdrv->remove)) {
322 - ssb_device_put(sdev);
323 + sdrv = drv_to_ssb_drv(sdev->dev->driver);
324 + if (SSB_WARN_ON(!sdrv->remove))
328 ctx->device_frozen[i] = 1;
330 @@ -292,7 +278,6 @@ int ssb_devices_thaw(struct ssb_freeze_c
331 dev_name(sdev->dev));
334 - ssb_driver_put(sdrv);
335 ssb_device_put(sdev);
338 @@ -557,7 +542,7 @@ error:
341 /* Needs ssb_buses_lock() */
342 -static int ssb_attach_queued_buses(void)
343 +static int __devinit ssb_attach_queued_buses(void)
345 struct ssb_bus *bus, *n;
347 @@ -768,9 +753,9 @@ out:
351 -static int ssb_bus_register(struct ssb_bus *bus,
352 - ssb_invariants_func_t get_invariants,
353 - unsigned long baseaddr)
354 +static int __devinit ssb_bus_register(struct ssb_bus *bus,
355 + ssb_invariants_func_t get_invariants,
356 + unsigned long baseaddr)
360 @@ -851,8 +836,8 @@ err_disable_xtal:
363 #ifdef CONFIG_SSB_PCIHOST
364 -int ssb_bus_pcibus_register(struct ssb_bus *bus,
365 - struct pci_dev *host_pci)
366 +int __devinit ssb_bus_pcibus_register(struct ssb_bus *bus,
367 + struct pci_dev *host_pci)
371 @@ -875,9 +860,9 @@ EXPORT_SYMBOL(ssb_bus_pcibus_register);
372 #endif /* CONFIG_SSB_PCIHOST */
374 #ifdef CONFIG_SSB_PCMCIAHOST
375 -int ssb_bus_pcmciabus_register(struct ssb_bus *bus,
376 - struct pcmcia_device *pcmcia_dev,
377 - unsigned long baseaddr)
378 +int __devinit ssb_bus_pcmciabus_register(struct ssb_bus *bus,
379 + struct pcmcia_device *pcmcia_dev,
380 + unsigned long baseaddr)
384 @@ -897,8 +882,9 @@ EXPORT_SYMBOL(ssb_bus_pcmciabus_register
385 #endif /* CONFIG_SSB_PCMCIAHOST */
387 #ifdef CONFIG_SSB_SDIOHOST
388 -int ssb_bus_sdiobus_register(struct ssb_bus *bus, struct sdio_func *func,
389 - unsigned int quirks)
390 +int __devinit ssb_bus_sdiobus_register(struct ssb_bus *bus,
391 + struct sdio_func *func,
392 + unsigned int quirks)
396 @@ -918,9 +904,9 @@ int ssb_bus_sdiobus_register(struct ssb_
397 EXPORT_SYMBOL(ssb_bus_sdiobus_register);
398 #endif /* CONFIG_SSB_PCMCIAHOST */
400 -int ssb_bus_ssbbus_register(struct ssb_bus *bus,
401 - unsigned long baseaddr,
402 - ssb_invariants_func_t get_invariants)
403 +int __devinit ssb_bus_ssbbus_register(struct ssb_bus *bus,
404 + unsigned long baseaddr,
405 + ssb_invariants_func_t get_invariants)
409 @@ -1001,8 +987,8 @@ u32 ssb_calc_clock_rate(u32 plltype, u32
411 case SSB_PLLTYPE_6: /* 100/200 or 120/240 only */
412 if (m & SSB_CHIPCO_CLK_T6_MMASK)
413 - return SSB_CHIPCO_CLK_T6_M0;
414 - return SSB_CHIPCO_CLK_T6_M1;
415 + return SSB_CHIPCO_CLK_T6_M1;
416 + return SSB_CHIPCO_CLK_T6_M0;
417 case SSB_PLLTYPE_1: /* 48Mhz base, 3 dividers */
418 case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */
419 case SSB_PLLTYPE_4: /* 48Mhz, 4 dividers */
420 @@ -1092,6 +1078,9 @@ u32 ssb_clockspeed(struct ssb_bus *bus)
422 u32 clkctl_n, clkctl_m;
424 + if (bus->chipco.capabilities & SSB_CHIPCO_CAP_PMU)
425 + return ssb_pmu_get_controlclock(&bus->chipco);
427 if (ssb_extif_available(&bus->extif))
428 ssb_extif_get_clockcontrol(&bus->extif, &plltype,
429 &clkctl_n, &clkctl_m);
430 @@ -1259,13 +1248,34 @@ void ssb_device_disable(struct ssb_devic
432 EXPORT_SYMBOL(ssb_device_disable);
434 +/* Some chipsets need routing known for PCIe and 64-bit DMA */
435 +static bool ssb_dma_translation_special_bit(struct ssb_device *dev)
437 + u16 chip_id = dev->bus->chip_id;
439 + if (dev->id.coreid == SSB_DEV_80211) {
440 + return (chip_id == 0x4322 || chip_id == 43221 ||
441 + chip_id == 43231 || chip_id == 43222);
447 u32 ssb_dma_translation(struct ssb_device *dev)
449 switch (dev->bus->bustype) {
450 case SSB_BUSTYPE_SSB:
452 case SSB_BUSTYPE_PCI:
453 - return SSB_PCI_DMA;
454 + if (pci_is_pcie(dev->bus->host_pci) &&
455 + ssb_read32(dev, SSB_TMSHIGH) & SSB_TMSHIGH_DMA64) {
456 + return SSB_PCIE_DMA_H32;
458 + if (ssb_dma_translation_special_bit(dev))
459 + return SSB_PCIE_DMA_H32;
461 + return SSB_PCI_DMA;
464 __ssb_dma_not_implemented(dev);
466 --- a/drivers/ssb/pci.c
467 +++ b/drivers/ssb/pci.c
470 * Sonics Silicon Backplane PCI-Hostbus related functions.
472 - * Copyright (C) 2005-2006 Michael Buesch <mb@bu3sch.de>
473 + * Copyright (C) 2005-2006 Michael Buesch <m@bues.ch>
474 * Copyright (C) 2005 Martin Langer <martin-langer@gmx.de>
475 * Copyright (C) 2005 Stefano Brivio <st3@riseup.net>
476 * Copyright (C) 2005 Danny van Dyk <kugelfang@gentoo.org>
477 @@ -331,7 +331,6 @@ static void sprom_extract_r123(struct ss
484 if (out->revision == 3) /* rev 3 moved MAC */
485 @@ -390,20 +389,12 @@ static void sprom_extract_r123(struct ss
486 SPEX(boardflags_hi, SSB_SPROM2_BFLHI, 0xFFFF, 0);
488 /* Extract the antenna gain values. */
489 - gain = r123_extract_antgain(out->revision, in,
490 - SSB_SPROM1_AGAIN_BG,
491 - SSB_SPROM1_AGAIN_BG_SHIFT);
492 - out->antenna_gain.ghz24.a0 = gain;
493 - out->antenna_gain.ghz24.a1 = gain;
494 - out->antenna_gain.ghz24.a2 = gain;
495 - out->antenna_gain.ghz24.a3 = gain;
496 - gain = r123_extract_antgain(out->revision, in,
497 - SSB_SPROM1_AGAIN_A,
498 - SSB_SPROM1_AGAIN_A_SHIFT);
499 - out->antenna_gain.ghz5.a0 = gain;
500 - out->antenna_gain.ghz5.a1 = gain;
501 - out->antenna_gain.ghz5.a2 = gain;
502 - out->antenna_gain.ghz5.a3 = gain;
503 + out->antenna_gain.a0 = r123_extract_antgain(out->revision, in,
504 + SSB_SPROM1_AGAIN_BG,
505 + SSB_SPROM1_AGAIN_BG_SHIFT);
506 + out->antenna_gain.a1 = r123_extract_antgain(out->revision, in,
507 + SSB_SPROM1_AGAIN_A,
508 + SSB_SPROM1_AGAIN_A_SHIFT);
511 /* Revs 4 5 and 8 have partially shared layout */
512 @@ -504,16 +495,14 @@ static void sprom_extract_r45(struct ssb
515 /* Extract the antenna gain values. */
516 - SPEX(antenna_gain.ghz24.a0, SSB_SPROM4_AGAIN01,
517 + SPEX(antenna_gain.a0, SSB_SPROM4_AGAIN01,
518 SSB_SPROM4_AGAIN0, SSB_SPROM4_AGAIN0_SHIFT);
519 - SPEX(antenna_gain.ghz24.a1, SSB_SPROM4_AGAIN01,
520 + SPEX(antenna_gain.a1, SSB_SPROM4_AGAIN01,
521 SSB_SPROM4_AGAIN1, SSB_SPROM4_AGAIN1_SHIFT);
522 - SPEX(antenna_gain.ghz24.a2, SSB_SPROM4_AGAIN23,
523 + SPEX(antenna_gain.a2, SSB_SPROM4_AGAIN23,
524 SSB_SPROM4_AGAIN2, SSB_SPROM4_AGAIN2_SHIFT);
525 - SPEX(antenna_gain.ghz24.a3, SSB_SPROM4_AGAIN23,
526 + SPEX(antenna_gain.a3, SSB_SPROM4_AGAIN23,
527 SSB_SPROM4_AGAIN3, SSB_SPROM4_AGAIN3_SHIFT);
528 - memcpy(&out->antenna_gain.ghz5, &out->antenna_gain.ghz24,
529 - sizeof(out->antenna_gain.ghz5));
531 sprom_extract_r458(out, in);
533 @@ -523,7 +512,13 @@ static void sprom_extract_r45(struct ssb
534 static void sprom_extract_r8(struct ssb_sprom *out, const u16 *in)
539 + u16 pwr_info_offset[] = {
540 + SSB_SROM8_PWR_INFO_CORE0, SSB_SROM8_PWR_INFO_CORE1,
541 + SSB_SROM8_PWR_INFO_CORE2, SSB_SROM8_PWR_INFO_CORE3
543 + BUILD_BUG_ON(ARRAY_SIZE(pwr_info_offset) !=
544 + ARRAY_SIZE(out->core_pwr_info));
546 /* extract the MAC address */
547 for (i = 0; i < 3; i++) {
548 @@ -596,16 +591,69 @@ static void sprom_extract_r8(struct ssb_
549 SPEX32(ofdm5ghpo, SSB_SPROM8_OFDM5GHPO, 0xFFFFFFFF, 0);
551 /* Extract the antenna gain values. */
552 - SPEX(antenna_gain.ghz24.a0, SSB_SPROM8_AGAIN01,
553 + SPEX(antenna_gain.a0, SSB_SPROM8_AGAIN01,
554 SSB_SPROM8_AGAIN0, SSB_SPROM8_AGAIN0_SHIFT);
555 - SPEX(antenna_gain.ghz24.a1, SSB_SPROM8_AGAIN01,
556 + SPEX(antenna_gain.a1, SSB_SPROM8_AGAIN01,
557 SSB_SPROM8_AGAIN1, SSB_SPROM8_AGAIN1_SHIFT);
558 - SPEX(antenna_gain.ghz24.a2, SSB_SPROM8_AGAIN23,
559 + SPEX(antenna_gain.a2, SSB_SPROM8_AGAIN23,
560 SSB_SPROM8_AGAIN2, SSB_SPROM8_AGAIN2_SHIFT);
561 - SPEX(antenna_gain.ghz24.a3, SSB_SPROM8_AGAIN23,
562 + SPEX(antenna_gain.a3, SSB_SPROM8_AGAIN23,
563 SSB_SPROM8_AGAIN3, SSB_SPROM8_AGAIN3_SHIFT);
564 - memcpy(&out->antenna_gain.ghz5, &out->antenna_gain.ghz24,
565 - sizeof(out->antenna_gain.ghz5));
567 + /* Extract cores power info info */
568 + for (i = 0; i < ARRAY_SIZE(pwr_info_offset); i++) {
569 + o = pwr_info_offset[i];
570 + SPEX(core_pwr_info[i].itssi_2g, o + SSB_SROM8_2G_MAXP_ITSSI,
571 + SSB_SPROM8_2G_ITSSI, SSB_SPROM8_2G_ITSSI_SHIFT);
572 + SPEX(core_pwr_info[i].maxpwr_2g, o + SSB_SROM8_2G_MAXP_ITSSI,
573 + SSB_SPROM8_2G_MAXP, 0);
575 + SPEX(core_pwr_info[i].pa_2g[0], o + SSB_SROM8_2G_PA_0, ~0, 0);
576 + SPEX(core_pwr_info[i].pa_2g[1], o + SSB_SROM8_2G_PA_1, ~0, 0);
577 + SPEX(core_pwr_info[i].pa_2g[2], o + SSB_SROM8_2G_PA_2, ~0, 0);
579 + SPEX(core_pwr_info[i].itssi_5g, o + SSB_SROM8_5G_MAXP_ITSSI,
580 + SSB_SPROM8_5G_ITSSI, SSB_SPROM8_5G_ITSSI_SHIFT);
581 + SPEX(core_pwr_info[i].maxpwr_5g, o + SSB_SROM8_5G_MAXP_ITSSI,
582 + SSB_SPROM8_5G_MAXP, 0);
583 + SPEX(core_pwr_info[i].maxpwr_5gh, o + SSB_SPROM8_5GHL_MAXP,
584 + SSB_SPROM8_5GH_MAXP, 0);
585 + SPEX(core_pwr_info[i].maxpwr_5gl, o + SSB_SPROM8_5GHL_MAXP,
586 + SSB_SPROM8_5GL_MAXP, SSB_SPROM8_5GL_MAXP_SHIFT);
588 + SPEX(core_pwr_info[i].pa_5gl[0], o + SSB_SROM8_5GL_PA_0, ~0, 0);
589 + SPEX(core_pwr_info[i].pa_5gl[1], o + SSB_SROM8_5GL_PA_1, ~0, 0);
590 + SPEX(core_pwr_info[i].pa_5gl[2], o + SSB_SROM8_5GL_PA_2, ~0, 0);
591 + SPEX(core_pwr_info[i].pa_5g[0], o + SSB_SROM8_5G_PA_0, ~0, 0);
592 + SPEX(core_pwr_info[i].pa_5g[1], o + SSB_SROM8_5G_PA_1, ~0, 0);
593 + SPEX(core_pwr_info[i].pa_5g[2], o + SSB_SROM8_5G_PA_2, ~0, 0);
594 + SPEX(core_pwr_info[i].pa_5gh[0], o + SSB_SROM8_5GH_PA_0, ~0, 0);
595 + SPEX(core_pwr_info[i].pa_5gh[1], o + SSB_SROM8_5GH_PA_1, ~0, 0);
596 + SPEX(core_pwr_info[i].pa_5gh[2], o + SSB_SROM8_5GH_PA_2, ~0, 0);
599 + /* Extract FEM info */
600 + SPEX(fem.ghz2.tssipos, SSB_SPROM8_FEM2G,
601 + SSB_SROM8_FEM_TSSIPOS, SSB_SROM8_FEM_TSSIPOS_SHIFT);
602 + SPEX(fem.ghz2.extpa_gain, SSB_SPROM8_FEM2G,
603 + SSB_SROM8_FEM_EXTPA_GAIN, SSB_SROM8_FEM_EXTPA_GAIN_SHIFT);
604 + SPEX(fem.ghz2.pdet_range, SSB_SPROM8_FEM2G,
605 + SSB_SROM8_FEM_PDET_RANGE, SSB_SROM8_FEM_PDET_RANGE_SHIFT);
606 + SPEX(fem.ghz2.tr_iso, SSB_SPROM8_FEM2G,
607 + SSB_SROM8_FEM_TR_ISO, SSB_SROM8_FEM_TR_ISO_SHIFT);
608 + SPEX(fem.ghz2.antswlut, SSB_SPROM8_FEM2G,
609 + SSB_SROM8_FEM_ANTSWLUT, SSB_SROM8_FEM_ANTSWLUT_SHIFT);
611 + SPEX(fem.ghz5.tssipos, SSB_SPROM8_FEM5G,
612 + SSB_SROM8_FEM_TSSIPOS, SSB_SROM8_FEM_TSSIPOS_SHIFT);
613 + SPEX(fem.ghz5.extpa_gain, SSB_SPROM8_FEM5G,
614 + SSB_SROM8_FEM_EXTPA_GAIN, SSB_SROM8_FEM_EXTPA_GAIN_SHIFT);
615 + SPEX(fem.ghz5.pdet_range, SSB_SPROM8_FEM5G,
616 + SSB_SROM8_FEM_PDET_RANGE, SSB_SROM8_FEM_PDET_RANGE_SHIFT);
617 + SPEX(fem.ghz5.tr_iso, SSB_SPROM8_FEM5G,
618 + SSB_SROM8_FEM_TR_ISO, SSB_SROM8_FEM_TR_ISO_SHIFT);
619 + SPEX(fem.ghz5.antswlut, SSB_SPROM8_FEM5G,
620 + SSB_SROM8_FEM_ANTSWLUT, SSB_SROM8_FEM_ANTSWLUT_SHIFT);
622 sprom_extract_r458(out, in);
624 @@ -734,12 +782,9 @@ out_free:
625 static void ssb_pci_get_boardinfo(struct ssb_bus *bus,
626 struct ssb_boardinfo *bi)
628 - pci_read_config_word(bus->host_pci, PCI_SUBSYSTEM_VENDOR_ID,
630 - pci_read_config_word(bus->host_pci, PCI_SUBSYSTEM_ID,
632 - pci_read_config_word(bus->host_pci, PCI_REVISION_ID,
634 + bi->vendor = bus->host_pci->subsystem_vendor;
635 + bi->type = bus->host_pci->subsystem_device;
636 + bi->rev = bus->host_pci->revision;
639 int ssb_pci_get_invariants(struct ssb_bus *bus,
640 --- a/drivers/ssb/pcihost_wrapper.c
641 +++ b/drivers/ssb/pcihost_wrapper.c
643 * Copyright (c) 2005 Stefano Brivio <st3@riseup.net>
644 * Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org>
645 * Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
646 - * Copyright (c) 2005-2007 Michael Buesch <mbuesch@freenet.de>
647 + * Copyright (c) 2005-2007 Michael Buesch <m@bues.ch>
649 * Licensed under the GNU/GPL. See COPYING for details.
651 @@ -53,8 +53,8 @@ static int ssb_pcihost_resume(struct pci
652 # define ssb_pcihost_resume NULL
653 #endif /* CONFIG_PM */
655 -static int ssb_pcihost_probe(struct pci_dev *dev,
656 - const struct pci_device_id *id)
657 +static int __devinit ssb_pcihost_probe(struct pci_dev *dev,
658 + const struct pci_device_id *id)
662 @@ -110,7 +110,7 @@ static void ssb_pcihost_remove(struct pc
663 pci_set_drvdata(dev, NULL);
666 -int ssb_pcihost_register(struct pci_driver *driver)
667 +int __devinit ssb_pcihost_register(struct pci_driver *driver)
669 driver->probe = ssb_pcihost_probe;
670 driver->remove = ssb_pcihost_remove;
671 --- a/drivers/ssb/pcmcia.c
672 +++ b/drivers/ssb/pcmcia.c
674 * PCMCIA-Hostbus related functions
676 * Copyright 2006 Johannes Berg <johannes@sipsolutions.net>
677 - * Copyright 2007-2008 Michael Buesch <mb@bu3sch.de>
678 + * Copyright 2007-2008 Michael Buesch <m@bues.ch>
680 * Licensed under the GNU/GPL. See COPYING for details.
682 @@ -676,14 +676,10 @@ static int ssb_pcmcia_do_get_invariants(
683 case SSB_PCMCIA_CIS_ANTGAIN:
684 GOTO_ERROR_ON(tuple->TupleDataLen != 2,
686 - sprom->antenna_gain.ghz24.a0 = tuple->TupleData[1];
687 - sprom->antenna_gain.ghz24.a1 = tuple->TupleData[1];
688 - sprom->antenna_gain.ghz24.a2 = tuple->TupleData[1];
689 - sprom->antenna_gain.ghz24.a3 = tuple->TupleData[1];
690 - sprom->antenna_gain.ghz5.a0 = tuple->TupleData[1];
691 - sprom->antenna_gain.ghz5.a1 = tuple->TupleData[1];
692 - sprom->antenna_gain.ghz5.a2 = tuple->TupleData[1];
693 - sprom->antenna_gain.ghz5.a3 = tuple->TupleData[1];
694 + sprom->antenna_gain.a0 = tuple->TupleData[1];
695 + sprom->antenna_gain.a1 = tuple->TupleData[1];
696 + sprom->antenna_gain.a2 = tuple->TupleData[1];
697 + sprom->antenna_gain.a3 = tuple->TupleData[1];
699 case SSB_PCMCIA_CIS_BFLAGS:
700 GOTO_ERROR_ON((tuple->TupleDataLen != 3) &&
701 --- a/drivers/ssb/scan.c
702 +++ b/drivers/ssb/scan.c
704 * Sonics Silicon Backplane
707 - * Copyright (C) 2005-2007 Michael Buesch <mb@bu3sch.de>
708 + * Copyright (C) 2005-2007 Michael Buesch <m@bues.ch>
709 * Copyright (C) 2005 Martin Langer <martin-langer@gmx.de>
710 * Copyright (C) 2005 Stefano Brivio <st3@riseup.net>
711 * Copyright (C) 2005 Danny van Dyk <kugelfang@gentoo.org>
712 @@ -310,8 +310,7 @@ int ssb_bus_scan(struct ssb_bus *bus,
714 if (bus->bustype == SSB_BUSTYPE_PCI) {
715 bus->chip_id = pcidev_to_chipid(bus->host_pci);
716 - pci_read_config_byte(bus->host_pci, PCI_REVISION_ID,
718 + bus->chip_rev = bus->host_pci->revision;
719 bus->chip_package = 0;
721 bus->chip_id = 0x4710;
722 @@ -319,6 +318,9 @@ int ssb_bus_scan(struct ssb_bus *bus,
723 bus->chip_package = 0;
726 + ssb_printk(KERN_INFO PFX "Found chip with id 0x%04X, rev 0x%02X and "
727 + "package 0x%02X\n", bus->chip_id, bus->chip_rev,
728 + bus->chip_package);
729 if (!bus->nr_devices)
730 bus->nr_devices = chipid_to_nrcores(bus->chip_id);
731 if (bus->nr_devices > ARRAY_SIZE(bus->devices)) {
732 --- a/drivers/ssb/sdio.c
733 +++ b/drivers/ssb/sdio.c
736 * Based on drivers/ssb/pcmcia.c
737 * Copyright 2006 Johannes Berg <johannes@sipsolutions.net>
738 - * Copyright 2007-2008 Michael Buesch <mb@bu3sch.de>
739 + * Copyright 2007-2008 Michael Buesch <m@bues.ch>
741 * Licensed under the GNU/GPL. See COPYING for details.
743 @@ -551,14 +551,10 @@ int ssb_sdio_get_invariants(struct ssb_b
744 case SSB_SDIO_CIS_ANTGAIN:
745 GOTO_ERROR_ON(tuple->size != 2,
747 - sprom->antenna_gain.ghz24.a0 = tuple->data[1];
748 - sprom->antenna_gain.ghz24.a1 = tuple->data[1];
749 - sprom->antenna_gain.ghz24.a2 = tuple->data[1];
750 - sprom->antenna_gain.ghz24.a3 = tuple->data[1];
751 - sprom->antenna_gain.ghz5.a0 = tuple->data[1];
752 - sprom->antenna_gain.ghz5.a1 = tuple->data[1];
753 - sprom->antenna_gain.ghz5.a2 = tuple->data[1];
754 - sprom->antenna_gain.ghz5.a3 = tuple->data[1];
755 + sprom->antenna_gain.a0 = tuple->data[1];
756 + sprom->antenna_gain.a1 = tuple->data[1];
757 + sprom->antenna_gain.a2 = tuple->data[1];
758 + sprom->antenna_gain.a3 = tuple->data[1];
760 case SSB_SDIO_CIS_BFLAGS:
761 GOTO_ERROR_ON((tuple->size != 3) &&
762 --- a/drivers/ssb/sprom.c
763 +++ b/drivers/ssb/sprom.c
765 * Sonics Silicon Backplane
766 * Common SPROM support routines
768 - * Copyright (C) 2005-2008 Michael Buesch <mb@bu3sch.de>
769 + * Copyright (C) 2005-2008 Michael Buesch <m@bues.ch>
770 * Copyright (C) 2005 Martin Langer <martin-langer@gmx.de>
771 * Copyright (C) 2005 Stefano Brivio <st3@riseup.net>
772 * Copyright (C) 2005 Danny van Dyk <kugelfang@gentoo.org>
773 --- a/include/linux/ssb/ssb.h
774 +++ b/include/linux/ssb/ssb.h
775 @@ -16,6 +16,12 @@ struct pcmcia_device;
779 +struct ssb_sprom_core_pwr_info {
780 + u8 itssi_2g, itssi_5g;
781 + u8 maxpwr_2g, maxpwr_5gl, maxpwr_5g, maxpwr_5gh;
782 + u16 pa_2g[4], pa_5gl[4], pa_5g[4], pa_5gh[4];
787 u8 il0mac[6]; /* MAC address for 802.11b/g */
788 @@ -25,8 +31,13 @@ struct ssb_sprom {
789 u8 et1phyaddr; /* MII address for enet1 */
790 u8 et0mdcport; /* MDIO for enet0 */
791 u8 et1mdcport; /* MDIO for enet1 */
792 - u8 board_rev; /* Board revision number from SPROM. */
793 + u16 board_rev; /* Board revision number from SPROM. */
794 + u16 board_num; /* Board number from SPROM. */
795 + u16 board_type; /* Board type from SPROM. */
796 u8 country_code; /* Country Code */
797 + char alpha2[2]; /* Country Code as two chars like EU or US */
798 + u8 leddc_on_time; /* LED Powersave Duty Cycle On Count */
799 + u8 leddc_off_time; /* LED Powersave Duty Cycle Off Count */
800 u8 ant_available_a; /* 2GHz antenna available bits (up to 4) */
801 u8 ant_available_bg; /* 5GHz antenna available bits (up to 4) */
803 @@ -45,10 +56,10 @@ struct ssb_sprom {
804 u8 gpio1; /* GPIO pin 1 */
805 u8 gpio2; /* GPIO pin 2 */
806 u8 gpio3; /* GPIO pin 3 */
807 - u16 maxpwr_bg; /* 2.4GHz Amplifier Max Power (in dBm Q5.2) */
808 - u16 maxpwr_al; /* 5.2GHz Amplifier Max Power (in dBm Q5.2) */
809 - u16 maxpwr_a; /* 5.3GHz Amplifier Max Power (in dBm Q5.2) */
810 - u16 maxpwr_ah; /* 5.8GHz Amplifier Max Power (in dBm Q5.2) */
811 + u8 maxpwr_bg; /* 2.4GHz Amplifier Max Power (in dBm Q5.2) */
812 + u8 maxpwr_al; /* 5.2GHz Amplifier Max Power (in dBm Q5.2) */
813 + u8 maxpwr_a; /* 5.3GHz Amplifier Max Power (in dBm Q5.2) */
814 + u8 maxpwr_ah; /* 5.8GHz Amplifier Max Power (in dBm Q5.2) */
815 u8 itssi_a; /* Idle TSSI Target for A-PHY */
816 u8 itssi_bg; /* Idle TSSI Target for B/G-PHY */
817 u8 tri2g; /* 2.4GHz TX isolation */
818 @@ -59,8 +70,8 @@ struct ssb_sprom {
819 u8 txpid5gl[4]; /* 4.9 - 5.1GHz TX power index */
820 u8 txpid5g[4]; /* 5.1 - 5.5GHz TX power index */
821 u8 txpid5gh[4]; /* 5.5 - ...GHz TX power index */
822 - u8 rxpo2g; /* 2GHz RX power offset */
823 - u8 rxpo5g; /* 5GHz RX power offset */
824 + s8 rxpo2g; /* 2GHz RX power offset */
825 + s8 rxpo5g; /* 5GHz RX power offset */
826 u8 rssisav2g; /* 2GHz RSSI params */
829 @@ -80,26 +91,104 @@ struct ssb_sprom {
830 u16 boardflags2_hi; /* Board flags (bits 48-63) */
831 /* TODO store board flags in a single u64 */
833 + struct ssb_sprom_core_pwr_info core_pwr_info[4];
835 /* Antenna gain values for up to 4 antennas
836 * on each band. Values in dBm/4 (Q5.2). Negative gain means the
837 * loss in the connectors is bigger than the gain. */
841 - } ghz24; /* 2.4GHz band */
844 - } ghz5; /* 5GHz band */
848 - /* TODO - add any parameters needed from rev 2, 3, 4, 5 or 8 SPROMs */
851 + u8 tssipos, extpa_gain, pdet_range, tr_iso, antswlut;
854 + u8 tssipos, extpa_gain, pdet_range, tr_iso, antswlut;
864 + u8 rxgainerr2ga[3];
865 + u8 rxgainerr5gla[3];
866 + u8 rxgainerr5gma[3];
867 + u8 rxgainerr5gha[3];
868 + u8 rxgainerr5gua[3];
871 + u8 noiselvl5gla[3];
872 + u8 noiselvl5gma[3];
873 + u8 noiselvl5gha[3];
874 + u8 noiselvl5gua[3];
889 + u8 tempsense_slope;
891 + u8 tempsense_option;
892 + u8 freqoffset_corr;
897 + u8 phycal_tempdelta;
899 + u8 temps_hysteresis;
902 + u8 pcieingress_war;
904 + /* power per rate from sromrev 9 */
907 + u32 legofdmbw202gpo;
908 + u32 legofdmbw20ul2gpo;
909 + u32 legofdmbw205glpo;
910 + u32 legofdmbw20ul5glpo;
911 + u32 legofdmbw205gmpo;
912 + u32 legofdmbw20ul5gmpo;
913 + u32 legofdmbw205ghpo;
914 + u32 legofdmbw20ul5ghpo;
919 + u32 mcsbw20ul5glpo;
922 + u32 mcsbw20ul5gmpo;
925 + u32 mcsbw20ul5ghpo;
928 + u16 legofdm40duppo;
933 /* Information about the PCB the circuitry is soldered on. */
934 struct ssb_boardinfo {
942 @@ -229,10 +318,9 @@ struct ssb_driver {
943 #define drv_to_ssb_drv(_drv) container_of(_drv, struct ssb_driver, drv)
945 extern int __ssb_driver_register(struct ssb_driver *drv, struct module *owner);
946 -static inline int ssb_driver_register(struct ssb_driver *drv)
948 - return __ssb_driver_register(drv, THIS_MODULE);
950 +#define ssb_driver_register(drv) \
951 + __ssb_driver_register(drv, THIS_MODULE)
953 extern void ssb_driver_unregister(struct ssb_driver *drv);
956 --- a/include/linux/ssb/ssb_driver_chipcommon.h
957 +++ b/include/linux/ssb/ssb_driver_chipcommon.h
959 * gpio interface, extbus, and support for serial and parallel flashes.
961 * Copyright 2005, Broadcom Corporation
962 - * Copyright 2006, Michael Buesch <mb@bu3sch.de>
963 + * Copyright 2006, Michael Buesch <m@bues.ch>
965 * Licensed under the GPL version 2. See COPYING for details.
967 --- a/include/linux/ssb/ssb_regs.h
968 +++ b/include/linux/ssb/ssb_regs.h
970 #define SSB_SPROM8_RXPO2G 0x00FF /* 2GHz RX power offset */
971 #define SSB_SPROM8_RXPO5G 0xFF00 /* 5GHz RX power offset */
972 #define SSB_SPROM8_RXPO5G_SHIFT 8
973 +#define SSB_SPROM8_FEM2G 0x00AE
974 +#define SSB_SPROM8_FEM5G 0x00B0
975 +#define SSB_SROM8_FEM_TSSIPOS 0x0001
976 +#define SSB_SROM8_FEM_TSSIPOS_SHIFT 0
977 +#define SSB_SROM8_FEM_EXTPA_GAIN 0x0006
978 +#define SSB_SROM8_FEM_EXTPA_GAIN_SHIFT 1
979 +#define SSB_SROM8_FEM_PDET_RANGE 0x00F8
980 +#define SSB_SROM8_FEM_PDET_RANGE_SHIFT 3
981 +#define SSB_SROM8_FEM_TR_ISO 0x0700
982 +#define SSB_SROM8_FEM_TR_ISO_SHIFT 8
983 +#define SSB_SROM8_FEM_ANTSWLUT 0xF800
984 +#define SSB_SROM8_FEM_ANTSWLUT_SHIFT 11
985 +#define SSB_SPROM8_THERMAL 0x00B2
986 +#define SSB_SPROM8_MPWR_RAWTS 0x00B4
987 +#define SSB_SPROM8_TS_SLP_OPT_CORRX 0x00B6
988 +#define SSB_SPROM8_FOC_HWIQ_IQSWP 0x00B8
989 +#define SSB_SPROM8_PHYCAL_TEMPDELTA 0x00BA
991 +/* There are 4 blocks with power info sharing the same layout */
992 +#define SSB_SROM8_PWR_INFO_CORE0 0x00C0
993 +#define SSB_SROM8_PWR_INFO_CORE1 0x00E0
994 +#define SSB_SROM8_PWR_INFO_CORE2 0x0100
995 +#define SSB_SROM8_PWR_INFO_CORE3 0x0120
997 +#define SSB_SROM8_2G_MAXP_ITSSI 0x00
998 +#define SSB_SPROM8_2G_MAXP 0x00FF
999 +#define SSB_SPROM8_2G_ITSSI 0xFF00
1000 +#define SSB_SPROM8_2G_ITSSI_SHIFT 8
1001 +#define SSB_SROM8_2G_PA_0 0x02 /* 2GHz power amp settings */
1002 +#define SSB_SROM8_2G_PA_1 0x04
1003 +#define SSB_SROM8_2G_PA_2 0x06
1004 +#define SSB_SROM8_5G_MAXP_ITSSI 0x08 /* 5GHz ITSSI and 5.3GHz Max Power */
1005 +#define SSB_SPROM8_5G_MAXP 0x00FF
1006 +#define SSB_SPROM8_5G_ITSSI 0xFF00
1007 +#define SSB_SPROM8_5G_ITSSI_SHIFT 8
1008 +#define SSB_SPROM8_5GHL_MAXP 0x0A /* 5.2GHz and 5.8GHz Max Power */
1009 +#define SSB_SPROM8_5GH_MAXP 0x00FF
1010 +#define SSB_SPROM8_5GL_MAXP 0xFF00
1011 +#define SSB_SPROM8_5GL_MAXP_SHIFT 8
1012 +#define SSB_SROM8_5G_PA_0 0x0C /* 5.3GHz power amp settings */
1013 +#define SSB_SROM8_5G_PA_1 0x0E
1014 +#define SSB_SROM8_5G_PA_2 0x10
1015 +#define SSB_SROM8_5GL_PA_0 0x12 /* 5.2GHz power amp settings */
1016 +#define SSB_SROM8_5GL_PA_1 0x14
1017 +#define SSB_SROM8_5GL_PA_2 0x16
1018 +#define SSB_SROM8_5GH_PA_0 0x18 /* 5.8GHz power amp settings */
1019 +#define SSB_SROM8_5GH_PA_1 0x1A
1020 +#define SSB_SROM8_5GH_PA_2 0x1C
1022 +/* TODO: Make it deprecated */
1023 #define SSB_SPROM8_MAXP_BG 0x00C0 /* Max Power 2GHz in path 1 */
1024 #define SSB_SPROM8_MAXP_BG_MASK 0x00FF /* Mask for Max Power 2GHz */
1025 #define SSB_SPROM8_ITSSI_BG 0xFF00 /* Mask for path 1 itssi_bg */
1026 @@ -456,12 +506,53 @@
1027 #define SSB_SPROM8_PA1HIB0 0x00D8 /* 5.8GHz power amp settings */
1028 #define SSB_SPROM8_PA1HIB1 0x00DA
1029 #define SSB_SPROM8_PA1HIB2 0x00DC
1031 #define SSB_SPROM8_CCK2GPO 0x0140 /* CCK power offset */
1032 #define SSB_SPROM8_OFDM2GPO 0x0142 /* 2.4GHz OFDM power offset */
1033 #define SSB_SPROM8_OFDM5GPO 0x0146 /* 5.3GHz OFDM power offset */
1034 #define SSB_SPROM8_OFDM5GLPO 0x014A /* 5.2GHz OFDM power offset */
1035 #define SSB_SPROM8_OFDM5GHPO 0x014E /* 5.8GHz OFDM power offset */
1037 +/* Values for boardflags_lo read from SPROM */
1038 +#define SSB_BFL_BTCOEXIST 0x0001 /* implements Bluetooth coexistance */
1039 +#define SSB_BFL_PACTRL 0x0002 /* GPIO 9 controlling the PA */
1040 +#define SSB_BFL_AIRLINEMODE 0x0004 /* implements GPIO 13 radio disable indication */
1041 +#define SSB_BFL_RSSI 0x0008 /* software calculates nrssi slope. */
1042 +#define SSB_BFL_ENETSPI 0x0010 /* has ephy roboswitch spi */
1043 +#define SSB_BFL_XTAL_NOSLOW 0x0020 /* no slow clock available */
1044 +#define SSB_BFL_CCKHIPWR 0x0040 /* can do high power CCK transmission */
1045 +#define SSB_BFL_ENETADM 0x0080 /* has ADMtek switch */
1046 +#define SSB_BFL_ENETVLAN 0x0100 /* can do vlan */
1047 +#define SSB_BFL_AFTERBURNER 0x0200 /* supports Afterburner mode */
1048 +#define SSB_BFL_NOPCI 0x0400 /* board leaves PCI floating */
1049 +#define SSB_BFL_FEM 0x0800 /* supports the Front End Module */
1050 +#define SSB_BFL_EXTLNA 0x1000 /* has an external LNA */
1051 +#define SSB_BFL_HGPA 0x2000 /* had high gain PA */
1052 +#define SSB_BFL_BTCMOD 0x4000 /* BFL_BTCOEXIST is given in alternate GPIOs */
1053 +#define SSB_BFL_ALTIQ 0x8000 /* alternate I/Q settings */
1055 +/* Values for boardflags_hi read from SPROM */
1056 +#define SSB_BFH_NOPA 0x0001 /* has no PA */
1057 +#define SSB_BFH_RSSIINV 0x0002 /* RSSI uses positive slope (not TSSI) */
1058 +#define SSB_BFH_PAREF 0x0004 /* uses the PARef LDO */
1059 +#define SSB_BFH_3TSWITCH 0x0008 /* uses a triple throw switch shared with bluetooth */
1060 +#define SSB_BFH_PHASESHIFT 0x0010 /* can support phase shifter */
1061 +#define SSB_BFH_BUCKBOOST 0x0020 /* has buck/booster */
1062 +#define SSB_BFH_FEM_BT 0x0040 /* has FEM and switch to share antenna with bluetooth */
1064 +/* Values for boardflags2_lo read from SPROM */
1065 +#define SSB_BFL2_RXBB_INT_REG_DIS 0x0001 /* external RX BB regulator present */
1066 +#define SSB_BFL2_APLL_WAR 0x0002 /* alternative A-band PLL settings implemented */
1067 +#define SSB_BFL2_TXPWRCTRL_EN 0x0004 /* permits enabling TX Power Control */
1068 +#define SSB_BFL2_2X4_DIV 0x0008 /* 2x4 diversity switch */
1069 +#define SSB_BFL2_5G_PWRGAIN 0x0010 /* supports 5G band power gain */
1070 +#define SSB_BFL2_PCIEWAR_OVR 0x0020 /* overrides ASPM and Clkreq settings */
1071 +#define SSB_BFL2_CAESERS_BRD 0x0040 /* is Caesers board (unused) */
1072 +#define SSB_BFL2_BTC3WIRE 0x0080 /* used 3-wire bluetooth coexist */
1073 +#define SSB_BFL2_SKWRKFEM_BRD 0x0100 /* 4321mcm93 uses Skyworks FEM */
1074 +#define SSB_BFL2_SPUR_WAR 0x0200 /* has a workaround for clock-harmonic spurs */
1075 +#define SSB_BFL2_GPLL_WAR 0x0400 /* altenative G-band PLL settings implemented */
1077 /* Values for SSB_SPROM1_BINF_CCODE */
1079 SSB_SPROM1CCODE_WORLD = 0,
1080 --- a/drivers/ssb/ssb_private.h
1081 +++ b/drivers/ssb/ssb_private.h
1082 @@ -207,4 +207,8 @@ static inline void b43_pci_ssb_bridge_ex
1084 #endif /* CONFIG_SSB_B43_PCI_BRIDGE */
1086 +/* driver_chipcommon_pmu.c */
1087 +extern u32 ssb_pmu_get_cpu_clock(struct ssb_chipcommon *cc);
1088 +extern u32 ssb_pmu_get_controlclock(struct ssb_chipcommon *cc);
1090 #endif /* LINUX_SSB_PRIVATE_H_ */
1091 --- a/include/linux/ssb/ssb_driver_gige.h
1092 +++ b/include/linux/ssb/ssb_driver_gige.h
1094 #define LINUX_SSB_DRIVER_GIGE_H_
1096 #include <linux/ssb/ssb.h>
1097 +#include <linux/bug.h>
1098 #include <linux/pci.h>
1099 #include <linux/spinlock.h>