1 // SPDX-License-Identifier: GPL-2.0-only
3 * Driver for MikroTik RouterBoot soft config.
5 * Copyright (C) 2020 Thibaut VARĂˆNE <hacks+kernel@slashdirt.org>
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published
9 * by the Free Software Foundation.
11 * This driver exposes the data encoded in the "soft_config" flash segment of
12 * MikroTik RouterBOARDs devices. It presents the data in a sysfs folder
13 * named "soft_config". The data is presented in a user/machine-friendly way
14 * with just as much parsing as can be generalized across mikrotik platforms
15 * (as inferred from reverse-engineering).
17 * The known soft_config tags are presented in the "soft_config" sysfs folder,
18 * with the addition of one specific file named "commit", which is only
19 * available if the driver supports writes to the mtd device: no modifications
20 * made to any of the other attributes are actually written back to flash media
21 * until a true value is input into this file (e.g. [Yy1]). This is to avoid
22 * unnecessary flash wear, and to permit to revert all changes by issuing a
23 * false value ([Nn0]). Reading the content of this file shows the current
24 * status of the driver: if the data in sysfs matches the content of the
25 * soft_config partition, the file will read "clean". Otherwise, it will read
28 * The writeable sysfs files presented by this driver will accept only inputs
29 * which are in a valid range for the given tag. As a design choice, the driver
30 * will not assess whether the inputs are identical to the existing data.
32 * Note: PAGE_SIZE is assumed to be >= 4K, hence the device attribute show
33 * routines need not check for output overflow.
35 * Some constant defines extracted from rbcfg.h by Gabor Juhos
36 * <juhosg@openwrt.org>
39 #include <linux/types.h>
40 #include <linux/init.h>
41 #include <linux/kernel.h>
42 #include <linux/slab.h>
43 #include <linux/errno.h>
44 #include <linux/kobject.h>
45 #include <linux/string.h>
46 #include <linux/mtd/mtd.h>
47 #include <linux/sysfs.h>
48 #include <linux/version.h>
49 #include <linux/capability.h>
50 #include <linux/spinlock.h>
51 #include <linux/crc32.h>
54 #include <asm/mach-ath79/ath79.h>
57 #include "routerboot.h"
59 #define RB_SOFTCONFIG_VER "0.02"
60 #define RB_SC_PR_PFX "[rb_softconfig] "
63 * mtd operations before 4.17 are asynchronous, not handled by this code
64 * Also make the driver act read-only if 4K_SECTORS are not enabled, since they
65 * are require to handle partial erasing of the small soft_config partition.
67 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 17, 0)) && defined(CONFIG_MTD_SPI_NOR_USE_4K_SECTORS)
68 #define RB_SC_HAS_WRITE_SUPPORT true
69 #define RB_SC_WMODE S_IWUSR
70 #define RB_SC_RMODE S_IRUSR
72 #define RB_SC_HAS_WRITE_SUPPORT false
74 #define RB_SC_RMODE S_IRUSR
77 /* ID values for software settings */
78 #define RB_SCID_UART_SPEED 0x01 // u32*1
79 #define RB_SCID_BOOT_DELAY 0x02 // u32*1
80 #define RB_SCID_BOOT_DEVICE 0x03 // u32*1
81 #define RB_SCID_BOOT_KEY 0x04 // u32*1
82 #define RB_SCID_CPU_MODE 0x05 // u32*1
83 #define RB_SCID_BIOS_VERSION 0x06 // str
84 #define RB_SCID_BOOT_PROTOCOL 0x09 // u32*1
85 #define RB_SCID_CPU_FREQ_IDX 0x0C // u32*1
86 #define RB_SCID_BOOTER 0x0D // u32*1
87 #define RB_SCID_SILENT_BOOT 0x0F // u32*1
89 * protected_routerboot seems to use tag 0x1F. It only works in combination with
90 * RouterOS, resulting in a wiped board otherwise, so it's not implemented here.
91 * The tag values are as follows:
93 * - on: the lower halfword encodes the max value in s for the reset feature,
94 * the higher halfword encodes the min value in s for the reset feature.
95 * Default value when on: 0x00140258: 0x14 = 20s / 0x258= 600s
96 * See details here: https://wiki.mikrotik.com/wiki/Manual:RouterBOARD_settings#Protected_bootloader
101 #define RB_UART_SPEED_115200 0
102 #define RB_UART_SPEED_57600 1
103 #define RB_UART_SPEED_38400 2
104 #define RB_UART_SPEED_19200 3
105 #define RB_UART_SPEED_9600 4
106 #define RB_UART_SPEED_4800 5
107 #define RB_UART_SPEED_2400 6
108 #define RB_UART_SPEED_1200 7
109 #define RB_UART_SPEED_OFF 8
111 /* valid boot delay: 1 - 9s in 1s increment */
112 #define RB_BOOT_DELAY_MIN 1
113 #define RB_BOOT_DELAY_MAX 9
115 #define RB_BOOT_DEVICE_ETHER 0 // "boot over Ethernet"
116 #define RB_BOOT_DEVICE_NANDETH 1 // "boot from NAND, if fail then Ethernet"
117 #define RB_BOOT_DEVICE_CFCARD 2 // (not available in rbcfg)
118 #define RB_BOOT_DEVICE_ETHONCE 3 // "boot Ethernet once, then NAND"
119 #define RB_BOOT_DEVICE_NANDONLY 5 // "boot from NAND only"
120 #define RB_BOOT_DEVICE_FLASHCFG 7 // "boot in flash configuration mode"
121 #define RB_BOOT_DEVICE_FLSHONCE 8 // "boot in flash configuration mode once, then NAND"
124 * ATH79 CPU frequency indices.
125 * It is unknown if they apply to all ATH79 RBs, and some do not seem to feature
126 * the up levels (QCA955x), while U3 is presumably AR9344-only.
128 #define RB_CPU_FREQ_IDX_ATH79_D2 (0 << 3)
129 #define RB_CPU_FREQ_IDX_ATH79_D1 (1 << 3) // 0x8
130 #define RB_CPU_FREQ_IDX_ATH79_N0 (2 << 3) // 0x10 - factory freq for many devices
131 #define RB_CPU_FREQ_IDX_ATH79_U1 (3 << 3) // 0x18
132 #define RB_CPU_FREQ_IDX_ATH79_U2 (4 << 3) // 0x20
133 #define RB_CPU_FREQ_IDX_ATH79_U3 (5 << 3) // 0x28
135 #define RB_CPU_FREQ_IDX_ATH79_MIN 0 // all devices support lowest setting
136 #define RB_CPU_FREQ_IDX_ATH79_AR9334_MAX 5 // stops at U3
137 #define RB_CPU_FREQ_IDX_ATH79_QCA953X_MAX 4 // stops at U2
138 #define RB_CPU_FREQ_IDX_ATH79_QCA9556_MAX 2 // stops at N0
139 #define RB_CPU_FREQ_IDX_ATH79_QCA9558_MAX 3 // stops at U1
141 #define RB_SC_CRC32_OFFSET 4 // located right after magic
143 static struct kobject *sc_kobj;
145 static size_t sc_buflen;
146 static rwlock_t sc_bufrwl; // rw lock to sc_buf
148 /* MUST be used with lock held */
149 #define RB_SC_CLRCRC() *(u32 *)(sc_buf + RB_SC_CRC32_OFFSET) = 0
150 #define RB_SC_GETCRC() *(u32 *)(sc_buf + RB_SC_CRC32_OFFSET)
151 #define RB_SC_SETCRC(_crc) *(u32 *)(sc_buf + RB_SC_CRC32_OFFSET) = (_crc)
158 #define RB_SC_TVS(_val, _str) { \
163 static ssize_t sc_tag_show_u32tvs(const u8 *pld, u16 pld_len, char *buf,
164 const struct sc_u32tvs tvs[], const int tvselmts)
168 u32 data; // cpu-endian
174 if (sizeof(data) != pld_len)
177 read_lock(&sc_bufrwl);
178 data = *(u32 *)pld; // pld aliases sc_buf
179 read_unlock(&sc_bufrwl);
181 for (i = 0; i < tvselmts; i++) {
182 fmt = (tvs[i].val == data) ? "[%s] " : "%s ";
183 out += sprintf(out, fmt, tvs[i].str);
186 out += sprintf(out, "\n");
190 static ssize_t sc_tag_store_u32tvs(const u8 *pld, u16 pld_len, const char *buf, size_t count,
191 const struct sc_u32tvs tvs[], const int tvselmts)
198 if (sizeof(u32) != pld_len)
201 for (i = 0; i < tvselmts; i++) {
202 if (sysfs_streq(buf, tvs[i].str)) {
203 write_lock(&sc_bufrwl);
204 *(u32 *)pld = tvs[i].val; // pld aliases sc_buf
206 write_unlock(&sc_bufrwl);
215 const char *strfalse;
219 static ssize_t sc_tag_show_boolts(const u8 *pld, u16 pld_len, char *buf,
220 const struct sc_boolts *bts)
224 u32 data; // cpu-endian
226 if (sizeof(data) != pld_len)
229 read_lock(&sc_bufrwl);
230 data = *(u32 *)pld; // pld aliases sc_buf
231 read_unlock(&sc_bufrwl);
233 fmt = (data) ? "%s [%s]\n" : "[%s] %s\n";
234 out += sprintf(out, fmt, bts->strfalse, bts->strtrue);
239 static ssize_t sc_tag_store_boolts(const u8 *pld, u16 pld_len, const char *buf, size_t count,
240 const struct sc_boolts *bts)
242 u32 data; // cpu-endian
244 if (sizeof(data) != pld_len)
247 if (sysfs_streq(buf, bts->strfalse))
249 else if (sysfs_streq(buf, bts->strtrue))
254 write_lock(&sc_bufrwl);
255 *(u32 *)pld = data; // pld aliases sc_buf
257 write_unlock(&sc_bufrwl);
261 static struct sc_u32tvs const sc_uartspeeds[] = {
262 RB_SC_TVS(RB_UART_SPEED_OFF, "off"),
263 RB_SC_TVS(RB_UART_SPEED_1200, "1200"),
264 RB_SC_TVS(RB_UART_SPEED_2400, "2400"),
265 RB_SC_TVS(RB_UART_SPEED_4800, "4800"),
266 RB_SC_TVS(RB_UART_SPEED_9600, "9600"),
267 RB_SC_TVS(RB_UART_SPEED_19200, "19200"),
268 RB_SC_TVS(RB_UART_SPEED_38400, "38400"),
269 RB_SC_TVS(RB_UART_SPEED_57600, "57600"),
270 RB_SC_TVS(RB_UART_SPEED_115200, "115200"),
274 * While the defines are carried over from rbcfg, use strings that more clearly
275 * show the actual setting purpose (especially since the NAND* settings apply
276 * to both nand- and nor-based devices). "cfcard" was disabled in rbcfg: disable
279 static struct sc_u32tvs const sc_bootdevices[] = {
280 RB_SC_TVS(RB_BOOT_DEVICE_ETHER, "eth"),
281 RB_SC_TVS(RB_BOOT_DEVICE_NANDETH, "flasheth"),
282 //RB_SC_TVS(RB_BOOT_DEVICE_CFCARD, "cfcard"),
283 RB_SC_TVS(RB_BOOT_DEVICE_ETHONCE, "ethonce"),
284 RB_SC_TVS(RB_BOOT_DEVICE_NANDONLY, "flash"),
285 RB_SC_TVS(RB_BOOT_DEVICE_FLASHCFG, "cfg"),
286 RB_SC_TVS(RB_BOOT_DEVICE_FLSHONCE, "cfgonce"),
289 static struct sc_boolts const sc_bootkey = {
294 static struct sc_boolts const sc_cpumode = {
295 .strfalse = "powersave",
296 .strtrue = "regular",
299 static struct sc_boolts const sc_bootproto = {
304 static struct sc_boolts const sc_booter = {
305 .strfalse = "regular",
309 static struct sc_boolts const sc_silent_boot = {
314 #define SC_TAG_SHOW_STORE_U32TVS_FUNCS(_name) \
315 static ssize_t sc_tag_show_##_name(const u8 *pld, u16 pld_len, char *buf) \
317 return sc_tag_show_u32tvs(pld, pld_len, buf, sc_##_name, ARRAY_SIZE(sc_##_name)); \
319 static ssize_t sc_tag_store_##_name(const u8 *pld, u16 pld_len, const char *buf, size_t count) \
321 return sc_tag_store_u32tvs(pld, pld_len, buf, count, sc_##_name, ARRAY_SIZE(sc_##_name)); \
324 #define SC_TAG_SHOW_STORE_BOOLTS_FUNCS(_name) \
325 static ssize_t sc_tag_show_##_name(const u8 *pld, u16 pld_len, char *buf) \
327 return sc_tag_show_boolts(pld, pld_len, buf, &sc_##_name); \
329 static ssize_t sc_tag_store_##_name(const u8 *pld, u16 pld_len, const char *buf, size_t count) \
331 return sc_tag_store_boolts(pld, pld_len, buf, count, &sc_##_name); \
334 SC_TAG_SHOW_STORE_U32TVS_FUNCS(uartspeeds)
335 SC_TAG_SHOW_STORE_U32TVS_FUNCS(bootdevices)
336 SC_TAG_SHOW_STORE_BOOLTS_FUNCS(bootkey)
337 SC_TAG_SHOW_STORE_BOOLTS_FUNCS(cpumode)
338 SC_TAG_SHOW_STORE_BOOLTS_FUNCS(bootproto)
339 SC_TAG_SHOW_STORE_BOOLTS_FUNCS(booter)
340 SC_TAG_SHOW_STORE_BOOLTS_FUNCS(silent_boot)
342 static ssize_t sc_tag_show_bootdelays(const u8 *pld, u16 pld_len, char *buf)
346 u32 data; // cpu-endian
349 if (sizeof(data) != pld_len)
352 read_lock(&sc_bufrwl);
353 data = *(u32 *)pld; // pld aliases sc_buf
354 read_unlock(&sc_bufrwl);
356 for (i = RB_BOOT_DELAY_MIN; i <= RB_BOOT_DELAY_MAX; i++) {
357 fmt = (i == data) ? "[%d] " : "%d ";
358 out += sprintf(out, fmt, i);
361 out += sprintf(out, "\n");
365 static ssize_t sc_tag_store_bootdelays(const u8 *pld, u16 pld_len, const char *buf, size_t count)
367 u32 data; // cpu-endian
370 if (sizeof(data) != pld_len)
373 ret = kstrtou32(buf, 10, &data);
377 if ((data < RB_BOOT_DELAY_MIN) || (RB_BOOT_DELAY_MAX < data))
380 write_lock(&sc_bufrwl);
381 *(u32 *)pld = data; // pld aliases sc_buf
383 write_unlock(&sc_bufrwl);
388 /* Support CPU frequency accessors only when the tag format has been asserted */
389 #if defined(CONFIG_ATH79)
390 static struct sc_u32tvs const sc_cpufreq_indexes_ath79[] = {
391 RB_SC_TVS(RB_CPU_FREQ_IDX_ATH79_D2, "-2"),
392 RB_SC_TVS(RB_CPU_FREQ_IDX_ATH79_D1, "-1"),
393 RB_SC_TVS(RB_CPU_FREQ_IDX_ATH79_N0, "0"),
394 RB_SC_TVS(RB_CPU_FREQ_IDX_ATH79_U1, "+1"),
395 RB_SC_TVS(RB_CPU_FREQ_IDX_ATH79_U2, "+2"),
396 RB_SC_TVS(RB_CPU_FREQ_IDX_ATH79_U3, "+3"),
399 static int sc_tag_cpufreq_ath79_idxmax(void)
401 int idx_max = -EOPNOTSUPP;
404 idx_max = RB_CPU_FREQ_IDX_ATH79_AR9334_MAX;
405 else if (soc_is_qca953x())
406 idx_max = RB_CPU_FREQ_IDX_ATH79_QCA953X_MAX;
407 else if (soc_is_qca9556())
408 idx_max = RB_CPU_FREQ_IDX_ATH79_QCA9556_MAX;
409 else if (soc_is_qca9558())
410 idx_max = RB_CPU_FREQ_IDX_ATH79_QCA9558_MAX;
415 static ssize_t sc_tag_show_cpufreq_indexes(const u8 *pld, u16 pld_len, char * buf)
417 return sc_tag_show_u32tvs(pld, pld_len, buf, sc_cpufreq_indexes_ath79, sc_tag_cpufreq_ath79_idxmax()+1);
420 static ssize_t sc_tag_store_cpufreq_indexes(const u8 *pld, u16 pld_len, const char *buf, size_t count)
422 return sc_tag_store_u32tvs(pld, pld_len, buf, count, sc_cpufreq_indexes_ath79, sc_tag_cpufreq_ath79_idxmax()+1);
425 /* By default we only show the raw value to help with reverse-engineering */
426 #define sc_tag_show_cpufreq_indexes routerboot_tag_show_u32s
427 #define sc_tag_store_cpufreq_indexes NULL
430 static ssize_t sc_attr_show(struct kobject *kobj, struct kobj_attribute *attr,
432 static ssize_t sc_attr_store(struct kobject *kobj, struct kobj_attribute *attr,
433 const char *buf, size_t count);
435 /* Array of known tags to publish in sysfs */
436 static struct sc_attr {
438 /* sysfs tag show attribute. Must lock sc_buf when dereferencing pld */
439 ssize_t (* const tshow)(const u8 *pld, u16 pld_len, char *buf);
440 /* sysfs tag store attribute. Must lock sc_buf when dereferencing pld */
441 ssize_t (* const tstore)(const u8 *pld, u16 pld_len, const char *buf, size_t count);
442 struct kobj_attribute kattr;
447 .tag_id = RB_SCID_UART_SPEED,
448 .tshow = sc_tag_show_uartspeeds,
449 .tstore = sc_tag_store_uartspeeds,
450 .kattr = __ATTR(uart_speed, RB_SC_RMODE|RB_SC_WMODE, sc_attr_show, sc_attr_store),
452 .tag_id = RB_SCID_BOOT_DELAY,
453 .tshow = sc_tag_show_bootdelays,
454 .tstore = sc_tag_store_bootdelays,
455 .kattr = __ATTR(boot_delay, RB_SC_RMODE|RB_SC_WMODE, sc_attr_show, sc_attr_store),
457 .tag_id = RB_SCID_BOOT_DEVICE,
458 .tshow = sc_tag_show_bootdevices,
459 .tstore = sc_tag_store_bootdevices,
460 .kattr = __ATTR(boot_device, RB_SC_RMODE|RB_SC_WMODE, sc_attr_show, sc_attr_store),
462 .tag_id = RB_SCID_BOOT_KEY,
463 .tshow = sc_tag_show_bootkey,
464 .tstore = sc_tag_store_bootkey,
465 .kattr = __ATTR(boot_key, RB_SC_RMODE|RB_SC_WMODE, sc_attr_show, sc_attr_store),
467 .tag_id = RB_SCID_CPU_MODE,
468 .tshow = sc_tag_show_cpumode,
469 .tstore = sc_tag_store_cpumode,
470 .kattr = __ATTR(cpu_mode, RB_SC_RMODE|RB_SC_WMODE, sc_attr_show, sc_attr_store),
472 .tag_id = RB_SCID_BIOS_VERSION,
473 .tshow = routerboot_tag_show_string,
475 .kattr = __ATTR(bios_version, RB_SC_RMODE, sc_attr_show, NULL),
477 .tag_id = RB_SCID_BOOT_PROTOCOL,
478 .tshow = sc_tag_show_bootproto,
479 .tstore = sc_tag_store_bootproto,
480 .kattr = __ATTR(boot_proto, RB_SC_RMODE|RB_SC_WMODE, sc_attr_show, sc_attr_store),
482 .tag_id = RB_SCID_CPU_FREQ_IDX,
483 .tshow = sc_tag_show_cpufreq_indexes,
484 .tstore = sc_tag_store_cpufreq_indexes,
485 .kattr = __ATTR(cpufreq_index, RB_SC_RMODE|RB_SC_WMODE, sc_attr_show, sc_attr_store),
487 .tag_id = RB_SCID_BOOTER,
488 .tshow = sc_tag_show_booter,
489 .tstore = sc_tag_store_booter,
490 .kattr = __ATTR(booter, RB_SC_RMODE|RB_SC_WMODE, sc_attr_show, sc_attr_store),
492 .tag_id = RB_SCID_SILENT_BOOT,
493 .tshow = sc_tag_show_silent_boot,
494 .tstore = sc_tag_store_silent_boot,
495 .kattr = __ATTR(silent_boot, RB_SC_RMODE|RB_SC_WMODE, sc_attr_show, sc_attr_store),
499 static ssize_t sc_attr_show(struct kobject *kobj, struct kobj_attribute *attr,
502 const struct sc_attr *sc_attr;
506 sc_attr = container_of(attr, typeof(*sc_attr), kattr);
508 if (!sc_attr->pld_len)
511 pld = sc_buf + sc_attr->pld_ofs; // pld aliases sc_buf -> lock!
512 pld_len = sc_attr->pld_len;
514 return sc_attr->tshow(pld, pld_len, buf);
517 static ssize_t sc_attr_store(struct kobject *kobj, struct kobj_attribute *attr,
518 const char *buf, size_t count)
520 const struct sc_attr *sc_attr;
524 if (!RB_SC_HAS_WRITE_SUPPORT)
527 if (!capable(CAP_SYS_ADMIN))
530 sc_attr = container_of(attr, typeof(*sc_attr), kattr);
532 if (!sc_attr->tstore)
535 if (!sc_attr->pld_len)
538 pld = sc_buf + sc_attr->pld_ofs; // pld aliases sc_buf -> lock!
539 pld_len = sc_attr->pld_len;
541 return sc_attr->tstore(pld, pld_len, buf, count);
545 * Shows the current buffer status:
546 * "clean": the buffer is in sync with the mtd data
547 * "dirty": the buffer is out of sync with the mtd data
549 static ssize_t sc_commit_show(struct kobject *kobj, struct kobj_attribute *attr,
556 read_lock(&sc_bufrwl);
557 crc = RB_SC_GETCRC();
558 read_unlock(&sc_bufrwl);
560 str = (crc) ? "clean" : "dirty";
561 out += sprintf(out, "%s\n", str);
567 * Performs buffer flushing:
568 * This routine expects an input compatible with kstrtobool().
569 * - a "false" input discards the current changes and reads data back from mtd.
570 * - a "true" input commits the current changes to mtd.
571 * If there is no pending changes, this routine is a no-op.
572 * Handling failures is left as an exercise to userspace.
574 static ssize_t sc_commit_store(struct kobject *kobj, struct kobj_attribute *attr,
575 const char *buf, size_t count)
577 struct mtd_info *mtd;
578 struct erase_info ei;
579 size_t bytes_rw, ret = count;
583 if (!RB_SC_HAS_WRITE_SUPPORT)
586 read_lock(&sc_bufrwl);
587 crc = RB_SC_GETCRC();
588 read_unlock(&sc_bufrwl);
591 return count; // NO-OP
593 ret = kstrtobool(buf, &flush);
597 mtd = get_mtd_device_nm(RB_MTD_SOFT_CONFIG); // TODO allow override
601 write_lock(&sc_bufrwl);
602 if (!flush) // reread
603 ret = mtd_read(mtd, 0, mtd->size, &bytes_rw, sc_buf);
604 else { // crc32 + commit
606 * CRC32 is computed on the entire buffer, excluding the CRC
607 * value itself. CRC is already null when we reach this point,
608 * so we can compute the CRC32 on the buffer as is.
609 * The expected CRC32 is Ethernet FCS style, meaning the seed is
610 * ~0 and the final result is also bitflipped.
613 crc = ~crc32(~0, sc_buf, sc_buflen);
617 * The soft_config partition is assumed to be entirely contained
618 * in a single eraseblock.
623 ret = mtd_erase(mtd, &ei);
625 ret = mtd_write(mtd, 0, mtd->size, &bytes_rw, sc_buf);
628 * Handling mtd_write() failure here is a tricky situation. The
629 * proposed approach is to let userspace deal with retrying,
630 * with the caveat that it must try to flush the buffer again as
631 * rereading the mtd contents could potentially read garbage.
632 * The rationale is: even if we keep a shadow buffer of the
633 * original content, there is no guarantee that we will ever be
634 * able to write it anyway.
635 * Regardless, it appears that RouterBOOT will ignore an invalid
636 * soft_config (including a completely wiped segment) and will
637 * write back factory defaults when it happens.
640 write_unlock(&sc_bufrwl);
645 if (bytes_rw != sc_buflen) {
653 RB_SC_CLRCRC(); // mark buffer content as dirty/invalid
657 static struct kobj_attribute sc_kattrcommit = __ATTR(commit, RB_SC_RMODE|RB_SC_WMODE, sc_commit_show, sc_commit_store);
659 int __init rb_softconfig_init(struct kobject *rb_kobj)
661 struct mtd_info *mtd;
662 size_t bytes_read, buflen;
670 // TODO allow override
671 mtd = get_mtd_device_nm(RB_MTD_SOFT_CONFIG);
675 sc_buflen = mtd->size;
676 sc_buf = kmalloc(sc_buflen, GFP_KERNEL);
680 ret = mtd_read(mtd, 0, sc_buflen, &bytes_read, sc_buf);
685 if (bytes_read != sc_buflen) {
690 /* Check we have what we expect */
691 magic = *(const u32 *)sc_buf;
692 if (RB_MAGIC_SOFT != magic) {
697 /* Skip magic and 32bit CRC located immediately after */
698 buf = sc_buf + (sizeof(magic) + sizeof(u32));
699 buflen = sc_buflen - (sizeof(magic) + sizeof(u32));
703 sc_kobj = kobject_create_and_add(RB_MTD_SOFT_CONFIG, rb_kobj);
707 rwlock_init(&sc_bufrwl);
709 /* Locate and publish all known tags */
710 for (i = 0; i < ARRAY_SIZE(sc_attrs); i++) {
711 ret = routerboot_tag_find(buf, buflen, sc_attrs[i].tag_id,
712 &sc_attrs[i].pld_ofs, &sc_attrs[i].pld_len);
714 sc_attrs[i].pld_ofs = sc_attrs[i].pld_len = 0;
718 /* Account for skipped magic and crc32 */
719 sc_attrs[i].pld_ofs += sizeof(magic) + sizeof(u32);
721 ret = sysfs_create_file(sc_kobj, &sc_attrs[i].kattr.attr);
723 pr_warn(RB_SC_PR_PFX "Could not create %s sysfs entry (%d)\n",
724 sc_attrs[i].kattr.attr.name, ret);
727 /* Finally add the 'commit' attribute */
728 if (RB_SC_HAS_WRITE_SUPPORT) {
729 ret = sysfs_create_file(sc_kobj, &sc_kattrcommit.attr);
731 pr_err(RB_SC_PR_PFX "Could not create %s sysfs entry (%d), aborting!\n",
732 sc_kattrcommit.attr.name, ret);
733 goto sysfsfail; // required attribute
737 pr_info("MikroTik RouterBOARD software configuration sysfs driver v" RB_SOFTCONFIG_VER "\n");
742 kobject_put(sc_kobj);
750 void __exit rb_softconfig_exit(void)
752 kobject_put(sc_kobj);