target/linux/generic/files/drivers/net/phy/rtl8367b.c

   1 /*
   2  * Platform driver for the Realtek RTL8367R-VB ethernet switches
   3  *
   4  * Copyright (C) 2012 Gabor Juhos <juhosg@openwrt.org>
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License version 2 as published
   8  * by the Free Software Foundation.
   9  */
  10
  11 #include <linux/kernel.h>
  12 #include <linux/module.h>
  13 #include <linux/init.h>
  14 #include <linux/device.h>
  15 #include <linux/of.h>
  16 #include <linux/of_platform.h>
  17 #include <linux/delay.h>
  18 #include <linux/skbuff.h>
  19 #include <linux/rtl8367.h>
  20
  21 #include "rtl8366_smi.h"
  22
  23 #define RTL8367B_RESET_DELAY    1000    /* msecs*/
  24
  25 #define RTL8367B_PHY_ADDR_MAX   8
  26 #define RTL8367B_PHY_REG_MAX    31
  27
  28 #define RTL8367B_VID_MASK       0x3fff
  29 #define RTL8367B_FID_MASK       0xf
  30 #define RTL8367B_UNTAG_MASK     0xff
  31 #define RTL8367B_MEMBER_MASK    0xff
  32
  33 #define RTL8367B_PORT_MISC_CFG_REG(_p)          (0x000e + 0x20 * (_p))
  34 #define   RTL8367B_PORT_MISC_CFG_EGRESS_MODE_SHIFT      4
  35 #define   RTL8367B_PORT_MISC_CFG_EGRESS_MODE_MASK       0x3
  36 #define   RTL8367B_PORT_MISC_CFG_EGRESS_MODE_ORIGINAL   0
  37 #define   RTL8367B_PORT_MISC_CFG_EGRESS_MODE_KEEP       1
  38 #define   RTL8367B_PORT_MISC_CFG_EGRESS_MODE_PRI        2
  39 #define   RTL8367B_PORT_MISC_CFG_EGRESS_MODE_REAL       3
  40
  41 #define RTL8367B_BYPASS_LINE_RATE_REG           0x03f7
  42
  43 #define RTL8367B_TA_CTRL_REG                    0x0500 /*GOOD*/
  44 #define   RTL8367B_TA_CTRL_SPA_SHIFT            8
  45 #define   RTL8367B_TA_CTRL_SPA_MASK             0x7
  46 #define   RTL8367B_TA_CTRL_METHOD               BIT(4)/*GOOD*/
  47 #define   RTL8367B_TA_CTRL_CMD_SHIFT            3
  48 #define   RTL8367B_TA_CTRL_CMD_READ             0
  49 #define   RTL8367B_TA_CTRL_CMD_WRITE            1
  50 #define   RTL8367B_TA_CTRL_TABLE_SHIFT          0 /*GOOD*/
  51 #define   RTL8367B_TA_CTRL_TABLE_ACLRULE        1
  52 #define   RTL8367B_TA_CTRL_TABLE_ACLACT         2
  53 #define   RTL8367B_TA_CTRL_TABLE_CVLAN          3
  54 #define   RTL8367B_TA_CTRL_TABLE_L2             4
  55 #define   RTL8367B_TA_CTRL_CVLAN_READ \
  56                 ((RTL8367B_TA_CTRL_CMD_READ << RTL8367B_TA_CTRL_CMD_SHIFT) | \
  57                  RTL8367B_TA_CTRL_TABLE_CVLAN)
  58 #define   RTL8367B_TA_CTRL_CVLAN_WRITE \
  59                 ((RTL8367B_TA_CTRL_CMD_WRITE << RTL8367B_TA_CTRL_CMD_SHIFT) | \
  60                  RTL8367B_TA_CTRL_TABLE_CVLAN)
  61
  62 #define RTL8367B_TA_ADDR_REG                    0x0501/*GOOD*/
  63 #define   RTL8367B_TA_ADDR_MASK                 0x3fff/*GOOD*/
  64
  65 #define RTL8367B_TA_LUT_REG                     0x0502/*GOOD*/
  66
  67 #define RTL8367B_TA_WRDATA_REG(_x)              (0x0510 + (_x))/*GOOD*/
  68 #define   RTL8367B_TA_VLAN_NUM_WORDS            2
  69 #define   RTL8367B_TA_VLAN_VID_MASK             RTL8367B_VID_MASK
  70 #define   RTL8367B_TA_VLAN0_MEMBER_SHIFT        0
  71 #define   RTL8367B_TA_VLAN0_MEMBER_MASK         RTL8367B_MEMBER_MASK
  72 #define   RTL8367B_TA_VLAN0_UNTAG_SHIFT         8
  73 #define   RTL8367B_TA_VLAN0_UNTAG_MASK          RTL8367B_MEMBER_MASK
  74 #define   RTL8367B_TA_VLAN1_FID_SHIFT           0
  75 #define   RTL8367B_TA_VLAN1_FID_MASK            RTL8367B_FID_MASK
  76
  77 #define RTL8367B_TA_RDDATA_REG(_x)              (0x0520 + (_x))/*GOOD*/
  78
  79 #define RTL8367B_VLAN_PVID_CTRL_REG(_p)         (0x0700 + (_p) / 2) /*GOOD*/
  80 #define RTL8367B_VLAN_PVID_CTRL_MASK            0x1f /*GOOD*/
  81 #define RTL8367B_VLAN_PVID_CTRL_SHIFT(_p)       (8 * ((_p) % 2)) /*GOOD*/
  82
  83 #define RTL8367B_VLAN_MC_BASE(_x)               (0x0728 + (_x) * 4) /*GOOD*/
  84 #define   RTL8367B_VLAN_MC_NUM_WORDS            4 /*GOOD*/
  85 #define   RTL8367B_VLAN_MC0_MEMBER_SHIFT        0/*GOOD*/
  86 #define   RTL8367B_VLAN_MC0_MEMBER_MASK         RTL8367B_MEMBER_MASK/*GOOD*/
  87 #define   RTL8367B_VLAN_MC1_FID_SHIFT           0/*GOOD*/
  88 #define   RTL8367B_VLAN_MC1_FID_MASK            RTL8367B_FID_MASK/*GOOD*/
  89 #define   RTL8367B_VLAN_MC3_EVID_SHIFT          0/*GOOD*/
  90 #define   RTL8367B_VLAN_MC3_EVID_MASK           RTL8367B_VID_MASK/*GOOD*/
  91
  92 #define RTL8367B_VLAN_CTRL_REG                  0x07a8 /*GOOD*/
  93 #define   RTL8367B_VLAN_CTRL_ENABLE             BIT(0)
  94
  95 #define RTL8367B_VLAN_INGRESS_REG               0x07a9 /*GOOD*/
  96
  97 #define RTL8367B_PORT_ISOLATION_REG(_p)         (0x08a2 + (_p)) /*GOOD*/
  98
  99 #define RTL8367B_MIB_COUNTER_REG(_x)            (0x1000 + (_x)) /*GOOD*/
 100 #define RTL8367B_MIB_COUNTER_PORT_OFFSET        0x007c /*GOOD*/
 101
 102 #define RTL8367B_MIB_ADDRESS_REG                0x1004 /*GOOD*/
 103
 104 #define RTL8367B_MIB_CTRL0_REG(_x)              (0x1005 + (_x)) /*GOOD*/
 105 #define   RTL8367B_MIB_CTRL0_GLOBAL_RESET_MASK  BIT(11) /*GOOD*/
 106 #define   RTL8367B_MIB_CTRL0_QM_RESET_MASK      BIT(10) /*GOOD*/
 107 #define   RTL8367B_MIB_CTRL0_PORT_RESET_MASK(_p) BIT(2 + (_p)) /*GOOD*/
 108 #define   RTL8367B_MIB_CTRL0_RESET_MASK         BIT(1) /*GOOD*/
 109 #define   RTL8367B_MIB_CTRL0_BUSY_MASK          BIT(0) /*GOOD*/
 110
 111 #define RTL8367B_SWC0_REG                       0x1200/*GOOD*/
 112 #define   RTL8367B_SWC0_MAX_LENGTH_SHIFT        13/*GOOD*/
 113 #define   RTL8367B_SWC0_MAX_LENGTH(_x)          ((_x) << 13) /*GOOD*/
 114 #define   RTL8367B_SWC0_MAX_LENGTH_MASK         RTL8367B_SWC0_MAX_LENGTH(0x3)
 115 #define   RTL8367B_SWC0_MAX_LENGTH_1522         RTL8367B_SWC0_MAX_LENGTH(0)
 116 #define   RTL8367B_SWC0_MAX_LENGTH_1536         RTL8367B_SWC0_MAX_LENGTH(1)
 117 #define   RTL8367B_SWC0_MAX_LENGTH_1552         RTL8367B_SWC0_MAX_LENGTH(2)
 118 #define   RTL8367B_SWC0_MAX_LENGTH_16000        RTL8367B_SWC0_MAX_LENGTH(3)
 119
 120 #define RTL8367B_CHIP_NUMBER_REG                0x1300/*GOOD*/
 121
 122 #define RTL8367B_CHIP_VER_REG                   0x1301/*GOOD*/
 123 #define   RTL8367B_CHIP_VER_RLVID_SHIFT         12/*GOOD*/
 124 #define   RTL8367B_CHIP_VER_RLVID_MASK          0xf/*GOOD*/
 125 #define   RTL8367B_CHIP_VER_MCID_SHIFT          8/*GOOD*/
 126 #define   RTL8367B_CHIP_VER_MCID_MASK           0xf/*GOOD*/
 127 #define   RTL8367B_CHIP_VER_BOID_SHIFT          4/*GOOD*/
 128 #define   RTL8367B_CHIP_VER_BOID_MASK           0xf/*GOOD*/
 129 #define   RTL8367B_CHIP_VER_AFE_SHIFT           0/*GOOD*/
 130 #define   RTL8367B_CHIP_VER_AFE_MASK            0x1/*GOOD*/
 131
 132 #define RTL8367B_CHIP_MODE_REG                  0x1302
 133 #define   RTL8367B_CHIP_MODE_MASK               0x7
 134
 135 #define RTL8367B_CHIP_DEBUG0_REG                0x1303
 136 #define   RTL8367B_CHIP_DEBUG0_DUMMY0(_x)       BIT(8 + (_x))
 137
 138 #define RTL8367B_CHIP_DEBUG1_REG                0x1304
 139
 140 #define RTL8367B_DIS_REG                        0x1305
 141 #define   RTL8367B_DIS_SKIP_MII_RXER(_x)        BIT(12 + (_x))
 142 #define   RTL8367B_DIS_RGMII_SHIFT(_x)          (4 * (_x))
 143 #define   RTL8367B_DIS_RGMII_MASK               0x7
 144
 145 #define RTL8367B_EXT_RGMXF_REG(_x)              (0x1306 + (_x))
 146 #define   RTL8367B_EXT_RGMXF_DUMMY0_SHIFT       5
 147 #define   RTL8367B_EXT_RGMXF_DUMMY0_MASK        0x7ff
 148 #define   RTL8367B_EXT_RGMXF_TXDELAY_SHIFT      3
 149 #define   RTL8367B_EXT_RGMXF_TXDELAY_MASK       1
 150 #define   RTL8367B_EXT_RGMXF_RXDELAY_MASK       0x7
 151
 152 #define RTL8367B_DI_FORCE_REG(_x)               (0x1310 + (_x))
 153 #define   RTL8367B_DI_FORCE_MODE                BIT(12)
 154 #define   RTL8367B_DI_FORCE_NWAY                BIT(7)
 155 #define   RTL8367B_DI_FORCE_TXPAUSE             BIT(6)
 156 #define   RTL8367B_DI_FORCE_RXPAUSE             BIT(5)
 157 #define   RTL8367B_DI_FORCE_LINK                BIT(4)
 158 #define   RTL8367B_DI_FORCE_DUPLEX              BIT(2)
 159 #define   RTL8367B_DI_FORCE_SPEED_MASK          3
 160 #define   RTL8367B_DI_FORCE_SPEED_10            0
 161 #define   RTL8367B_DI_FORCE_SPEED_100           1
 162 #define   RTL8367B_DI_FORCE_SPEED_1000          2
 163
 164 #define RTL8367B_MAC_FORCE_REG(_x)              (0x1312 + (_x))
 165
 166 #define RTL8367B_CHIP_RESET_REG                 0x1322 /*GOOD*/
 167 #define   RTL8367B_CHIP_RESET_SW                BIT(1) /*GOOD*/
 168 #define   RTL8367B_CHIP_RESET_HW                BIT(0) /*GOOD*/
 169
 170 #define RTL8367B_PORT_STATUS_REG(_p)            (0x1352 + (_p)) /*GOOD*/
 171 #define   RTL8367B_PORT_STATUS_EN_1000_SPI      BIT(11) /*GOOD*/
 172 #define   RTL8367B_PORT_STATUS_EN_100_SPI       BIT(10)/*GOOD*/
 173 #define   RTL8367B_PORT_STATUS_NWAY_FAULT       BIT(9)/*GOOD*/
 174 #define   RTL8367B_PORT_STATUS_LINK_MASTER      BIT(8)/*GOOD*/
 175 #define   RTL8367B_PORT_STATUS_NWAY             BIT(7)/*GOOD*/
 176 #define   RTL8367B_PORT_STATUS_TXPAUSE          BIT(6)/*GOOD*/
 177 #define   RTL8367B_PORT_STATUS_RXPAUSE          BIT(5)/*GOOD*/
 178 #define   RTL8367B_PORT_STATUS_LINK             BIT(4)/*GOOD*/
 179 #define   RTL8367B_PORT_STATUS_DUPLEX           BIT(2)/*GOOD*/
 180 #define   RTL8367B_PORT_STATUS_SPEED_MASK       0x0003/*GOOD*/
 181 #define   RTL8367B_PORT_STATUS_SPEED_10         0/*GOOD*/
 182 #define   RTL8367B_PORT_STATUS_SPEED_100        1/*GOOD*/
 183 #define   RTL8367B_PORT_STATUS_SPEED_1000       2/*GOOD*/
 184
 185 #define RTL8367B_RTL_MAGIC_ID_REG               0x13c2
 186 #define   RTL8367B_RTL_MAGIC_ID_VAL             0x0249
 187
 188 #define RTL8367B_IA_CTRL_REG                    0x1f00
 189 #define   RTL8367B_IA_CTRL_RW(_x)               ((_x) << 1)
 190 #define   RTL8367B_IA_CTRL_RW_READ              RTL8367B_IA_CTRL_RW(0)
 191 #define   RTL8367B_IA_CTRL_RW_WRITE             RTL8367B_IA_CTRL_RW(1)
 192 #define   RTL8367B_IA_CTRL_CMD_MASK             BIT(0)
 193
 194 #define RTL8367B_IA_STATUS_REG                  0x1f01
 195 #define   RTL8367B_IA_STATUS_PHY_BUSY           BIT(2)
 196 #define   RTL8367B_IA_STATUS_SDS_BUSY           BIT(1)
 197 #define   RTL8367B_IA_STATUS_MDX_BUSY           BIT(0)
 198
 199 #define RTL8367B_IA_ADDRESS_REG                 0x1f02
 200 #define RTL8367B_IA_WRITE_DATA_REG              0x1f03
 201 #define RTL8367B_IA_READ_DATA_REG               0x1f04
 202
 203 #define RTL8367B_INTERNAL_PHY_REG(_a, _r)       (0x2000 + 32 * (_a) + (_r))
 204
 205 #define RTL8367B_NUM_MIB_COUNTERS       58
 206
 207 #define RTL8367B_CPU_PORT_NUM           5
 208 #define RTL8367B_NUM_PORTS              8
 209 #define RTL8367B_NUM_VLANS              32
 210 #define RTL8367B_NUM_VIDS               4096
 211 #define RTL8367B_PRIORITYMAX            7
 212 #define RTL8367B_FIDMAX                 7
 213
 214 #define RTL8367B_PORT_0                 BIT(0)
 215 #define RTL8367B_PORT_1                 BIT(1)
 216 #define RTL8367B_PORT_2                 BIT(2)
 217 #define RTL8367B_PORT_3                 BIT(3)
 218 #define RTL8367B_PORT_4                 BIT(4)
 219 #define RTL8367B_PORT_E0                BIT(5)  /* External port 0 */
 220 #define RTL8367B_PORT_E1                BIT(6)  /* External port 1 */
 221 #define RTL8367B_PORT_E2                BIT(7)  /* External port 2 */
 222
 223 #define RTL8367B_PORTS_ALL                                      \
 224         (RTL8367B_PORT_0 | RTL8367B_PORT_1 | RTL8367B_PORT_2 |  \
 225          RTL8367B_PORT_3 | RTL8367B_PORT_4 | RTL8367B_PORT_E0 | \
 226          RTL8367B_PORT_E1 | RTL8367B_PORT_E2)
 227
 228 #define RTL8367B_PORTS_ALL_BUT_CPU                              \
 229         (RTL8367B_PORT_0 | RTL8367B_PORT_1 | RTL8367B_PORT_2 |  \
 230          RTL8367B_PORT_3 | RTL8367B_PORT_4 | RTL8367B_PORT_E1 | \
 231          RTL8367B_PORT_E2)
 232
 233 struct rtl8367b_initval {
 234         u16 reg;
 235         u16 val;
 236 };
 237
 238 #define RTL8367B_MIB_RXB_ID             0       /* IfInOctets */
 239 #define RTL8367B_MIB_TXB_ID             28      /* IfOutOctets */
 240
 241 static struct rtl8366_mib_counter
 242 rtl8367b_mib_counters[RTL8367B_NUM_MIB_COUNTERS] = {
 243         {0,   0, 4, "ifInOctets"                        },
 244         {0,   4, 2, "dot3StatsFCSErrors"                },
 245         {0,   6, 2, "dot3StatsSymbolErrors"             },
 246         {0,   8, 2, "dot3InPauseFrames"                 },
 247         {0,  10, 2, "dot3ControlInUnknownOpcodes"       },
 248         {0,  12, 2, "etherStatsFragments"               },
 249         {0,  14, 2, "etherStatsJabbers"                 },
 250         {0,  16, 2, "ifInUcastPkts"                     },
 251         {0,  18, 2, "etherStatsDropEvents"              },
 252         {0,  20, 2, "ifInMulticastPkts"                 },
 253         {0,  22, 2, "ifInBroadcastPkts"                 },
 254         {0,  24, 2, "inMldChecksumError"                },
 255         {0,  26, 2, "inIgmpChecksumError"               },
 256         {0,  28, 2, "inMldSpecificQuery"                },
 257         {0,  30, 2, "inMldGeneralQuery"                 },
 258         {0,  32, 2, "inIgmpSpecificQuery"               },
 259         {0,  34, 2, "inIgmpGeneralQuery"                },
 260         {0,  36, 2, "inMldLeaves"                       },
 261         {0,  38, 2, "inIgmpLeaves"                      },
 262
 263         {0,  40, 4, "etherStatsOctets"                  },
 264         {0,  44, 2, "etherStatsUnderSizePkts"           },
 265         {0,  46, 2, "etherOversizeStats"                },
 266         {0,  48, 2, "etherStatsPkts64Octets"            },
 267         {0,  50, 2, "etherStatsPkts65to127Octets"       },
 268         {0,  52, 2, "etherStatsPkts128to255Octets"      },
 269         {0,  54, 2, "etherStatsPkts256to511Octets"      },
 270         {0,  56, 2, "etherStatsPkts512to1023Octets"     },
 271         {0,  58, 2, "etherStatsPkts1024to1518Octets"    },
 272
 273         {0,  60, 4, "ifOutOctets"                       },
 274         {0,  64, 2, "dot3StatsSingleCollisionFrames"    },
 275         {0,  66, 2, "dot3StatMultipleCollisionFrames"   },
 276         {0,  68, 2, "dot3sDeferredTransmissions"        },
 277         {0,  70, 2, "dot3StatsLateCollisions"           },
 278         {0,  72, 2, "etherStatsCollisions"              },
 279         {0,  74, 2, "dot3StatsExcessiveCollisions"      },
 280         {0,  76, 2, "dot3OutPauseFrames"                },
 281         {0,  78, 2, "ifOutDiscards"                     },
 282         {0,  80, 2, "dot1dTpPortInDiscards"             },
 283         {0,  82, 2, "ifOutUcastPkts"                    },
 284         {0,  84, 2, "ifOutMulticastPkts"                },
 285         {0,  86, 2, "ifOutBroadcastPkts"                },
 286         {0,  88, 2, "outOampduPkts"                     },
 287         {0,  90, 2, "inOampduPkts"                      },
 288         {0,  92, 2, "inIgmpJoinsSuccess"                },
 289         {0,  94, 2, "inIgmpJoinsFail"                   },
 290         {0,  96, 2, "inMldJoinsSuccess"                 },
 291         {0,  98, 2, "inMldJoinsFail"                    },
 292         {0, 100, 2, "inReportSuppressionDrop"           },
 293         {0, 102, 2, "inLeaveSuppressionDrop"            },
 294         {0, 104, 2, "outIgmpReports"                    },
 295         {0, 106, 2, "outIgmpLeaves"                     },
 296         {0, 108, 2, "outIgmpGeneralQuery"               },
 297         {0, 110, 2, "outIgmpSpecificQuery"              },
 298         {0, 112, 2, "outMldReports"                     },
 299         {0, 114, 2, "outMldLeaves"                      },
 300         {0, 116, 2, "outMldGeneralQuery"                },
 301         {0, 118, 2, "outMldSpecificQuery"               },
 302         {0, 120, 2, "inKnownMulticastPkts"              },
 303 };
 304
 305 #define REG_RD(_smi, _reg, _val)                                        \
 306         do {                                                            \
 307                 err = rtl8366_smi_read_reg(_smi, _reg, _val);           \
 308                 if (err)                                                \
 309                         return err;                                     \
 310         } while (0)
 311
 312 #define REG_WR(_smi, _reg, _val)                                        \
 313         do {                                                            \
 314                 err = rtl8366_smi_write_reg(_smi, _reg, _val);          \
 315                 if (err)                                                \
 316                         return err;                                     \
 317         } while (0)
 318
 319 #define REG_RMW(_smi, _reg, _mask, _val)                                \
 320         do {                                                            \
 321                 err = rtl8366_smi_rmwr(_smi, _reg, _mask, _val);        \
 322                 if (err)                                                \
 323                         return err;                                     \
 324         } while (0)
 325
 326 static const struct rtl8367b_initval rtl8367r_vb_initvals_0[] = {
 327         {0x1B03, 0x0876}, {0x1200, 0x7FC4}, {0x0301, 0x0026}, {0x1722, 0x0E14},
 328         {0x205F, 0x0002}, {0x2059, 0x1A00}, {0x205F, 0x0000}, {0x207F, 0x0002},
 329         {0x2077, 0x0000}, {0x2078, 0x0000}, {0x2079, 0x0000}, {0x207A, 0x0000},
 330         {0x207B, 0x0000}, {0x207F, 0x0000}, {0x205F, 0x0002}, {0x2053, 0x0000},
 331         {0x2054, 0x0000}, {0x2055, 0x0000}, {0x2056, 0x0000}, {0x2057, 0x0000},
 332         {0x205F, 0x0000}, {0x12A4, 0x110A}, {0x12A6, 0x150A}, {0x13F1, 0x0013},
 333         {0x13F4, 0x0010}, {0x13F5, 0x0000}, {0x0018, 0x0F00}, {0x0038, 0x0F00},
 334         {0x0058, 0x0F00}, {0x0078, 0x0F00}, {0x0098, 0x0F00}, {0x12B6, 0x0C02},
 335         {0x12B7, 0x030F}, {0x12B8, 0x11FF}, {0x12BC, 0x0004}, {0x1362, 0x0115},
 336         {0x1363, 0x0002}, {0x1363, 0x0000}, {0x133F, 0x0030}, {0x133E, 0x000E},
 337         {0x221F, 0x0007}, {0x221E, 0x002D}, {0x2218, 0xF030}, {0x221F, 0x0007},
 338         {0x221E, 0x0023}, {0x2216, 0x0005}, {0x2215, 0x00B9}, {0x2219, 0x0044},
 339         {0x2215, 0x00BA}, {0x2219, 0x0020}, {0x2215, 0x00BB}, {0x2219, 0x00C1},
 340         {0x2215, 0x0148}, {0x2219, 0x0096}, {0x2215, 0x016E}, {0x2219, 0x0026},
 341         {0x2216, 0x0000}, {0x2216, 0x0000}, {0x221E, 0x002D}, {0x2218, 0xF010},
 342         {0x221F, 0x0007}, {0x221E, 0x0020}, {0x2215, 0x0D00}, {0x221F, 0x0000},
 343         {0x221F, 0x0000}, {0x2217, 0x2160}, {0x221F, 0x0001}, {0x2210, 0xF25E},
 344         {0x221F, 0x0007}, {0x221E, 0x0042}, {0x2215, 0x0F00}, {0x2215, 0x0F00},
 345         {0x2216, 0x7408}, {0x2215, 0x0E00}, {0x2215, 0x0F00}, {0x2215, 0x0F01},
 346         {0x2216, 0x4000}, {0x2215, 0x0E01}, {0x2215, 0x0F01}, {0x2215, 0x0F02},
 347         {0x2216, 0x9400}, {0x2215, 0x0E02}, {0x2215, 0x0F02}, {0x2215, 0x0F03},
 348         {0x2216, 0x7408}, {0x2215, 0x0E03}, {0x2215, 0x0F03}, {0x2215, 0x0F04},
 349         {0x2216, 0x4008}, {0x2215, 0x0E04}, {0x2215, 0x0F04}, {0x2215, 0x0F05},
 350         {0x2216, 0x9400}, {0x2215, 0x0E05}, {0x2215, 0x0F05}, {0x2215, 0x0F06},
 351         {0x2216, 0x0803}, {0x2215, 0x0E06}, {0x2215, 0x0F06}, {0x2215, 0x0D00},
 352         {0x2215, 0x0100}, {0x221F, 0x0001}, {0x2210, 0xF05E}, {0x221F, 0x0000},
 353         {0x2217, 0x2100}, {0x221F, 0x0000}, {0x220D, 0x0003}, {0x220E, 0x0015},
 354         {0x220D, 0x4003}, {0x220E, 0x0006}, {0x221F, 0x0000}, {0x2200, 0x1340},
 355         {0x133F, 0x0010}, {0x12A0, 0x0058}, {0x12A1, 0x0058}, {0x133E, 0x000E},
 356         {0x133F, 0x0030}, {0x221F, 0x0000}, {0x2210, 0x0166}, {0x221F, 0x0000},
 357         {0x133E, 0x000E}, {0x133F, 0x0010}, {0x133F, 0x0030}, {0x133E, 0x000E},
 358         {0x221F, 0x0005}, {0x2205, 0xFFF6}, {0x2206, 0x0080}, {0x2205, 0x8B6E},
 359         {0x2206, 0x0000}, {0x220F, 0x0100}, {0x2205, 0x8000}, {0x2206, 0x0280},
 360         {0x2206, 0x28F7}, {0x2206, 0x00E0}, {0x2206, 0xFFF7}, {0x2206, 0xA080},
 361         {0x2206, 0x02AE}, {0x2206, 0xF602}, {0x2206, 0x0153}, {0x2206, 0x0201},
 362         {0x2206, 0x6602}, {0x2206, 0x80B9}, {0x2206, 0xE08B}, {0x2206, 0x8CE1},
 363         {0x2206, 0x8B8D}, {0x2206, 0x1E01}, {0x2206, 0xE18B}, {0x2206, 0x8E1E},
 364         {0x2206, 0x01A0}, {0x2206, 0x00E7}, {0x2206, 0xAEDB}, {0x2206, 0xEEE0},
 365         {0x2206, 0x120E}, {0x2206, 0xEEE0}, {0x2206, 0x1300}, {0x2206, 0xEEE0},
 366         {0x2206, 0x2001}, {0x2206, 0xEEE0}, {0x2206, 0x2166}, {0x2206, 0xEEE0},
 367         {0x2206, 0xC463}, {0x2206, 0xEEE0}, {0x2206, 0xC5E8}, {0x2206, 0xEEE0},
 368         {0x2206, 0xC699}, {0x2206, 0xEEE0}, {0x2206, 0xC7C2}, {0x2206, 0xEEE0},
 369         {0x2206, 0xC801}, {0x2206, 0xEEE0}, {0x2206, 0xC913}, {0x2206, 0xEEE0},
 370         {0x2206, 0xCA30}, {0x2206, 0xEEE0}, {0x2206, 0xCB3E}, {0x2206, 0xEEE0},
 371         {0x2206, 0xDCE1}, {0x2206, 0xEEE0}, {0x2206, 0xDD00}, {0x2206, 0xEEE2},
 372         {0x2206, 0x0001}, {0x2206, 0xEEE2}, {0x2206, 0x0100}, {0x2206, 0xEEE4},
 373         {0x2206, 0x8860}, {0x2206, 0xEEE4}, {0x2206, 0x8902}, {0x2206, 0xEEE4},
 374         {0x2206, 0x8C00}, {0x2206, 0xEEE4}, {0x2206, 0x8D30}, {0x2206, 0xEEEA},
 375         {0x2206, 0x1480}, {0x2206, 0xEEEA}, {0x2206, 0x1503}, {0x2206, 0xEEEA},
 376         {0x2206, 0xC600}, {0x2206, 0xEEEA}, {0x2206, 0xC706}, {0x2206, 0xEE85},
 377         {0x2206, 0xEE00}, {0x2206, 0xEE85}, {0x2206, 0xEF00}, {0x2206, 0xEE8B},
 378         {0x2206, 0x6750}, {0x2206, 0xEE8B}, {0x2206, 0x6632}, {0x2206, 0xEE8A},
 379         {0x2206, 0xD448}, {0x2206, 0xEE8A}, {0x2206, 0xD548}, {0x2206, 0xEE8A},
 380         {0x2206, 0xD649}, {0x2206, 0xEE8A}, {0x2206, 0xD7F8}, {0x2206, 0xEE8B},
 381         {0x2206, 0x85E2}, {0x2206, 0xEE8B}, {0x2206, 0x8700}, {0x2206, 0xEEFF},
 382         {0x2206, 0xF600}, {0x2206, 0xEEFF}, {0x2206, 0xF7FC}, {0x2206, 0x04F8},
 383         {0x2206, 0xE08B}, {0x2206, 0x8EAD}, {0x2206, 0x2023}, {0x2206, 0xF620},
 384         {0x2206, 0xE48B}, {0x2206, 0x8E02}, {0x2206, 0x2877}, {0x2206, 0x0225},
 385         {0x2206, 0xC702}, {0x2206, 0x26A1}, {0x2206, 0x0281}, {0x2206, 0xB302},
 386         {0x2206, 0x8496}, {0x2206, 0x0202}, {0x2206, 0xA102}, {0x2206, 0x27F1},
 387         {0x2206, 0x0228}, {0x2206, 0xF902}, {0x2206, 0x2AA0}, {0x2206, 0x0282},
 388         {0x2206, 0xB8E0}, {0x2206, 0x8B8E}, {0x2206, 0xAD21}, {0x2206, 0x08F6},
 389         {0x2206, 0x21E4}, {0x2206, 0x8B8E}, {0x2206, 0x0202}, {0x2206, 0x80E0},
 390         {0x2206, 0x8B8E}, {0x2206, 0xAD22}, {0x2206, 0x05F6}, {0x2206, 0x22E4},
 391         {0x2206, 0x8B8E}, {0x2206, 0xE08B}, {0x2206, 0x8EAD}, {0x2206, 0x2305},
 392         {0x2206, 0xF623}, {0x2206, 0xE48B}, {0x2206, 0x8EE0}, {0x2206, 0x8B8E},
 393         {0x2206, 0xAD24}, {0x2206, 0x08F6}, {0x2206, 0x24E4}, {0x2206, 0x8B8E},
 394         {0x2206, 0x0227}, {0x2206, 0x6AE0}, {0x2206, 0x8B8E}, {0x2206, 0xAD25},
 395         {0x2206, 0x05F6}, {0x2206, 0x25E4}, {0x2206, 0x8B8E}, {0x2206, 0xE08B},
 396         {0x2206, 0x8EAD}, {0x2206, 0x260B}, {0x2206, 0xF626}, {0x2206, 0xE48B},
 397         {0x2206, 0x8E02}, {0x2206, 0x830D}, {0x2206, 0x021D}, {0x2206, 0x6BE0},
 398         {0x2206, 0x8B8E}, {0x2206, 0xAD27}, {0x2206, 0x05F6}, {0x2206, 0x27E4},
 399         {0x2206, 0x8B8E}, {0x2206, 0x0281}, {0x2206, 0x4402}, {0x2206, 0x045C},
 400         {0x2206, 0xFC04}, {0x2206, 0xF8E0}, {0x2206, 0x8B83}, {0x2206, 0xAD23},
 401         {0x2206, 0x30E0}, {0x2206, 0xE022}, {0x2206, 0xE1E0}, {0x2206, 0x2359},
 402         {0x2206, 0x02E0}, {0x2206, 0x85EF}, {0x2206, 0xE585}, {0x2206, 0xEFAC},
 403         {0x2206, 0x2907}, {0x2206, 0x1F01}, {0x2206, 0x9E51}, {0x2206, 0xAD29},
 404         {0x2206, 0x20E0}, {0x2206, 0x8B83}, {0x2206, 0xAD21}, {0x2206, 0x06E1},
 405         {0x2206, 0x8B84}, {0x2206, 0xAD28}, {0x2206, 0x42E0}, {0x2206, 0x8B85},
 406         {0x2206, 0xAD21}, {0x2206, 0x06E1}, {0x2206, 0x8B84}, {0x2206, 0xAD29},
 407         {0x2206, 0x36BF}, {0x2206, 0x34BF}, {0x2206, 0x022C}, {0x2206, 0x31AE},
 408         {0x2206, 0x2EE0}, {0x2206, 0x8B83}, {0x2206, 0xAD21}, {0x2206, 0x10E0},
 409         {0x2206, 0x8B84}, {0x2206, 0xF620}, {0x2206, 0xE48B}, {0x2206, 0x84EE},
 410         {0x2206, 0x8ADA}, {0x2206, 0x00EE}, {0x2206, 0x8ADB}, {0x2206, 0x00E0},
 411         {0x2206, 0x8B85}, {0x2206, 0xAD21}, {0x2206, 0x0CE0}, {0x2206, 0x8B84},
 412         {0x2206, 0xF621}, {0x2206, 0xE48B}, {0x2206, 0x84EE}, {0x2206, 0x8B72},
 413         {0x2206, 0xFFBF}, {0x2206, 0x34C2}, {0x2206, 0x022C}, {0x2206, 0x31FC},
 414         {0x2206, 0x04F8}, {0x2206, 0xFAEF}, {0x2206, 0x69E0}, {0x2206, 0x8B85},
 415         {0x2206, 0xAD21}, {0x2206, 0x42E0}, {0x2206, 0xE022}, {0x2206, 0xE1E0},
 416         {0x2206, 0x2358}, {0x2206, 0xC059}, {0x2206, 0x021E}, {0x2206, 0x01E1},
 417         {0x2206, 0x8B72}, {0x2206, 0x1F10}, {0x2206, 0x9E2F}, {0x2206, 0xE48B},
 418         {0x2206, 0x72AD}, {0x2206, 0x2123}, {0x2206, 0xE18B}, {0x2206, 0x84F7},
 419         {0x2206, 0x29E5}, {0x2206, 0x8B84}, {0x2206, 0xAC27}, {0x2206, 0x10AC},
 420         {0x2206, 0x2605}, {0x2206, 0x0205}, {0x2206, 0x23AE}, {0x2206, 0x1602},
 421         {0x2206, 0x0535}, {0x2206, 0x0282}, {0x2206, 0x30AE}, {0x2206, 0x0E02},
 422         {0x2206, 0x056A}, {0x2206, 0x0282}, {0x2206, 0x75AE}, {0x2206, 0x0602},
 423         {0x2206, 0x04DC}, {0x2206, 0x0282}, {0x2206, 0x04EF}, {0x2206, 0x96FE},
 424         {0x2206, 0xFC04}, {0x2206, 0xF8F9}, {0x2206, 0xE08B}, {0x2206, 0x87AD},
 425         {0x2206, 0x2321}, {0x2206, 0xE0EA}, {0x2206, 0x14E1}, {0x2206, 0xEA15},
 426         {0x2206, 0xAD26}, {0x2206, 0x18F6}, {0x2206, 0x27E4}, {0x2206, 0xEA14},
 427         {0x2206, 0xE5EA}, {0x2206, 0x15F6}, {0x2206, 0x26E4}, {0x2206, 0xEA14},
 428         {0x2206, 0xE5EA}, {0x2206, 0x15F7}, {0x2206, 0x27E4}, {0x2206, 0xEA14},
 429         {0x2206, 0xE5EA}, {0x2206, 0x15FD}, {0x2206, 0xFC04}, {0x2206, 0xF8F9},
 430         {0x2206, 0xE08B}, {0x2206, 0x87AD}, {0x2206, 0x233A}, {0x2206, 0xAD22},
 431         {0x2206, 0x37E0}, {0x2206, 0xE020}, {0x2206, 0xE1E0}, {0x2206, 0x21AC},
 432         {0x2206, 0x212E}, {0x2206, 0xE0EA}, {0x2206, 0x14E1}, {0x2206, 0xEA15},
 433         {0x2206, 0xF627}, {0x2206, 0xE4EA}, {0x2206, 0x14E5}, {0x2206, 0xEA15},
 434         {0x2206, 0xE2EA}, {0x2206, 0x12E3}, {0x2206, 0xEA13}, {0x2206, 0x5A8F},
 435         {0x2206, 0x6A20}, {0x2206, 0xE6EA}, {0x2206, 0x12E7}, {0x2206, 0xEA13},
 436         {0x2206, 0xF726}, {0x2206, 0xE4EA}, {0x2206, 0x14E5}, {0x2206, 0xEA15},
 437         {0x2206, 0xF727}, {0x2206, 0xE4EA}, {0x2206, 0x14E5}, {0x2206, 0xEA15},
 438         {0x2206, 0xFDFC}, {0x2206, 0x04F8}, {0x2206, 0xF9E0}, {0x2206, 0x8B87},
 439         {0x2206, 0xAD23}, {0x2206, 0x38AD}, {0x2206, 0x2135}, {0x2206, 0xE0E0},
 440         {0x2206, 0x20E1}, {0x2206, 0xE021}, {0x2206, 0xAC21}, {0x2206, 0x2CE0},
 441         {0x2206, 0xEA14}, {0x2206, 0xE1EA}, {0x2206, 0x15F6}, {0x2206, 0x27E4},
 442         {0x2206, 0xEA14}, {0x2206, 0xE5EA}, {0x2206, 0x15E2}, {0x2206, 0xEA12},
 443         {0x2206, 0xE3EA}, {0x2206, 0x135A}, {0x2206, 0x8FE6}, {0x2206, 0xEA12},
 444         {0x2206, 0xE7EA}, {0x2206, 0x13F7}, {0x2206, 0x26E4}, {0x2206, 0xEA14},
 445         {0x2206, 0xE5EA}, {0x2206, 0x15F7}, {0x2206, 0x27E4}, {0x2206, 0xEA14},
 446         {0x2206, 0xE5EA}, {0x2206, 0x15FD}, {0x2206, 0xFC04}, {0x2206, 0xF8FA},
 447         {0x2206, 0xEF69}, {0x2206, 0xE08B}, {0x2206, 0x86AD}, {0x2206, 0x2146},
 448         {0x2206, 0xE0E0}, {0x2206, 0x22E1}, {0x2206, 0xE023}, {0x2206, 0x58C0},
 449         {0x2206, 0x5902}, {0x2206, 0x1E01}, {0x2206, 0xE18B}, {0x2206, 0x651F},
 450         {0x2206, 0x109E}, {0x2206, 0x33E4}, {0x2206, 0x8B65}, {0x2206, 0xAD21},
 451         {0x2206, 0x22AD}, {0x2206, 0x272A}, {0x2206, 0xD400}, {0x2206, 0x01BF},
 452         {0x2206, 0x34F2}, {0x2206, 0x022C}, {0x2206, 0xA2BF}, {0x2206, 0x34F5},
 453         {0x2206, 0x022C}, {0x2206, 0xE0E0}, {0x2206, 0x8B67}, {0x2206, 0x1B10},
 454         {0x2206, 0xAA14}, {0x2206, 0xE18B}, {0x2206, 0x660D}, {0x2206, 0x1459},
 455         {0x2206, 0x0FAE}, {0x2206, 0x05E1}, {0x2206, 0x8B66}, {0x2206, 0x590F},
 456         {0x2206, 0xBF85}, {0x2206, 0x6102}, {0x2206, 0x2CA2}, {0x2206, 0xEF96},
 457         {0x2206, 0xFEFC}, {0x2206, 0x04F8}, {0x2206, 0xF9FA}, {0x2206, 0xFBEF},
 458         {0x2206, 0x79E2}, {0x2206, 0x8AD2}, {0x2206, 0xAC19}, {0x2206, 0x2DE0},
 459         {0x2206, 0xE036}, {0x2206, 0xE1E0}, {0x2206, 0x37EF}, {0x2206, 0x311F},
 460         {0x2206, 0x325B}, {0x2206, 0x019E}, {0x2206, 0x1F7A}, {0x2206, 0x0159},
 461         {0x2206, 0x019F}, {0x2206, 0x0ABF}, {0x2206, 0x348E}, {0x2206, 0x022C},
 462         {0x2206, 0x31F6}, {0x2206, 0x06AE}, {0x2206, 0x0FF6}, {0x2206, 0x0302},
 463         {0x2206, 0x0470}, {0x2206, 0xF703}, {0x2206, 0xF706}, {0x2206, 0xBF34},
 464         {0x2206, 0x9302}, {0x2206, 0x2C31}, {0x2206, 0xAC1A}, {0x2206, 0x25E0},
 465         {0x2206, 0xE022}, {0x2206, 0xE1E0}, {0x2206, 0x23EF}, {0x2206, 0x300D},
 466         {0x2206, 0x311F}, {0x2206, 0x325B}, {0x2206, 0x029E}, {0x2206, 0x157A},
 467         {0x2206, 0x0258}, {0x2206, 0xC4A0}, {0x2206, 0x0408}, {0x2206, 0xBF34},
 468         {0x2206, 0x9E02}, {0x2206, 0x2C31}, {0x2206, 0xAE06}, {0x2206, 0xBF34},
 469         {0x2206, 0x9C02}, {0x2206, 0x2C31}, {0x2206, 0xAC1B}, {0x2206, 0x4AE0},
 470         {0x2206, 0xE012}, {0x2206, 0xE1E0}, {0x2206, 0x13EF}, {0x2206, 0x300D},
 471         {0x2206, 0x331F}, {0x2206, 0x325B}, {0x2206, 0x1C9E}, {0x2206, 0x3AEF},
 472         {0x2206, 0x325B}, {0x2206, 0x1C9F}, {0x2206, 0x09BF}, {0x2206, 0x3498},
 473         {0x2206, 0x022C}, {0x2206, 0x3102}, {0x2206, 0x83C5}, {0x2206, 0x5A03},
 474         {0x2206, 0x0D03}, {0x2206, 0x581C}, {0x2206, 0x1E20}, {0x2206, 0x0207},
 475         {0x2206, 0xA0A0}, {0x2206, 0x000E}, {0x2206, 0x0284}, {0x2206, 0x17AD},
 476         {0x2206, 0x1817}, {0x2206, 0xBF34}, {0x2206, 0x9A02}, {0x2206, 0x2C31},
 477         {0x2206, 0xAE0F}, {0x2206, 0xBF34}, {0x2206, 0xC802}, {0x2206, 0x2C31},
 478         {0x2206, 0xBF34}, {0x2206, 0xC502}, {0x2206, 0x2C31}, {0x2206, 0x0284},
 479         {0x2206, 0x52E6}, {0x2206, 0x8AD2}, {0x2206, 0xEF97}, {0x2206, 0xFFFE},
 480         {0x2206, 0xFDFC}, {0x2206, 0x04F8}, {0x2206, 0xBF34}, {0x2206, 0xDA02},
 481         {0x2206, 0x2CE0}, {0x2206, 0xE58A}, {0x2206, 0xD3BF}, {0x2206, 0x34D4},
 482         {0x2206, 0x022C}, {0x2206, 0xE00C}, {0x2206, 0x1159}, {0x2206, 0x02E0},
 483         {0x2206, 0x8AD3}, {0x2206, 0x1E01}, {0x2206, 0xE48A}, {0x2206, 0xD3D1},
 484         {0x2206, 0x00BF}, {0x2206, 0x34DA}, {0x2206, 0x022C}, {0x2206, 0xA2D1},
 485         {0x2206, 0x01BF}, {0x2206, 0x34D4}, {0x2206, 0x022C}, {0x2206, 0xA2BF},
 486         {0x2206, 0x34CB}, {0x2206, 0x022C}, {0x2206, 0xE0E5}, {0x2206, 0x8ACE},
 487         {0x2206, 0xBF85}, {0x2206, 0x6702}, {0x2206, 0x2CE0}, {0x2206, 0xE58A},
 488         {0x2206, 0xCFBF}, {0x2206, 0x8564}, {0x2206, 0x022C}, {0x2206, 0xE0E5},
 489         {0x2206, 0x8AD0}, {0x2206, 0xBF85}, {0x2206, 0x6A02}, {0x2206, 0x2CE0},
 490         {0x2206, 0xE58A}, {0x2206, 0xD1FC}, {0x2206, 0x04F8}, {0x2206, 0xE18A},
 491         {0x2206, 0xD1BF}, {0x2206, 0x856A}, {0x2206, 0x022C}, {0x2206, 0xA2E1},
 492         {0x2206, 0x8AD0}, {0x2206, 0xBF85}, {0x2206, 0x6402}, {0x2206, 0x2CA2},
 493         {0x2206, 0xE18A}, {0x2206, 0xCFBF}, {0x2206, 0x8567}, {0x2206, 0x022C},
 494         {0x2206, 0xA2E1}, {0x2206, 0x8ACE}, {0x2206, 0xBF34}, {0x2206, 0xCB02},
 495         {0x2206, 0x2CA2}, {0x2206, 0xE18A}, {0x2206, 0xD3BF}, {0x2206, 0x34DA},
 496         {0x2206, 0x022C}, {0x2206, 0xA2E1}, {0x2206, 0x8AD3}, {0x2206, 0x0D11},
 497         {0x2206, 0xBF34}, {0x2206, 0xD402}, {0x2206, 0x2CA2}, {0x2206, 0xFC04},
 498         {0x2206, 0xF9A0}, {0x2206, 0x0405}, {0x2206, 0xE38A}, {0x2206, 0xD4AE},
 499         {0x2206, 0x13A0}, {0x2206, 0x0805}, {0x2206, 0xE38A}, {0x2206, 0xD5AE},
 500         {0x2206, 0x0BA0}, {0x2206, 0x0C05}, {0x2206, 0xE38A}, {0x2206, 0xD6AE},
 501         {0x2206, 0x03E3}, {0x2206, 0x8AD7}, {0x2206, 0xEF13}, {0x2206, 0xBF34},
 502         {0x2206, 0xCB02}, {0x2206, 0x2CA2}, {0x2206, 0xEF13}, {0x2206, 0x0D11},
 503         {0x2206, 0xBF85}, {0x2206, 0x6702}, {0x2206, 0x2CA2}, {0x2206, 0xEF13},
 504         {0x2206, 0x0D14}, {0x2206, 0xBF85}, {0x2206, 0x6402}, {0x2206, 0x2CA2},
 505         {0x2206, 0xEF13}, {0x2206, 0x0D17}, {0x2206, 0xBF85}, {0x2206, 0x6A02},
 506         {0x2206, 0x2CA2}, {0x2206, 0xFD04}, {0x2206, 0xF8E0}, {0x2206, 0x8B85},
 507         {0x2206, 0xAD27}, {0x2206, 0x2DE0}, {0x2206, 0xE036}, {0x2206, 0xE1E0},
 508         {0x2206, 0x37E1}, {0x2206, 0x8B73}, {0x2206, 0x1F10}, {0x2206, 0x9E20},
 509         {0x2206, 0xE48B}, {0x2206, 0x73AC}, {0x2206, 0x200B}, {0x2206, 0xAC21},
 510         {0x2206, 0x0DAC}, {0x2206, 0x250F}, {0x2206, 0xAC27}, {0x2206, 0x0EAE},
 511         {0x2206, 0x0F02}, {0x2206, 0x84CC}, {0x2206, 0xAE0A}, {0x2206, 0x0284},
 512         {0x2206, 0xD1AE}, {0x2206, 0x05AE}, {0x2206, 0x0302}, {0x2206, 0x84D8},
 513         {0x2206, 0xFC04}, {0x2206, 0xEE8B}, {0x2206, 0x6800}, {0x2206, 0x0402},
 514         {0x2206, 0x84E5}, {0x2206, 0x0285}, {0x2206, 0x2804}, {0x2206, 0x0285},
 515         {0x2206, 0x4904}, {0x2206, 0xEE8B}, {0x2206, 0x6800}, {0x2206, 0xEE8B},
 516         {0x2206, 0x6902}, {0x2206, 0x04F8}, {0x2206, 0xF9E0}, {0x2206, 0x8B85},
 517         {0x2206, 0xAD26}, {0x2206, 0x38D0}, {0x2206, 0x0B02}, {0x2206, 0x2B4D},
 518         {0x2206, 0x5882}, {0x2206, 0x7882}, {0x2206, 0x9F2D}, {0x2206, 0xE08B},
 519         {0x2206, 0x68E1}, {0x2206, 0x8B69}, {0x2206, 0x1F10}, {0x2206, 0x9EC8},
 520         {0x2206, 0x10E4}, {0x2206, 0x8B68}, {0x2206, 0xE0E0}, {0x2206, 0x00E1},
 521         {0x2206, 0xE001}, {0x2206, 0xF727}, {0x2206, 0xE4E0}, {0x2206, 0x00E5},
 522         {0x2206, 0xE001}, {0x2206, 0xE2E0}, {0x2206, 0x20E3}, {0x2206, 0xE021},
 523         {0x2206, 0xAD30}, {0x2206, 0xF7F6}, {0x2206, 0x27E4}, {0x2206, 0xE000},
 524         {0x2206, 0xE5E0}, {0x2206, 0x01FD}, {0x2206, 0xFC04}, {0x2206, 0xF8FA},
 525         {0x2206, 0xEF69}, {0x2206, 0xE08B}, {0x2206, 0x86AD}, {0x2206, 0x2212},
 526         {0x2206, 0xE0E0}, {0x2206, 0x14E1}, {0x2206, 0xE015}, {0x2206, 0xAD26},
 527         {0x2206, 0x9CE1}, {0x2206, 0x85E0}, {0x2206, 0xBF85}, {0x2206, 0x6D02},
 528         {0x2206, 0x2CA2}, {0x2206, 0xEF96}, {0x2206, 0xFEFC}, {0x2206, 0x04F8},
 529         {0x2206, 0xFAEF}, {0x2206, 0x69E0}, {0x2206, 0x8B86}, {0x2206, 0xAD22},
 530         {0x2206, 0x09E1}, {0x2206, 0x85E1}, {0x2206, 0xBF85}, {0x2206, 0x6D02},
 531         {0x2206, 0x2CA2}, {0x2206, 0xEF96}, {0x2206, 0xFEFC}, {0x2206, 0x0464},
 532         {0x2206, 0xE48C}, {0x2206, 0xFDE4}, {0x2206, 0x80CA}, {0x2206, 0xE480},
 533         {0x2206, 0x66E0}, {0x2206, 0x8E70}, {0x2206, 0xE076}, {0x2205, 0xE142},
 534         {0x2206, 0x0701}, {0x2205, 0xE140}, {0x2206, 0x0405}, {0x220F, 0x0000},
 535         {0x221F, 0x0000}, {0x2200, 0x1340}, {0x133E, 0x000E}, {0x133F, 0x0010},
 536         {0x13EB, 0x11BB}
 537 };
 538
 539 static const struct rtl8367b_initval rtl8367r_vb_initvals_1[] = {
 540         {0x1B03, 0x0876}, {0x1200, 0x7FC4}, {0x1305, 0xC000}, {0x121E, 0x03CA},
 541         {0x1233, 0x0352}, {0x1234, 0x0064}, {0x1237, 0x0096}, {0x1238, 0x0078},
 542         {0x1239, 0x0084}, {0x123A, 0x0030}, {0x205F, 0x0002}, {0x2059, 0x1A00},
 543         {0x205F, 0x0000}, {0x207F, 0x0002}, {0x2077, 0x0000}, {0x2078, 0x0000},
 544         {0x2079, 0x0000}, {0x207A, 0x0000}, {0x207B, 0x0000}, {0x207F, 0x0000},
 545         {0x205F, 0x0002}, {0x2053, 0x0000}, {0x2054, 0x0000}, {0x2055, 0x0000},
 546         {0x2056, 0x0000}, {0x2057, 0x0000}, {0x205F, 0x0000}, {0x133F, 0x0030},
 547         {0x133E, 0x000E}, {0x221F, 0x0005}, {0x2205, 0x8B86}, {0x2206, 0x800E},
 548         {0x221F, 0x0000}, {0x133F, 0x0010}, {0x12A3, 0x2200}, {0x6107, 0xE58B},
 549         {0x6103, 0xA970}, {0x0018, 0x0F00}, {0x0038, 0x0F00}, {0x0058, 0x0F00},
 550         {0x0078, 0x0F00}, {0x0098, 0x0F00}, {0x133F, 0x0030}, {0x133E, 0x000E},
 551         {0x221F, 0x0005}, {0x2205, 0x8B6E}, {0x2206, 0x0000}, {0x220F, 0x0100},
 552         {0x2205, 0xFFF6}, {0x2206, 0x0080}, {0x2205, 0x8000}, {0x2206, 0x0280},
 553         {0x2206, 0x2BF7}, {0x2206, 0x00E0}, {0x2206, 0xFFF7}, {0x2206, 0xA080},
 554         {0x2206, 0x02AE}, {0x2206, 0xF602}, {0x2206, 0x0153}, {0x2206, 0x0201},
 555         {0x2206, 0x6602}, {0x2206, 0x8044}, {0x2206, 0x0201}, {0x2206, 0x7CE0},
 556         {0x2206, 0x8B8C}, {0x2206, 0xE18B}, {0x2206, 0x8D1E}, {0x2206, 0x01E1},
 557         {0x2206, 0x8B8E}, {0x2206, 0x1E01}, {0x2206, 0xA000}, {0x2206, 0xE4AE},
 558         {0x2206, 0xD8EE}, {0x2206, 0x85C0}, {0x2206, 0x00EE}, {0x2206, 0x85C1},
 559         {0x2206, 0x00EE}, {0x2206, 0x8AFC}, {0x2206, 0x07EE}, {0x2206, 0x8AFD},
 560         {0x2206, 0x73EE}, {0x2206, 0xFFF6}, {0x2206, 0x00EE}, {0x2206, 0xFFF7},
 561         {0x2206, 0xFC04}, {0x2206, 0xF8E0}, {0x2206, 0x8B8E}, {0x2206, 0xAD20},
 562         {0x2206, 0x0302}, {0x2206, 0x8050}, {0x2206, 0xFC04}, {0x2206, 0xF8F9},
 563         {0x2206, 0xE08B}, {0x2206, 0x85AD}, {0x2206, 0x2548}, {0x2206, 0xE08A},
 564         {0x2206, 0xE4E1}, {0x2206, 0x8AE5}, {0x2206, 0x7C00}, {0x2206, 0x009E},
 565         {0x2206, 0x35EE}, {0x2206, 0x8AE4}, {0x2206, 0x00EE}, {0x2206, 0x8AE5},
 566         {0x2206, 0x00E0}, {0x2206, 0x8AFC}, {0x2206, 0xE18A}, {0x2206, 0xFDE2},
 567         {0x2206, 0x85C0}, {0x2206, 0xE385}, {0x2206, 0xC102}, {0x2206, 0x2DAC},
 568         {0x2206, 0xAD20}, {0x2206, 0x12EE}, {0x2206, 0x8AE4}, {0x2206, 0x03EE},
 569         {0x2206, 0x8AE5}, {0x2206, 0xB7EE}, {0x2206, 0x85C0}, {0x2206, 0x00EE},
 570         {0x2206, 0x85C1}, {0x2206, 0x00AE}, {0x2206, 0x1115}, {0x2206, 0xE685},
 571         {0x2206, 0xC0E7}, {0x2206, 0x85C1}, {0x2206, 0xAE08}, {0x2206, 0xEE85},
 572         {0x2206, 0xC000}, {0x2206, 0xEE85}, {0x2206, 0xC100}, {0x2206, 0xFDFC},
 573         {0x2206, 0x0400}, {0x2205, 0xE142}, {0x2206, 0x0701}, {0x2205, 0xE140},
 574         {0x2206, 0x0405}, {0x220F, 0x0000}, {0x221F, 0x0000}, {0x133E, 0x000E},
 575         {0x133F, 0x0010}, {0x13EB, 0x11BB}, {0x207F, 0x0002}, {0x2073, 0x1D22},
 576         {0x207F, 0x0000}, {0x133F, 0x0030}, {0x133E, 0x000E}, {0x2200, 0x1340},
 577         {0x133E, 0x000E}, {0x133F, 0x0010},
 578 };
 579
 580 static int rtl8367b_write_initvals(struct rtl8366_smi *smi,
 581                                   const struct rtl8367b_initval *initvals,
 582                                   int count)
 583 {
 584         int err;
 585         int i;
 586
 587         for (i = 0; i < count; i++)
 588                 REG_WR(smi, initvals[i].reg, initvals[i].val);
 589
 590         return 0;
 591 }
 592
 593 static int rtl8367b_read_phy_reg(struct rtl8366_smi *smi,
 594                                 u32 phy_addr, u32 phy_reg, u32 *val)
 595 {
 596         int timeout;
 597         u32 data;
 598         int err;
 599
 600         if (phy_addr > RTL8367B_PHY_ADDR_MAX)
 601                 return -EINVAL;
 602
 603         if (phy_reg > RTL8367B_PHY_REG_MAX)
 604                 return -EINVAL;
 605
 606         REG_RD(smi, RTL8367B_IA_STATUS_REG, &data);
 607         if (data & RTL8367B_IA_STATUS_PHY_BUSY)
 608                 return -ETIMEDOUT;
 609
 610         /* prepare address */
 611         REG_WR(smi, RTL8367B_IA_ADDRESS_REG,
 612                RTL8367B_INTERNAL_PHY_REG(phy_addr, phy_reg));
 613
 614         /* send read command */
 615         REG_WR(smi, RTL8367B_IA_CTRL_REG,
 616                RTL8367B_IA_CTRL_CMD_MASK | RTL8367B_IA_CTRL_RW_READ);
 617
 618         timeout = 5;
 619         do {
 620                 REG_RD(smi, RTL8367B_IA_STATUS_REG, &data);
 621                 if ((data & RTL8367B_IA_STATUS_PHY_BUSY) == 0)
 622                         break;
 623
 624                 if (timeout--) {
 625                         dev_err(smi->parent, "phy read timed out\n");
 626                         return -ETIMEDOUT;
 627                 }
 628
 629                 udelay(1);
 630         } while (1);
 631
 632         /* read data */
 633         REG_RD(smi, RTL8367B_IA_READ_DATA_REG, val);
 634
 635         dev_dbg(smi->parent, "phy_read: addr:%02x, reg:%02x, val:%04x\n",
 636                 phy_addr, phy_reg, *val);
 637         return 0;
 638 }
 639
 640 static int rtl8367b_write_phy_reg(struct rtl8366_smi *smi,
 641                                  u32 phy_addr, u32 phy_reg, u32 val)
 642 {
 643         int timeout;
 644         u32 data;
 645         int err;
 646
 647         dev_dbg(smi->parent, "phy_write: addr:%02x, reg:%02x, val:%04x\n",
 648                 phy_addr, phy_reg, val);
 649
 650         if (phy_addr > RTL8367B_PHY_ADDR_MAX)
 651                 return -EINVAL;
 652
 653         if (phy_reg > RTL8367B_PHY_REG_MAX)
 654                 return -EINVAL;
 655
 656         REG_RD(smi, RTL8367B_IA_STATUS_REG, &data);
 657         if (data & RTL8367B_IA_STATUS_PHY_BUSY)
 658                 return -ETIMEDOUT;
 659
 660         /* preapre data */
 661         REG_WR(smi, RTL8367B_IA_WRITE_DATA_REG, val);
 662
 663         /* prepare address */
 664         REG_WR(smi, RTL8367B_IA_ADDRESS_REG,
 665                RTL8367B_INTERNAL_PHY_REG(phy_addr, phy_reg));
 666
 667         /* send write command */
 668         REG_WR(smi, RTL8367B_IA_CTRL_REG,
 669                RTL8367B_IA_CTRL_CMD_MASK | RTL8367B_IA_CTRL_RW_WRITE);
 670
 671         timeout = 5;
 672         do {
 673                 REG_RD(smi, RTL8367B_IA_STATUS_REG, &data);
 674                 if ((data & RTL8367B_IA_STATUS_PHY_BUSY) == 0)
 675                         break;
 676
 677                 if (timeout--) {
 678                         dev_err(smi->parent, "phy write timed out\n");
 679                         return -ETIMEDOUT;
 680                 }
 681
 682                 udelay(1);
 683         } while (1);
 684
 685         return 0;
 686 }
 687
 688 static int rtl8367b_init_regs(struct rtl8366_smi *smi)
 689 {
 690         const struct rtl8367b_initval *initvals;
 691         u32 chip_ver;
 692         u32 rlvid;
 693         int count;
 694         int err;
 695
 696         REG_WR(smi, RTL8367B_RTL_MAGIC_ID_REG, RTL8367B_RTL_MAGIC_ID_VAL);
 697         REG_RD(smi, RTL8367B_CHIP_VER_REG, &chip_ver);
 698
 699         rlvid = (chip_ver >> RTL8367B_CHIP_VER_RLVID_SHIFT) &
 700                 RTL8367B_CHIP_VER_RLVID_MASK;
 701
 702         switch (rlvid) {
 703         case 0:
 704                 initvals = rtl8367r_vb_initvals_0;
 705                 count = ARRAY_SIZE(rtl8367r_vb_initvals_0);
 706                 break;
 707
 708         case 1:
 709                 initvals = rtl8367r_vb_initvals_1;
 710                 count = ARRAY_SIZE(rtl8367r_vb_initvals_1);
 711                 break;
 712
 713         default:
 714                 dev_err(smi->parent, "unknow rlvid %u\n", rlvid);
 715                 return -ENODEV;
 716         }
 717
 718         /* TODO: disable RLTP */
 719
 720         return rtl8367b_write_initvals(smi, initvals, count);
 721 }
 722
 723 static int rtl8367b_reset_chip(struct rtl8366_smi *smi)
 724 {
 725         int timeout = 10;
 726         int err;
 727         u32 data;
 728
 729         REG_WR(smi, RTL8367B_CHIP_RESET_REG, RTL8367B_CHIP_RESET_HW);
 730         msleep(RTL8367B_RESET_DELAY);
 731
 732         do {
 733                 REG_RD(smi, RTL8367B_CHIP_RESET_REG, &data);
 734                 if (!(data & RTL8367B_CHIP_RESET_HW))
 735                         break;
 736
 737                 msleep(1);
 738         } while (--timeout);
 739
 740         if (!timeout) {
 741                 dev_err(smi->parent, "chip reset timed out\n");
 742                 return -ETIMEDOUT;
 743         }
 744
 745         return 0;
 746 }
 747
 748 static int rtl8367b_extif_set_mode(struct rtl8366_smi *smi, int id,
 749                                    enum rtl8367_extif_mode mode)
 750 {
 751         int err;
 752
 753         /* set port mode */
 754         switch (mode) {
 755         case RTL8367_EXTIF_MODE_RGMII:
 756         case RTL8367_EXTIF_MODE_RGMII_33V:
 757                 REG_WR(smi, RTL8367B_CHIP_DEBUG0_REG, 0x0367);
 758                 REG_WR(smi, RTL8367B_CHIP_DEBUG1_REG, 0x7777);
 759                 break;
 760
 761         case RTL8367_EXTIF_MODE_TMII_MAC:
 762         case RTL8367_EXTIF_MODE_TMII_PHY:
 763                 REG_RMW(smi, RTL8367B_BYPASS_LINE_RATE_REG,
 764                         BIT((id + 1) % 2), BIT((id + 1) % 2));
 765                 break;
 766
 767         case RTL8367_EXTIF_MODE_GMII:
 768                 REG_RMW(smi, RTL8367B_CHIP_DEBUG0_REG,
 769                         RTL8367B_CHIP_DEBUG0_DUMMY0(id),
 770                         RTL8367B_CHIP_DEBUG0_DUMMY0(id));
 771                 REG_RMW(smi, RTL8367B_EXT_RGMXF_REG(id), BIT(6), BIT(6));
 772                 break;
 773
 774         case RTL8367_EXTIF_MODE_MII_MAC:
 775         case RTL8367_EXTIF_MODE_MII_PHY:
 776         case RTL8367_EXTIF_MODE_DISABLED:
 777                 REG_RMW(smi, RTL8367B_BYPASS_LINE_RATE_REG,
 778                         BIT((id + 1) % 2), 0);
 779                 REG_RMW(smi, RTL8367B_EXT_RGMXF_REG(id), BIT(6), 0);
 780                 break;
 781
 782         default:
 783                 dev_err(smi->parent,
 784                         "invalid mode for external interface %d\n", id);
 785                 return -EINVAL;
 786         }
 787
 788         REG_RMW(smi, RTL8367B_DIS_REG,
 789                 RTL8367B_DIS_RGMII_MASK << RTL8367B_DIS_RGMII_SHIFT(id),
 790                 mode << RTL8367B_DIS_RGMII_SHIFT(id));
 791
 792         return 0;
 793 }
 794
 795 static int rtl8367b_extif_set_force(struct rtl8366_smi *smi, int id,
 796                                     struct rtl8367_port_ability *pa)
 797 {
 798         u32 mask;
 799         u32 val;
 800         int err;
 801
 802         mask = (RTL8367B_DI_FORCE_MODE |
 803                 RTL8367B_DI_FORCE_NWAY |
 804                 RTL8367B_DI_FORCE_TXPAUSE |
 805                 RTL8367B_DI_FORCE_RXPAUSE |
 806                 RTL8367B_DI_FORCE_LINK |
 807                 RTL8367B_DI_FORCE_DUPLEX |
 808                 RTL8367B_DI_FORCE_SPEED_MASK);
 809
 810         val = pa->speed;
 811         val |= pa->force_mode ? RTL8367B_DI_FORCE_MODE : 0;
 812         val |= pa->nway ? RTL8367B_DI_FORCE_NWAY : 0;
 813         val |= pa->txpause ? RTL8367B_DI_FORCE_TXPAUSE : 0;
 814         val |= pa->rxpause ? RTL8367B_DI_FORCE_RXPAUSE : 0;
 815         val |= pa->link ? RTL8367B_DI_FORCE_LINK : 0;
 816         val |= pa->duplex ? RTL8367B_DI_FORCE_DUPLEX : 0;
 817
 818         REG_RMW(smi, RTL8367B_DI_FORCE_REG(id), mask, val);
 819
 820         return 0;
 821 }
 822
 823 static int rtl8367b_extif_set_rgmii_delay(struct rtl8366_smi *smi, int id,
 824                                          unsigned txdelay, unsigned rxdelay)
 825 {
 826         u32 mask;
 827         u32 val;
 828         int err;
 829
 830         mask = (RTL8367B_EXT_RGMXF_RXDELAY_MASK |
 831                 (RTL8367B_EXT_RGMXF_TXDELAY_MASK <<
 832                         RTL8367B_EXT_RGMXF_TXDELAY_SHIFT));
 833
 834         val = rxdelay;
 835         val |= txdelay << RTL8367B_EXT_RGMXF_TXDELAY_SHIFT;
 836
 837         REG_RMW(smi, RTL8367B_EXT_RGMXF_REG(id), mask, val);
 838
 839         return 0;
 840 }
 841
 842 static int rtl8367b_extif_init(struct rtl8366_smi *smi, int id,
 843                                struct rtl8367_extif_config *cfg)
 844 {
 845         enum rtl8367_extif_mode mode;
 846         int err;
 847
 848         mode = (cfg) ? cfg->mode : RTL8367_EXTIF_MODE_DISABLED;
 849
 850         err = rtl8367b_extif_set_mode(smi, id, mode);
 851         if (err)
 852                 return err;
 853
 854         if (mode != RTL8367_EXTIF_MODE_DISABLED) {
 855                 err = rtl8367b_extif_set_force(smi, id, &cfg->ability);
 856                 if (err)
 857                         return err;
 858
 859                 err = rtl8367b_extif_set_rgmii_delay(smi, id, cfg->txdelay,
 860                                                      cfg->rxdelay);
 861                 if (err)
 862                         return err;
 863         }
 864
 865         return 0;
 866 }
 867
 868 #ifdef CONFIG_OF
 869 static int rtl8367b_extif_init_of(struct rtl8366_smi *smi, int id,
 870                                   const char *name)
 871 {
 872         struct rtl8367_extif_config *cfg;
 873         const __be32 *prop;
 874         int size;
 875         int err;
 876
 877         prop = of_get_property(smi->parent->of_node, name, &size);
 878         if (!prop)
 879                 return rtl8367b_extif_init(smi, id, NULL);
 880
 881         if (size != (9 * sizeof(*prop))) {
 882                 dev_err(smi->parent, "%s property is invalid\n", name);
 883                 return -EINVAL;
 884         }
 885
 886         cfg = kzalloc(sizeof(struct rtl8367_extif_config), GFP_KERNEL);
 887         if (!cfg)
 888                 return -ENOMEM;
 889
 890         cfg->txdelay = be32_to_cpup(prop++);
 891         cfg->rxdelay = be32_to_cpup(prop++);
 892         cfg->mode = be32_to_cpup(prop++);
 893         cfg->ability.force_mode = be32_to_cpup(prop++);
 894         cfg->ability.txpause = be32_to_cpup(prop++);
 895         cfg->ability.rxpause = be32_to_cpup(prop++);
 896         cfg->ability.link = be32_to_cpup(prop++);
 897         cfg->ability.duplex = be32_to_cpup(prop++);
 898         cfg->ability.speed = be32_to_cpup(prop++);
 899
 900         err = rtl8367b_extif_init(smi, id, cfg);
 901         kfree(cfg);
 902
 903         return err;
 904 }
 905 #else
 906 static int rtl8367b_extif_init_of(struct rtl8366_smi *smi, int id,
 907                                   const char *name)
 908 {
 909         return -EINVAL;
 910 }
 911 #endif
 912
 913 static int rtl8367b_setup(struct rtl8366_smi *smi)
 914 {
 915         struct rtl8367_platform_data *pdata;
 916         int err;
 917         int i;
 918
 919         pdata = smi->parent->platform_data;
 920
 921         err = rtl8367b_init_regs(smi);
 922         if (err)
 923                 return err;
 924
 925         /* initialize external interfaces */
 926         if (smi->parent->of_node) {
 927                 err = rtl8367b_extif_init_of(smi, 0, "realtek,extif0");
 928                 if (err)
 929                         return err;
 930
 931                 err = rtl8367b_extif_init_of(smi, 1, "realtek,extif1");
 932                 if (err)
 933                         return err;
 934         } else {
 935                 err = rtl8367b_extif_init(smi, 0, pdata->extif0_cfg);
 936                 if (err)
 937                         return err;
 938
 939                 err = rtl8367b_extif_init(smi, 1, pdata->extif1_cfg);
 940                 if (err)
 941                         return err;
 942         }
 943
 944         /* set maximum packet length to 1536 bytes */
 945         REG_RMW(smi, RTL8367B_SWC0_REG, RTL8367B_SWC0_MAX_LENGTH_MASK,
 946                 RTL8367B_SWC0_MAX_LENGTH_1536);
 947
 948         /*
 949          * discard VLAN tagged packets if the port is not a member of
 950          * the VLAN with which the packets is associated.
 951          */
 952         REG_WR(smi, RTL8367B_VLAN_INGRESS_REG, RTL8367B_PORTS_ALL);
 953
 954         /*
 955          * Setup egress tag mode for each port.
 956          */
 957         for (i = 0; i < RTL8367B_NUM_PORTS; i++)
 958                 REG_RMW(smi,
 959                         RTL8367B_PORT_MISC_CFG_REG(i),
 960                         RTL8367B_PORT_MISC_CFG_EGRESS_MODE_MASK <<
 961                                 RTL8367B_PORT_MISC_CFG_EGRESS_MODE_SHIFT,
 962                         RTL8367B_PORT_MISC_CFG_EGRESS_MODE_ORIGINAL <<
 963                                 RTL8367B_PORT_MISC_CFG_EGRESS_MODE_SHIFT);
 964
 965         return 0;
 966 }
 967
 968 static int rtl8367b_get_mib_counter(struct rtl8366_smi *smi, int counter,
 969                                     int port, unsigned long long *val)
 970 {
 971         struct rtl8366_mib_counter *mib;
 972         int offset;
 973         int i;
 974         int err;
 975         u32 addr, data;
 976         u64 mibvalue;
 977
 978         if (port > RTL8367B_NUM_PORTS ||
 979             counter >= RTL8367B_NUM_MIB_COUNTERS)
 980                 return -EINVAL;
 981
 982         mib = &rtl8367b_mib_counters[counter];
 983         addr = RTL8367B_MIB_COUNTER_PORT_OFFSET * port + mib->offset;
 984
 985         /*
 986          * Writing access counter address first
 987          * then ASIC will prepare 64bits counter wait for being retrived
 988          */
 989         REG_WR(smi, RTL8367B_MIB_ADDRESS_REG, addr >> 2);
 990
 991         /* read MIB control register */
 992         REG_RD(smi, RTL8367B_MIB_CTRL0_REG(0), &data);
 993
 994         if (data & RTL8367B_MIB_CTRL0_BUSY_MASK)
 995                 return -EBUSY;
 996
 997         if (data & RTL8367B_MIB_CTRL0_RESET_MASK)
 998                 return -EIO;
 999
1000         if (mib->length == 4)
1001                 offset = 3;
1002         else
1003                 offset = (mib->offset + 1) % 4;
1004
1005         mibvalue = 0;
1006         for (i = 0; i < mib->length; i++) {
1007                 REG_RD(smi, RTL8367B_MIB_COUNTER_REG(offset - i), &data);
1008                 mibvalue = (mibvalue << 16) | (data & 0xFFFF);
1009         }
1010
1011         *val = mibvalue;
1012         return 0;
1013 }
1014
1015 static int rtl8367b_get_vlan_4k(struct rtl8366_smi *smi, u32 vid,
1016                                 struct rtl8366_vlan_4k *vlan4k)
1017 {
1018         u32 data[RTL8367B_TA_VLAN_NUM_WORDS];
1019         int err;
1020         int i;
1021
1022         memset(vlan4k, '\0', sizeof(struct rtl8366_vlan_4k));
1023
1024         if (vid >= RTL8367B_NUM_VIDS)
1025                 return -EINVAL;
1026
1027         /* write VID */
1028         REG_WR(smi, RTL8367B_TA_ADDR_REG, vid);
1029
1030         /* write table access control word */
1031         REG_WR(smi, RTL8367B_TA_CTRL_REG, RTL8367B_TA_CTRL_CVLAN_READ);
1032
1033         for (i = 0; i < ARRAY_SIZE(data); i++)
1034                 REG_RD(smi, RTL8367B_TA_RDDATA_REG(i), &data[i]);
1035
1036         vlan4k->vid = vid;
1037         vlan4k->member = (data[0] >> RTL8367B_TA_VLAN0_MEMBER_SHIFT) &
1038                          RTL8367B_TA_VLAN0_MEMBER_MASK;
1039         vlan4k->untag = (data[0] >> RTL8367B_TA_VLAN0_UNTAG_SHIFT) &
1040                         RTL8367B_TA_VLAN0_UNTAG_MASK;
1041         vlan4k->fid = (data[1] >> RTL8367B_TA_VLAN1_FID_SHIFT) &
1042                       RTL8367B_TA_VLAN1_FID_MASK;
1043
1044         return 0;
1045 }
1046
1047 static int rtl8367b_set_vlan_4k(struct rtl8366_smi *smi,
1048                                 const struct rtl8366_vlan_4k *vlan4k)
1049 {
1050         u32 data[RTL8367B_TA_VLAN_NUM_WORDS];
1051         int err;
1052         int i;
1053
1054         if (vlan4k->vid >= RTL8367B_NUM_VIDS ||
1055             vlan4k->member > RTL8367B_TA_VLAN0_MEMBER_MASK ||
1056             vlan4k->untag > RTL8367B_UNTAG_MASK ||
1057             vlan4k->fid > RTL8367B_FIDMAX)
1058                 return -EINVAL;
1059
1060         memset(data, 0, sizeof(data));
1061
1062         data[0] = (vlan4k->member & RTL8367B_TA_VLAN0_MEMBER_MASK) <<
1063                   RTL8367B_TA_VLAN0_MEMBER_SHIFT;
1064         data[0] |= (vlan4k->untag & RTL8367B_TA_VLAN0_UNTAG_MASK) <<
1065                    RTL8367B_TA_VLAN0_UNTAG_SHIFT;
1066         data[1] = (vlan4k->fid & RTL8367B_TA_VLAN1_FID_MASK) <<
1067                   RTL8367B_TA_VLAN1_FID_SHIFT;
1068
1069         for (i = 0; i < ARRAY_SIZE(data); i++)
1070                 REG_WR(smi, RTL8367B_TA_WRDATA_REG(i), data[i]);
1071
1072         /* write VID */
1073         REG_WR(smi, RTL8367B_TA_ADDR_REG,
1074                vlan4k->vid & RTL8367B_TA_VLAN_VID_MASK);
1075
1076         /* write table access control word */
1077         REG_WR(smi, RTL8367B_TA_CTRL_REG, RTL8367B_TA_CTRL_CVLAN_WRITE);
1078
1079         return 0;
1080 }
1081
1082 static int rtl8367b_get_vlan_mc(struct rtl8366_smi *smi, u32 index,
1083                                 struct rtl8366_vlan_mc *vlanmc)
1084 {
1085         u32 data[RTL8367B_VLAN_MC_NUM_WORDS];
1086         int err;
1087         int i;
1088
1089         memset(vlanmc, '\0', sizeof(struct rtl8366_vlan_mc));
1090
1091         if (index >= RTL8367B_NUM_VLANS)
1092                 return -EINVAL;
1093
1094         for (i = 0; i < ARRAY_SIZE(data); i++)
1095                 REG_RD(smi, RTL8367B_VLAN_MC_BASE(index) + i, &data[i]);
1096
1097         vlanmc->member = (data[0] >> RTL8367B_VLAN_MC0_MEMBER_SHIFT) &
1098                          RTL8367B_VLAN_MC0_MEMBER_MASK;
1099         vlanmc->fid = (data[1] >> RTL8367B_VLAN_MC1_FID_SHIFT) &
1100                       RTL8367B_VLAN_MC1_FID_MASK;
1101         vlanmc->vid = (data[3] >> RTL8367B_VLAN_MC3_EVID_SHIFT) &
1102                       RTL8367B_VLAN_MC3_EVID_MASK;
1103
1104         return 0;
1105 }
1106
1107 static int rtl8367b_set_vlan_mc(struct rtl8366_smi *smi, u32 index,
1108                                 const struct rtl8366_vlan_mc *vlanmc)
1109 {
1110         u32 data[RTL8367B_VLAN_MC_NUM_WORDS];
1111         int err;
1112         int i;
1113
1114         if (index >= RTL8367B_NUM_VLANS ||
1115             vlanmc->vid >= RTL8367B_NUM_VIDS ||
1116             vlanmc->priority > RTL8367B_PRIORITYMAX ||
1117             vlanmc->member > RTL8367B_VLAN_MC0_MEMBER_MASK ||
1118             vlanmc->untag > RTL8367B_UNTAG_MASK ||
1119             vlanmc->fid > RTL8367B_FIDMAX)
1120                 return -EINVAL;
1121
1122         data[0] = (vlanmc->member & RTL8367B_VLAN_MC0_MEMBER_MASK) <<
1123                   RTL8367B_VLAN_MC0_MEMBER_SHIFT;
1124         data[1] = (vlanmc->fid & RTL8367B_VLAN_MC1_FID_MASK) <<
1125                   RTL8367B_VLAN_MC1_FID_SHIFT;
1126         data[2] = 0;
1127         data[3] = (vlanmc->vid & RTL8367B_VLAN_MC3_EVID_MASK) <<
1128                    RTL8367B_VLAN_MC3_EVID_SHIFT;
1129
1130         for (i = 0; i < ARRAY_SIZE(data); i++)
1131                 REG_WR(smi, RTL8367B_VLAN_MC_BASE(index) + i, data[i]);
1132
1133         return 0;
1134 }
1135
1136 static int rtl8367b_get_mc_index(struct rtl8366_smi *smi, int port, int *val)
1137 {
1138         u32 data;
1139         int err;
1140
1141         if (port >= RTL8367B_NUM_PORTS)
1142                 return -EINVAL;
1143
1144         REG_RD(smi, RTL8367B_VLAN_PVID_CTRL_REG(port), &data);
1145
1146         *val = (data >> RTL8367B_VLAN_PVID_CTRL_SHIFT(port)) &
1147                RTL8367B_VLAN_PVID_CTRL_MASK;
1148
1149         return 0;
1150 }
1151
1152 static int rtl8367b_set_mc_index(struct rtl8366_smi *smi, int port, int index)
1153 {
1154         if (port >= RTL8367B_NUM_PORTS || index >= RTL8367B_NUM_VLANS)
1155                 return -EINVAL;
1156
1157         return rtl8366_smi_rmwr(smi, RTL8367B_VLAN_PVID_CTRL_REG(port),
1158                                 RTL8367B_VLAN_PVID_CTRL_MASK <<
1159                                         RTL8367B_VLAN_PVID_CTRL_SHIFT(port),
1160                                 (index & RTL8367B_VLAN_PVID_CTRL_MASK) <<
1161                                         RTL8367B_VLAN_PVID_CTRL_SHIFT(port));
1162 }
1163
1164 static int rtl8367b_enable_vlan(struct rtl8366_smi *smi, int enable)
1165 {
1166         return rtl8366_smi_rmwr(smi, RTL8367B_VLAN_CTRL_REG,
1167                                 RTL8367B_VLAN_CTRL_ENABLE,
1168                                 (enable) ? RTL8367B_VLAN_CTRL_ENABLE : 0);
1169 }
1170
1171 static int rtl8367b_enable_vlan4k(struct rtl8366_smi *smi, int enable)
1172 {
1173         return 0;
1174 }
1175
1176 static int rtl8367b_is_vlan_valid(struct rtl8366_smi *smi, unsigned vlan)
1177 {
1178         unsigned max = RTL8367B_NUM_VLANS;
1179
1180         if (smi->vlan4k_enabled)
1181                 max = RTL8367B_NUM_VIDS - 1;
1182
1183         if (vlan == 0 || vlan >= max)
1184                 return 0;
1185
1186         return 1;
1187 }
1188
1189 static int rtl8367b_enable_port(struct rtl8366_smi *smi, int port, int enable)
1190 {
1191         int err;
1192
1193         REG_WR(smi, RTL8367B_PORT_ISOLATION_REG(port),
1194                (enable) ? RTL8367B_PORTS_ALL : 0);
1195
1196         return 0;
1197 }
1198
1199 static int rtl8367b_sw_reset_mibs(struct switch_dev *dev,
1200                                   const struct switch_attr *attr,
1201                                   struct switch_val *val)
1202 {
1203         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1204
1205         return rtl8366_smi_rmwr(smi, RTL8367B_MIB_CTRL0_REG(0), 0,
1206                                 RTL8367B_MIB_CTRL0_GLOBAL_RESET_MASK);
1207 }
1208
1209 static int rtl8367b_sw_get_port_link(struct switch_dev *dev,
1210                                     int port,
1211                                     struct switch_port_link *link)
1212 {
1213         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1214         u32 data = 0;
1215         u32 speed;
1216
1217         if (port >= RTL8367B_NUM_PORTS)
1218                 return -EINVAL;
1219
1220         rtl8366_smi_read_reg(smi, RTL8367B_PORT_STATUS_REG(port), &data);
1221
1222         link->link = !!(data & RTL8367B_PORT_STATUS_LINK);
1223         if (!link->link)
1224                 return 0;
1225
1226         link->duplex = !!(data & RTL8367B_PORT_STATUS_DUPLEX);
1227         link->rx_flow = !!(data & RTL8367B_PORT_STATUS_RXPAUSE);
1228         link->tx_flow = !!(data & RTL8367B_PORT_STATUS_TXPAUSE);
1229         link->aneg = !!(data & RTL8367B_PORT_STATUS_NWAY);
1230
1231         speed = (data & RTL8367B_PORT_STATUS_SPEED_MASK);
1232         switch (speed) {
1233         case 0:
1234                 link->speed = SWITCH_PORT_SPEED_10;
1235                 break;
1236         case 1:
1237                 link->speed = SWITCH_PORT_SPEED_100;
1238                 break;
1239         case 2:
1240                 link->speed = SWITCH_PORT_SPEED_1000;
1241                 break;
1242         default:
1243                 link->speed = SWITCH_PORT_SPEED_UNKNOWN;
1244                 break;
1245         }
1246
1247         return 0;
1248 }
1249
1250 static int rtl8367b_sw_get_max_length(struct switch_dev *dev,
1251                                      const struct switch_attr *attr,
1252                                      struct switch_val *val)
1253 {
1254         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1255         u32 data;
1256
1257         rtl8366_smi_read_reg(smi, RTL8367B_SWC0_REG, &data);
1258         val->value.i = (data & RTL8367B_SWC0_MAX_LENGTH_MASK) >>
1259                         RTL8367B_SWC0_MAX_LENGTH_SHIFT;
1260
1261         return 0;
1262 }
1263
1264 static int rtl8367b_sw_set_max_length(struct switch_dev *dev,
1265                                      const struct switch_attr *attr,
1266                                      struct switch_val *val)
1267 {
1268         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1269         u32 max_len;
1270
1271         switch (val->value.i) {
1272         case 0:
1273                 max_len = RTL8367B_SWC0_MAX_LENGTH_1522;
1274                 break;
1275         case 1:
1276                 max_len = RTL8367B_SWC0_MAX_LENGTH_1536;
1277                 break;
1278         case 2:
1279                 max_len = RTL8367B_SWC0_MAX_LENGTH_1552;
1280                 break;
1281         case 3:
1282                 max_len = RTL8367B_SWC0_MAX_LENGTH_16000;
1283                 break;
1284         default:
1285                 return -EINVAL;
1286         }
1287
1288         return rtl8366_smi_rmwr(smi, RTL8367B_SWC0_REG,
1289                                 RTL8367B_SWC0_MAX_LENGTH_MASK, max_len);
1290 }
1291
1292
1293 static int rtl8367b_sw_reset_port_mibs(struct switch_dev *dev,
1294                                        const struct switch_attr *attr,
1295                                        struct switch_val *val)
1296 {
1297         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1298         int port;
1299
1300         port = val->port_vlan;
1301         if (port >= RTL8367B_NUM_PORTS)
1302                 return -EINVAL;
1303
1304         return rtl8366_smi_rmwr(smi, RTL8367B_MIB_CTRL0_REG(port / 8), 0,
1305                                 RTL8367B_MIB_CTRL0_PORT_RESET_MASK(port % 8));
1306 }
1307
1308 static int rtl8367b_sw_get_port_stats(struct switch_dev *dev, int port,
1309                                         struct switch_port_stats *stats)
1310 {
1311         return (rtl8366_sw_get_port_stats(dev, port, stats,
1312                                 RTL8367B_MIB_TXB_ID, RTL8367B_MIB_RXB_ID));
1313 }
1314
1315 static struct switch_attr rtl8367b_globals[] = {
1316         {
1317                 .type = SWITCH_TYPE_INT,
1318                 .name = "enable_vlan",
1319                 .description = "Enable VLAN mode",
1320                 .set = rtl8366_sw_set_vlan_enable,
1321                 .get = rtl8366_sw_get_vlan_enable,
1322                 .max = 1,
1323                 .ofs = 1
1324         }, {
1325                 .type = SWITCH_TYPE_INT,
1326                 .name = "enable_vlan4k",
1327                 .description = "Enable VLAN 4K mode",
1328                 .set = rtl8366_sw_set_vlan_enable,
1329                 .get = rtl8366_sw_get_vlan_enable,
1330                 .max = 1,
1331                 .ofs = 2
1332         }, {
1333                 .type = SWITCH_TYPE_NOVAL,
1334                 .name = "reset_mibs",
1335                 .description = "Reset all MIB counters",
1336                 .set = rtl8367b_sw_reset_mibs,
1337         }, {
1338                 .type = SWITCH_TYPE_INT,
1339                 .name = "max_length",
1340                 .description = "Get/Set the maximum length of valid packets"
1341                                "(0:1522, 1:1536, 2:1552, 3:16000)",
1342                 .set = rtl8367b_sw_set_max_length,
1343                 .get = rtl8367b_sw_get_max_length,
1344                 .max = 3,
1345         }
1346 };
1347
1348 static struct switch_attr rtl8367b_port[] = {
1349         {
1350                 .type = SWITCH_TYPE_NOVAL,
1351                 .name = "reset_mib",
1352                 .description = "Reset single port MIB counters",
1353                 .set = rtl8367b_sw_reset_port_mibs,
1354         }, {
1355                 .type = SWITCH_TYPE_STRING,
1356                 .name = "mib",
1357                 .description = "Get MIB counters for port",
1358                 .max = 33,
1359                 .set = NULL,
1360                 .get = rtl8366_sw_get_port_mib,
1361         },
1362 };
1363
1364 static struct switch_attr rtl8367b_vlan[] = {
1365         {
1366                 .type = SWITCH_TYPE_STRING,
1367                 .name = "info",
1368                 .description = "Get vlan information",
1369                 .max = 1,
1370                 .set = NULL,
1371                 .get = rtl8366_sw_get_vlan_info,
1372         },
1373 };
1374
1375 static const struct switch_dev_ops rtl8367b_sw_ops = {
1376         .attr_global = {
1377                 .attr = rtl8367b_globals,
1378                 .n_attr = ARRAY_SIZE(rtl8367b_globals),
1379         },
1380         .attr_port = {
1381                 .attr = rtl8367b_port,
1382                 .n_attr = ARRAY_SIZE(rtl8367b_port),
1383         },
1384         .attr_vlan = {
1385                 .attr = rtl8367b_vlan,
1386                 .n_attr = ARRAY_SIZE(rtl8367b_vlan),
1387         },
1388
1389         .get_vlan_ports = rtl8366_sw_get_vlan_ports,
1390         .set_vlan_ports = rtl8366_sw_set_vlan_ports,
1391         .get_port_pvid = rtl8366_sw_get_port_pvid,
1392         .set_port_pvid = rtl8366_sw_set_port_pvid,
1393         .reset_switch = rtl8366_sw_reset_switch,
1394         .get_port_link = rtl8367b_sw_get_port_link,
1395         .get_port_stats = rtl8367b_sw_get_port_stats,
1396 };
1397
1398 static int rtl8367b_switch_init(struct rtl8366_smi *smi)
1399 {
1400         struct switch_dev *dev = &smi->sw_dev;
1401         int err;
1402
1403         dev->name = "RTL8367B";
1404         dev->cpu_port = RTL8367B_CPU_PORT_NUM;
1405         dev->ports = RTL8367B_NUM_PORTS;
1406         dev->vlans = RTL8367B_NUM_VIDS;
1407         dev->ops = &rtl8367b_sw_ops;
1408         dev->alias = dev_name(smi->parent);
1409
1410         err = register_switch(dev, NULL);
1411         if (err)
1412                 dev_err(smi->parent, "switch registration failed\n");
1413
1414         return err;
1415 }
1416
1417 static void rtl8367b_switch_cleanup(struct rtl8366_smi *smi)
1418 {
1419         unregister_switch(&smi->sw_dev);
1420 }
1421
1422 static int rtl8367b_mii_read(struct mii_bus *bus, int addr, int reg)
1423 {
1424         struct rtl8366_smi *smi = bus->priv;
1425         u32 val = 0;
1426         int err;
1427
1428         err = rtl8367b_read_phy_reg(smi, addr, reg, &val);
1429         if (err)
1430                 return 0xffff;
1431
1432         return val;
1433 }
1434
1435 static int rtl8367b_mii_write(struct mii_bus *bus, int addr, int reg, u16 val)
1436 {
1437         struct rtl8366_smi *smi = bus->priv;
1438         u32 t;
1439         int err;
1440
1441         err = rtl8367b_write_phy_reg(smi, addr, reg, val);
1442         if (err)
1443                 return err;
1444
1445         /* flush write */
1446         (void) rtl8367b_read_phy_reg(smi, addr, reg, &t);
1447
1448         return err;
1449 }
1450
1451 static int rtl8367b_detect(struct rtl8366_smi *smi)
1452 {
1453         const char *chip_name;
1454         u32 chip_num;
1455         u32 chip_ver;
1456         u32 chip_mode;
1457         int ret;
1458
1459         /* TODO: improve chip detection */
1460         rtl8366_smi_write_reg(smi, RTL8367B_RTL_MAGIC_ID_REG,
1461                               RTL8367B_RTL_MAGIC_ID_VAL);
1462
1463         ret = rtl8366_smi_read_reg(smi, RTL8367B_CHIP_NUMBER_REG, &chip_num);
1464         if (ret) {
1465                 dev_err(smi->parent, "unable to read %s register\n",
1466                         "chip number");
1467                 return ret;
1468         }
1469
1470         ret = rtl8366_smi_read_reg(smi, RTL8367B_CHIP_VER_REG, &chip_ver);
1471         if (ret) {
1472                 dev_err(smi->parent, "unable to read %s register\n",
1473                         "chip version");
1474                 return ret;
1475         }
1476
1477         ret = rtl8366_smi_read_reg(smi, RTL8367B_CHIP_MODE_REG, &chip_mode);
1478         if (ret) {
1479                 dev_err(smi->parent, "unable to read %s register\n",
1480                         "chip mode");
1481                 return ret;
1482         }
1483
1484         switch (chip_ver) {
1485         case 0x1000:
1486                 chip_name = "8367RB";
1487                 break;
1488         case 0x1010:
1489                 chip_name = "8367R-VB";
1490                 break;
1491         default:
1492                 dev_err(smi->parent,
1493                         "unknown chip num:%04x ver:%04x, mode:%04x\n",
1494                         chip_num, chip_ver, chip_mode);
1495                 return -ENODEV;
1496         }
1497
1498         dev_info(smi->parent, "RTL%s chip found\n", chip_name);
1499
1500         return 0;
1501 }
1502
1503 static struct rtl8366_smi_ops rtl8367b_smi_ops = {
1504         .detect         = rtl8367b_detect,
1505         .reset_chip     = rtl8367b_reset_chip,
1506         .setup          = rtl8367b_setup,
1507
1508         .mii_read       = rtl8367b_mii_read,
1509         .mii_write      = rtl8367b_mii_write,
1510
1511         .get_vlan_mc    = rtl8367b_get_vlan_mc,
1512         .set_vlan_mc    = rtl8367b_set_vlan_mc,
1513         .get_vlan_4k    = rtl8367b_get_vlan_4k,
1514         .set_vlan_4k    = rtl8367b_set_vlan_4k,
1515         .get_mc_index   = rtl8367b_get_mc_index,
1516         .set_mc_index   = rtl8367b_set_mc_index,
1517         .get_mib_counter = rtl8367b_get_mib_counter,
1518         .is_vlan_valid  = rtl8367b_is_vlan_valid,
1519         .enable_vlan    = rtl8367b_enable_vlan,
1520         .enable_vlan4k  = rtl8367b_enable_vlan4k,
1521         .enable_port    = rtl8367b_enable_port,
1522 };
1523
1524 static int  rtl8367b_probe(struct platform_device *pdev)
1525 {
1526         struct rtl8366_smi *smi;
1527         int err;
1528
1529         smi = rtl8366_smi_probe(pdev);
1530         if (!smi)
1531                 return -ENODEV;
1532
1533         smi->clk_delay = 1500;
1534         smi->cmd_read = 0xb9;
1535         smi->cmd_write = 0xb8;
1536         smi->ops = &rtl8367b_smi_ops;
1537         smi->cpu_port = RTL8367B_CPU_PORT_NUM;
1538         smi->num_ports = RTL8367B_NUM_PORTS;
1539         smi->num_vlan_mc = RTL8367B_NUM_VLANS;
1540         smi->mib_counters = rtl8367b_mib_counters;
1541         smi->num_mib_counters = ARRAY_SIZE(rtl8367b_mib_counters);
1542
1543         err = rtl8366_smi_init(smi);
1544         if (err)
1545                 goto err_free_smi;
1546
1547         platform_set_drvdata(pdev, smi);
1548
1549         err = rtl8367b_switch_init(smi);
1550         if (err)
1551                 goto err_clear_drvdata;
1552
1553         return 0;
1554
1555  err_clear_drvdata:
1556         platform_set_drvdata(pdev, NULL);
1557         rtl8366_smi_cleanup(smi);
1558  err_free_smi:
1559         kfree(smi);
1560         return err;
1561 }
1562
1563 static int rtl8367b_remove(struct platform_device *pdev)
1564 {
1565         struct rtl8366_smi *smi = platform_get_drvdata(pdev);
1566
1567         if (smi) {
1568                 rtl8367b_switch_cleanup(smi);
1569                 platform_set_drvdata(pdev, NULL);
1570                 rtl8366_smi_cleanup(smi);
1571                 kfree(smi);
1572         }
1573
1574         return 0;
1575 }
1576
1577 static void rtl8367b_shutdown(struct platform_device *pdev)
1578 {
1579         struct rtl8366_smi *smi = platform_get_drvdata(pdev);
1580
1581         if (smi)
1582                 rtl8367b_reset_chip(smi);
1583 }
1584
1585 #ifdef CONFIG_OF
1586 static const struct of_device_id rtl8367b_match[] = {
1587         { .compatible = "realtek,rtl8367b" },
1588         { .compatible = "rtl8367b" },
1589         {},
1590 };
1591 MODULE_DEVICE_TABLE(of, rtl8367b_match);
1592 #endif
1593
1594 static struct platform_driver rtl8367b_driver = {
1595         .driver = {
1596                 .name           = RTL8367B_DRIVER_NAME,
1597                 .owner          = THIS_MODULE,
1598 #ifdef CONFIG_OF
1599                 .of_match_table = of_match_ptr(rtl8367b_match),
1600 #endif
1601         },
1602         .probe          = rtl8367b_probe,
1603         .remove         = rtl8367b_remove,
1604         .shutdown       = rtl8367b_shutdown,
1605 };
1606
1607 module_platform_driver(rtl8367b_driver);
1608
1609 MODULE_DESCRIPTION("Realtek RTL8367B ethernet switch driver");
1610 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
1611 MODULE_LICENSE("GPL v2");
1612 MODULE_ALIAS("platform:" RTL8367B_DRIVER_NAME);
1613