target/linux/generic/files/drivers/net/phy/rtl8366s.c

   1 /*
   2  * Platform driver for the Realtek RTL8366S ethernet switch
   3  *
   4  * Copyright (C) 2009-2010 Gabor Juhos <juhosg@openwrt.org>
   5  * Copyright (C) 2010 Antti Seppälä <a.seppala@gmail.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms of the GNU General Public License version 2 as published
   9  * by the Free Software Foundation.
  10  */
  11
  12 #include <linux/kernel.h>
  13 #include <linux/module.h>
  14 #include <linux/init.h>
  15 #include <linux/of.h>
  16 #include <linux/of_platform.h>
  17 #include <linux/delay.h>
  18 #include <linux/skbuff.h>
  19 #include <linux/rtl8366.h>
  20
  21 #include "rtl8366_smi.h"
  22
  23 #define RTL8366S_DRIVER_DESC    "Realtek RTL8366S ethernet switch driver"
  24 #define RTL8366S_DRIVER_VER     "0.2.2"
  25
  26 #define RTL8366S_PHY_NO_MAX     4
  27 #define RTL8366S_PHY_PAGE_MAX   7
  28 #define RTL8366S_PHY_ADDR_MAX   31
  29
  30 /* Switch Global Configuration register */
  31 #define RTL8366S_SGCR                           0x0000
  32 #define RTL8366S_SGCR_EN_BC_STORM_CTRL          BIT(0)
  33 #define RTL8366S_SGCR_MAX_LENGTH(_x)            (_x << 4)
  34 #define RTL8366S_SGCR_MAX_LENGTH_MASK           RTL8366S_SGCR_MAX_LENGTH(0x3)
  35 #define RTL8366S_SGCR_MAX_LENGTH_1522           RTL8366S_SGCR_MAX_LENGTH(0x0)
  36 #define RTL8366S_SGCR_MAX_LENGTH_1536           RTL8366S_SGCR_MAX_LENGTH(0x1)
  37 #define RTL8366S_SGCR_MAX_LENGTH_1552           RTL8366S_SGCR_MAX_LENGTH(0x2)
  38 #define RTL8366S_SGCR_MAX_LENGTH_16000          RTL8366S_SGCR_MAX_LENGTH(0x3)
  39 #define RTL8366S_SGCR_EN_VLAN                   BIT(13)
  40
  41 /* Port Enable Control register */
  42 #define RTL8366S_PECR                           0x0001
  43
  44 /* Switch Security Control registers */
  45 #define RTL8366S_SSCR0                          0x0002
  46 #define RTL8366S_SSCR1                          0x0003
  47 #define RTL8366S_SSCR2                          0x0004
  48 #define RTL8366S_SSCR2_DROP_UNKNOWN_DA          BIT(0)
  49
  50 #define RTL8366S_RESET_CTRL_REG                 0x0100
  51 #define RTL8366S_CHIP_CTRL_RESET_HW             1
  52 #define RTL8366S_CHIP_CTRL_RESET_SW             (1 << 1)
  53
  54 #define RTL8366S_CHIP_VERSION_CTRL_REG          0x0104
  55 #define RTL8366S_CHIP_VERSION_MASK              0xf
  56 #define RTL8366S_CHIP_ID_REG                    0x0105
  57 #define RTL8366S_CHIP_ID_8366                   0x8366
  58
  59 /* PHY registers control */
  60 #define RTL8366S_PHY_ACCESS_CTRL_REG            0x8028
  61 #define RTL8366S_PHY_ACCESS_DATA_REG            0x8029
  62
  63 #define RTL8366S_PHY_CTRL_READ                  1
  64 #define RTL8366S_PHY_CTRL_WRITE                 0
  65
  66 #define RTL8366S_PHY_REG_MASK                   0x1f
  67 #define RTL8366S_PHY_PAGE_OFFSET                5
  68 #define RTL8366S_PHY_PAGE_MASK                  (0x7 << 5)
  69 #define RTL8366S_PHY_NO_OFFSET                  9
  70 #define RTL8366S_PHY_NO_MASK                    (0x1f << 9)
  71
  72 /* LED control registers */
  73 #define RTL8366S_LED_BLINKRATE_REG              0x0420
  74 #define RTL8366S_LED_BLINKRATE_BIT              0
  75 #define RTL8366S_LED_BLINKRATE_MASK             0x0007
  76
  77 #define RTL8366S_LED_CTRL_REG                   0x0421
  78 #define RTL8366S_LED_0_1_CTRL_REG               0x0422
  79 #define RTL8366S_LED_2_3_CTRL_REG               0x0423
  80
  81 #define RTL8366S_MIB_COUNT                      33
  82 #define RTL8366S_GLOBAL_MIB_COUNT               1
  83 #define RTL8366S_MIB_COUNTER_PORT_OFFSET        0x0040
  84 #define RTL8366S_MIB_COUNTER_BASE               0x1000
  85 #define RTL8366S_MIB_COUNTER_PORT_OFFSET2       0x0008
  86 #define RTL8366S_MIB_COUNTER_BASE2              0x1180
  87 #define RTL8366S_MIB_CTRL_REG                   0x11F0
  88 #define RTL8366S_MIB_CTRL_USER_MASK             0x01FF
  89 #define RTL8366S_MIB_CTRL_BUSY_MASK             0x0001
  90 #define RTL8366S_MIB_CTRL_RESET_MASK            0x0002
  91
  92 #define RTL8366S_MIB_CTRL_GLOBAL_RESET_MASK     0x0004
  93 #define RTL8366S_MIB_CTRL_PORT_RESET_BIT        0x0003
  94 #define RTL8366S_MIB_CTRL_PORT_RESET_MASK       0x01FC
  95
  96
  97 #define RTL8366S_PORT_VLAN_CTRL_BASE            0x0058
  98 #define RTL8366S_PORT_VLAN_CTRL_REG(_p)  \
  99                 (RTL8366S_PORT_VLAN_CTRL_BASE + (_p) / 4)
 100 #define RTL8366S_PORT_VLAN_CTRL_MASK            0xf
 101 #define RTL8366S_PORT_VLAN_CTRL_SHIFT(_p)       (4 * ((_p) % 4))
 102
 103
 104 #define RTL8366S_VLAN_TABLE_READ_BASE           0x018B
 105 #define RTL8366S_VLAN_TABLE_WRITE_BASE          0x0185
 106
 107 #define RTL8366S_VLAN_TB_CTRL_REG               0x010F
 108
 109 #define RTL8366S_TABLE_ACCESS_CTRL_REG          0x0180
 110 #define RTL8366S_TABLE_VLAN_READ_CTRL           0x0E01
 111 #define RTL8366S_TABLE_VLAN_WRITE_CTRL          0x0F01
 112
 113 #define RTL8366S_VLAN_MC_BASE(_x)               (0x0016 + (_x) * 2)
 114
 115 #define RTL8366S_VLAN_MEMBERINGRESS_REG         0x0379
 116
 117 #define RTL8366S_PORT_LINK_STATUS_BASE          0x0060
 118 #define RTL8366S_PORT_STATUS_SPEED_MASK         0x0003
 119 #define RTL8366S_PORT_STATUS_DUPLEX_MASK        0x0004
 120 #define RTL8366S_PORT_STATUS_LINK_MASK          0x0010
 121 #define RTL8366S_PORT_STATUS_TXPAUSE_MASK       0x0020
 122 #define RTL8366S_PORT_STATUS_RXPAUSE_MASK       0x0040
 123 #define RTL8366S_PORT_STATUS_AN_MASK            0x0080
 124
 125
 126 #define RTL8366S_PORT_NUM_CPU           5
 127 #define RTL8366S_NUM_PORTS              6
 128 #define RTL8366S_NUM_VLANS              16
 129 #define RTL8366S_NUM_LEDGROUPS          4
 130 #define RTL8366S_NUM_VIDS               4096
 131 #define RTL8366S_PRIORITYMAX            7
 132 #define RTL8366S_FIDMAX                 7
 133
 134
 135 #define RTL8366S_PORT_1                 (1 << 0) /* In userspace port 0 */
 136 #define RTL8366S_PORT_2                 (1 << 1) /* In userspace port 1 */
 137 #define RTL8366S_PORT_3                 (1 << 2) /* In userspace port 2 */
 138 #define RTL8366S_PORT_4                 (1 << 3) /* In userspace port 3 */
 139
 140 #define RTL8366S_PORT_UNKNOWN           (1 << 4) /* No known connection */
 141 #define RTL8366S_PORT_CPU               (1 << 5) /* CPU port */
 142
 143 #define RTL8366S_PORT_ALL               (RTL8366S_PORT_1 |      \
 144                                          RTL8366S_PORT_2 |      \
 145                                          RTL8366S_PORT_3 |      \
 146                                          RTL8366S_PORT_4 |      \
 147                                          RTL8366S_PORT_UNKNOWN | \
 148                                          RTL8366S_PORT_CPU)
 149
 150 #define RTL8366S_PORT_ALL_BUT_CPU       (RTL8366S_PORT_1 |      \
 151                                          RTL8366S_PORT_2 |      \
 152                                          RTL8366S_PORT_3 |      \
 153                                          RTL8366S_PORT_4 |      \
 154                                          RTL8366S_PORT_UNKNOWN)
 155
 156 #define RTL8366S_PORT_ALL_EXTERNAL      (RTL8366S_PORT_1 |      \
 157                                          RTL8366S_PORT_2 |      \
 158                                          RTL8366S_PORT_3 |      \
 159                                          RTL8366S_PORT_4)
 160
 161 #define RTL8366S_PORT_ALL_INTERNAL      (RTL8366S_PORT_UNKNOWN | \
 162                                          RTL8366S_PORT_CPU)
 163
 164 #define RTL8366S_VLAN_VID_MASK          0xfff
 165 #define RTL8366S_VLAN_PRIORITY_SHIFT    12
 166 #define RTL8366S_VLAN_PRIORITY_MASK     0x7
 167 #define RTL8366S_VLAN_MEMBER_MASK       0x3f
 168 #define RTL8366S_VLAN_UNTAG_SHIFT       6
 169 #define RTL8366S_VLAN_UNTAG_MASK        0x3f
 170 #define RTL8366S_VLAN_FID_SHIFT         12
 171 #define RTL8366S_VLAN_FID_MASK          0x7
 172
 173 static struct rtl8366_mib_counter rtl8366s_mib_counters[] = {
 174         { 0,  0, 4, "IfInOctets"                                },
 175         { 0,  4, 4, "EtherStatsOctets"                          },
 176         { 0,  8, 2, "EtherStatsUnderSizePkts"                   },
 177         { 0, 10, 2, "EtherFragments"                            },
 178         { 0, 12, 2, "EtherStatsPkts64Octets"                    },
 179         { 0, 14, 2, "EtherStatsPkts65to127Octets"               },
 180         { 0, 16, 2, "EtherStatsPkts128to255Octets"              },
 181         { 0, 18, 2, "EtherStatsPkts256to511Octets"              },
 182         { 0, 20, 2, "EtherStatsPkts512to1023Octets"             },
 183         { 0, 22, 2, "EtherStatsPkts1024to1518Octets"            },
 184         { 0, 24, 2, "EtherOversizeStats"                        },
 185         { 0, 26, 2, "EtherStatsJabbers"                         },
 186         { 0, 28, 2, "IfInUcastPkts"                             },
 187         { 0, 30, 2, "EtherStatsMulticastPkts"                   },
 188         { 0, 32, 2, "EtherStatsBroadcastPkts"                   },
 189         { 0, 34, 2, "EtherStatsDropEvents"                      },
 190         { 0, 36, 2, "Dot3StatsFCSErrors"                        },
 191         { 0, 38, 2, "Dot3StatsSymbolErrors"                     },
 192         { 0, 40, 2, "Dot3InPauseFrames"                         },
 193         { 0, 42, 2, "Dot3ControlInUnknownOpcodes"               },
 194         { 0, 44, 4, "IfOutOctets"                               },
 195         { 0, 48, 2, "Dot3StatsSingleCollisionFrames"            },
 196         { 0, 50, 2, "Dot3StatMultipleCollisionFrames"           },
 197         { 0, 52, 2, "Dot3sDeferredTransmissions"                },
 198         { 0, 54, 2, "Dot3StatsLateCollisions"                   },
 199         { 0, 56, 2, "EtherStatsCollisions"                      },
 200         { 0, 58, 2, "Dot3StatsExcessiveCollisions"              },
 201         { 0, 60, 2, "Dot3OutPauseFrames"                        },
 202         { 0, 62, 2, "Dot1dBasePortDelayExceededDiscards"        },
 203
 204         /*
 205          * The following counters are accessible at a different
 206          * base address.
 207          */
 208         { 1,  0, 2, "Dot1dTpPortInDiscards"                     },
 209         { 1,  2, 2, "IfOutUcastPkts"                            },
 210         { 1,  4, 2, "IfOutMulticastPkts"                        },
 211         { 1,  6, 2, "IfOutBroadcastPkts"                        },
 212 };
 213
 214 #define REG_WR(_smi, _reg, _val)                                        \
 215         do {                                                            \
 216                 err = rtl8366_smi_write_reg(_smi, _reg, _val);          \
 217                 if (err)                                                \
 218                         return err;                                     \
 219         } while (0)
 220
 221 #define REG_RMW(_smi, _reg, _mask, _val)                                \
 222         do {                                                            \
 223                 err = rtl8366_smi_rmwr(_smi, _reg, _mask, _val);        \
 224                 if (err)                                                \
 225                         return err;                                     \
 226         } while (0)
 227
 228 static int rtl8366s_reset_chip(struct rtl8366_smi *smi)
 229 {
 230         int timeout = 10;
 231         u32 data;
 232
 233         rtl8366_smi_write_reg_noack(smi, RTL8366S_RESET_CTRL_REG,
 234                                     RTL8366S_CHIP_CTRL_RESET_HW);
 235         do {
 236                 msleep(1);
 237                 if (rtl8366_smi_read_reg(smi, RTL8366S_RESET_CTRL_REG, &data))
 238                         return -EIO;
 239
 240                 if (!(data & RTL8366S_CHIP_CTRL_RESET_HW))
 241                         break;
 242         } while (--timeout);
 243
 244         if (!timeout) {
 245                 printk("Timeout waiting for the switch to reset\n");
 246                 return -EIO;
 247         }
 248
 249         return 0;
 250 }
 251
 252 static int rtl8366s_setup(struct rtl8366_smi *smi)
 253 {
 254         struct rtl8366_platform_data *pdata;
 255         int err;
 256
 257         pdata = smi->parent->platform_data;
 258         if (pdata->num_initvals && pdata->initvals) {
 259                 unsigned i;
 260
 261                 dev_info(smi->parent, "applying initvals\n");
 262                 for (i = 0; i < pdata->num_initvals; i++)
 263                         REG_WR(smi, pdata->initvals[i].reg,
 264                                pdata->initvals[i].val);
 265         }
 266
 267         /* set maximum packet length to 1536 bytes */
 268         REG_RMW(smi, RTL8366S_SGCR, RTL8366S_SGCR_MAX_LENGTH_MASK,
 269                 RTL8366S_SGCR_MAX_LENGTH_1536);
 270
 271         /* enable learning for all ports */
 272         REG_WR(smi, RTL8366S_SSCR0, 0);
 273
 274         /* enable auto ageing for all ports */
 275         REG_WR(smi, RTL8366S_SSCR1, 0);
 276
 277         /*
 278          * discard VLAN tagged packets if the port is not a member of
 279          * the VLAN with which the packets is associated.
 280          */
 281         REG_WR(smi, RTL8366S_VLAN_MEMBERINGRESS_REG, RTL8366S_PORT_ALL);
 282
 283         /* don't drop packets whose DA has not been learned */
 284         REG_RMW(smi, RTL8366S_SSCR2, RTL8366S_SSCR2_DROP_UNKNOWN_DA, 0);
 285
 286         return 0;
 287 }
 288
 289 static int rtl8366s_read_phy_reg(struct rtl8366_smi *smi,
 290                                  u32 phy_no, u32 page, u32 addr, u32 *data)
 291 {
 292         u32 reg;
 293         int ret;
 294
 295         if (phy_no > RTL8366S_PHY_NO_MAX)
 296                 return -EINVAL;
 297
 298         if (page > RTL8366S_PHY_PAGE_MAX)
 299                 return -EINVAL;
 300
 301         if (addr > RTL8366S_PHY_ADDR_MAX)
 302                 return -EINVAL;
 303
 304         ret = rtl8366_smi_write_reg(smi, RTL8366S_PHY_ACCESS_CTRL_REG,
 305                                     RTL8366S_PHY_CTRL_READ);
 306         if (ret)
 307                 return ret;
 308
 309         reg = 0x8000 | (1 << (phy_no + RTL8366S_PHY_NO_OFFSET)) |
 310               ((page << RTL8366S_PHY_PAGE_OFFSET) & RTL8366S_PHY_PAGE_MASK) |
 311               (addr & RTL8366S_PHY_REG_MASK);
 312
 313         ret = rtl8366_smi_write_reg(smi, reg, 0);
 314         if (ret)
 315                 return ret;
 316
 317         ret = rtl8366_smi_read_reg(smi, RTL8366S_PHY_ACCESS_DATA_REG, data);
 318         if (ret)
 319                 return ret;
 320
 321         return 0;
 322 }
 323
 324 static int rtl8366s_write_phy_reg(struct rtl8366_smi *smi,
 325                                   u32 phy_no, u32 page, u32 addr, u32 data)
 326 {
 327         u32 reg;
 328         int ret;
 329
 330         if (phy_no > RTL8366S_PHY_NO_MAX)
 331                 return -EINVAL;
 332
 333         if (page > RTL8366S_PHY_PAGE_MAX)
 334                 return -EINVAL;
 335
 336         if (addr > RTL8366S_PHY_ADDR_MAX)
 337                 return -EINVAL;
 338
 339         ret = rtl8366_smi_write_reg(smi, RTL8366S_PHY_ACCESS_CTRL_REG,
 340                                     RTL8366S_PHY_CTRL_WRITE);
 341         if (ret)
 342                 return ret;
 343
 344         reg = 0x8000 | (1 << (phy_no + RTL8366S_PHY_NO_OFFSET)) |
 345               ((page << RTL8366S_PHY_PAGE_OFFSET) & RTL8366S_PHY_PAGE_MASK) |
 346               (addr & RTL8366S_PHY_REG_MASK);
 347
 348         ret = rtl8366_smi_write_reg(smi, reg, data);
 349         if (ret)
 350                 return ret;
 351
 352         return 0;
 353 }
 354
 355 static int rtl8366_get_mib_counter(struct rtl8366_smi *smi, int counter,
 356                                    int port, unsigned long long *val)
 357 {
 358         int i;
 359         int err;
 360         u32 addr, data;
 361         u64 mibvalue;
 362
 363         if (port > RTL8366S_NUM_PORTS || counter >= RTL8366S_MIB_COUNT)
 364                 return -EINVAL;
 365
 366         switch (rtl8366s_mib_counters[counter].base) {
 367         case 0:
 368                 addr = RTL8366S_MIB_COUNTER_BASE +
 369                        RTL8366S_MIB_COUNTER_PORT_OFFSET * port;
 370                 break;
 371
 372         case 1:
 373                 addr = RTL8366S_MIB_COUNTER_BASE2 +
 374                         RTL8366S_MIB_COUNTER_PORT_OFFSET2 * port;
 375                 break;
 376
 377         default:
 378                 return -EINVAL;
 379         }
 380
 381         addr += rtl8366s_mib_counters[counter].offset;
 382
 383         /*
 384          * Writing access counter address first
 385          * then ASIC will prepare 64bits counter wait for being retrived
 386          */
 387         data = 0; /* writing data will be discard by ASIC */
 388         err = rtl8366_smi_write_reg(smi, addr, data);
 389         if (err)
 390                 return err;
 391
 392         /* read MIB control register */
 393         err =  rtl8366_smi_read_reg(smi, RTL8366S_MIB_CTRL_REG, &data);
 394         if (err)
 395                 return err;
 396
 397         if (data & RTL8366S_MIB_CTRL_BUSY_MASK)
 398                 return -EBUSY;
 399
 400         if (data & RTL8366S_MIB_CTRL_RESET_MASK)
 401                 return -EIO;
 402
 403         mibvalue = 0;
 404         for (i = rtl8366s_mib_counters[counter].length; i > 0; i--) {
 405                 err = rtl8366_smi_read_reg(smi, addr + (i - 1), &data);
 406                 if (err)
 407                         return err;
 408
 409                 mibvalue = (mibvalue << 16) | (data & 0xFFFF);
 410         }
 411
 412         *val = mibvalue;
 413         return 0;
 414 }
 415
 416 static int rtl8366s_get_vlan_4k(struct rtl8366_smi *smi, u32 vid,
 417                                 struct rtl8366_vlan_4k *vlan4k)
 418 {
 419         u32 data[2];
 420         int err;
 421         int i;
 422
 423         memset(vlan4k, '\0', sizeof(struct rtl8366_vlan_4k));
 424
 425         if (vid >= RTL8366S_NUM_VIDS)
 426                 return -EINVAL;
 427
 428         /* write VID */
 429         err = rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TABLE_WRITE_BASE,
 430                                     vid & RTL8366S_VLAN_VID_MASK);
 431         if (err)
 432                 return err;
 433
 434         /* write table access control word */
 435         err = rtl8366_smi_write_reg(smi, RTL8366S_TABLE_ACCESS_CTRL_REG,
 436                                     RTL8366S_TABLE_VLAN_READ_CTRL);
 437         if (err)
 438                 return err;
 439
 440         for (i = 0; i < 2; i++) {
 441                 err = rtl8366_smi_read_reg(smi,
 442                                            RTL8366S_VLAN_TABLE_READ_BASE + i,
 443                                            &data[i]);
 444                 if (err)
 445                         return err;
 446         }
 447
 448         vlan4k->vid = vid;
 449         vlan4k->untag = (data[1] >> RTL8366S_VLAN_UNTAG_SHIFT) &
 450                         RTL8366S_VLAN_UNTAG_MASK;
 451         vlan4k->member = data[1] & RTL8366S_VLAN_MEMBER_MASK;
 452         vlan4k->fid = (data[1] >> RTL8366S_VLAN_FID_SHIFT) &
 453                         RTL8366S_VLAN_FID_MASK;
 454
 455         return 0;
 456 }
 457
 458 static int rtl8366s_set_vlan_4k(struct rtl8366_smi *smi,
 459                                 const struct rtl8366_vlan_4k *vlan4k)
 460 {
 461         u32 data[2];
 462         int err;
 463         int i;
 464
 465         if (vlan4k->vid >= RTL8366S_NUM_VIDS ||
 466             vlan4k->member > RTL8366S_VLAN_MEMBER_MASK ||
 467             vlan4k->untag > RTL8366S_VLAN_UNTAG_MASK ||
 468             vlan4k->fid > RTL8366S_FIDMAX)
 469                 return -EINVAL;
 470
 471         data[0] = vlan4k->vid & RTL8366S_VLAN_VID_MASK;
 472         data[1] = (vlan4k->member & RTL8366S_VLAN_MEMBER_MASK) |
 473                   ((vlan4k->untag & RTL8366S_VLAN_UNTAG_MASK) <<
 474                         RTL8366S_VLAN_UNTAG_SHIFT) |
 475                   ((vlan4k->fid & RTL8366S_VLAN_FID_MASK) <<
 476                         RTL8366S_VLAN_FID_SHIFT);
 477
 478         for (i = 0; i < 2; i++) {
 479                 err = rtl8366_smi_write_reg(smi,
 480                                             RTL8366S_VLAN_TABLE_WRITE_BASE + i,
 481                                             data[i]);
 482                 if (err)
 483                         return err;
 484         }
 485
 486         /* write table access control word */
 487         err = rtl8366_smi_write_reg(smi, RTL8366S_TABLE_ACCESS_CTRL_REG,
 488                                     RTL8366S_TABLE_VLAN_WRITE_CTRL);
 489
 490         return err;
 491 }
 492
 493 static int rtl8366s_get_vlan_mc(struct rtl8366_smi *smi, u32 index,
 494                                 struct rtl8366_vlan_mc *vlanmc)
 495 {
 496         u32 data[2];
 497         int err;
 498         int i;
 499
 500         memset(vlanmc, '\0', sizeof(struct rtl8366_vlan_mc));
 501
 502         if (index >= RTL8366S_NUM_VLANS)
 503                 return -EINVAL;
 504
 505         for (i = 0; i < 2; i++) {
 506                 err = rtl8366_smi_read_reg(smi,
 507                                            RTL8366S_VLAN_MC_BASE(index) + i,
 508                                            &data[i]);
 509                 if (err)
 510                         return err;
 511         }
 512
 513         vlanmc->vid = data[0] & RTL8366S_VLAN_VID_MASK;
 514         vlanmc->priority = (data[0] >> RTL8366S_VLAN_PRIORITY_SHIFT) &
 515                            RTL8366S_VLAN_PRIORITY_MASK;
 516         vlanmc->untag = (data[1] >> RTL8366S_VLAN_UNTAG_SHIFT) &
 517                         RTL8366S_VLAN_UNTAG_MASK;
 518         vlanmc->member = data[1] & RTL8366S_VLAN_MEMBER_MASK;
 519         vlanmc->fid = (data[1] >> RTL8366S_VLAN_FID_SHIFT) &
 520                       RTL8366S_VLAN_FID_MASK;
 521
 522         return 0;
 523 }
 524
 525 static int rtl8366s_set_vlan_mc(struct rtl8366_smi *smi, u32 index,
 526                                 const struct rtl8366_vlan_mc *vlanmc)
 527 {
 528         u32 data[2];
 529         int err;
 530         int i;
 531
 532         if (index >= RTL8366S_NUM_VLANS ||
 533             vlanmc->vid >= RTL8366S_NUM_VIDS ||
 534             vlanmc->priority > RTL8366S_PRIORITYMAX ||
 535             vlanmc->member > RTL8366S_VLAN_MEMBER_MASK ||
 536             vlanmc->untag > RTL8366S_VLAN_UNTAG_MASK ||
 537             vlanmc->fid > RTL8366S_FIDMAX)
 538                 return -EINVAL;
 539
 540         data[0] = (vlanmc->vid & RTL8366S_VLAN_VID_MASK) |
 541                   ((vlanmc->priority & RTL8366S_VLAN_PRIORITY_MASK) <<
 542                         RTL8366S_VLAN_PRIORITY_SHIFT);
 543         data[1] = (vlanmc->member & RTL8366S_VLAN_MEMBER_MASK) |
 544                   ((vlanmc->untag & RTL8366S_VLAN_UNTAG_MASK) <<
 545                         RTL8366S_VLAN_UNTAG_SHIFT) |
 546                   ((vlanmc->fid & RTL8366S_VLAN_FID_MASK) <<
 547                         RTL8366S_VLAN_FID_SHIFT);
 548
 549         for (i = 0; i < 2; i++) {
 550                 err = rtl8366_smi_write_reg(smi,
 551                                             RTL8366S_VLAN_MC_BASE(index) + i,
 552                                             data[i]);
 553                 if (err)
 554                         return err;
 555         }
 556
 557         return 0;
 558 }
 559
 560 static int rtl8366s_get_mc_index(struct rtl8366_smi *smi, int port, int *val)
 561 {
 562         u32 data;
 563         int err;
 564
 565         if (port >= RTL8366S_NUM_PORTS)
 566                 return -EINVAL;
 567
 568         err = rtl8366_smi_read_reg(smi, RTL8366S_PORT_VLAN_CTRL_REG(port),
 569                                    &data);
 570         if (err)
 571                 return err;
 572
 573         *val = (data >> RTL8366S_PORT_VLAN_CTRL_SHIFT(port)) &
 574                RTL8366S_PORT_VLAN_CTRL_MASK;
 575
 576         return 0;
 577 }
 578
 579 static int rtl8366s_set_mc_index(struct rtl8366_smi *smi, int port, int index)
 580 {
 581         if (port >= RTL8366S_NUM_PORTS || index >= RTL8366S_NUM_VLANS)
 582                 return -EINVAL;
 583
 584         return rtl8366_smi_rmwr(smi, RTL8366S_PORT_VLAN_CTRL_REG(port),
 585                                 RTL8366S_PORT_VLAN_CTRL_MASK <<
 586                                         RTL8366S_PORT_VLAN_CTRL_SHIFT(port),
 587                                 (index & RTL8366S_PORT_VLAN_CTRL_MASK) <<
 588                                         RTL8366S_PORT_VLAN_CTRL_SHIFT(port));
 589 }
 590
 591 static int rtl8366s_enable_vlan(struct rtl8366_smi *smi, int enable)
 592 {
 593         return rtl8366_smi_rmwr(smi, RTL8366S_SGCR, RTL8366S_SGCR_EN_VLAN,
 594                                 (enable) ? RTL8366S_SGCR_EN_VLAN : 0);
 595 }
 596
 597 static int rtl8366s_enable_vlan4k(struct rtl8366_smi *smi, int enable)
 598 {
 599         return rtl8366_smi_rmwr(smi, RTL8366S_VLAN_TB_CTRL_REG,
 600                                 1, (enable) ? 1 : 0);
 601 }
 602
 603 static int rtl8366s_is_vlan_valid(struct rtl8366_smi *smi, unsigned vlan)
 604 {
 605         unsigned max = RTL8366S_NUM_VLANS;
 606
 607         if (smi->vlan4k_enabled)
 608                 max = RTL8366S_NUM_VIDS - 1;
 609
 610         if (vlan == 0 || vlan >= max)
 611                 return 0;
 612
 613         return 1;
 614 }
 615
 616 static int rtl8366s_enable_port(struct rtl8366_smi *smi, int port, int enable)
 617 {
 618         return rtl8366_smi_rmwr(smi, RTL8366S_PECR, (1 << port),
 619                                 (enable) ? 0 : (1 << port));
 620 }
 621
 622 static int rtl8366s_sw_reset_mibs(struct switch_dev *dev,
 623                                   const struct switch_attr *attr,
 624                                   struct switch_val *val)
 625 {
 626         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 627
 628         return rtl8366_smi_rmwr(smi, RTL8366S_MIB_CTRL_REG, 0, (1 << 2));
 629 }
 630
 631 static int rtl8366s_sw_get_blinkrate(struct switch_dev *dev,
 632                                      const struct switch_attr *attr,
 633                                      struct switch_val *val)
 634 {
 635         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 636         u32 data;
 637
 638         rtl8366_smi_read_reg(smi, RTL8366S_LED_BLINKRATE_REG, &data);
 639
 640         val->value.i = (data & (RTL8366S_LED_BLINKRATE_MASK));
 641
 642         return 0;
 643 }
 644
 645 static int rtl8366s_sw_set_blinkrate(struct switch_dev *dev,
 646                                     const struct switch_attr *attr,
 647                                     struct switch_val *val)
 648 {
 649         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 650
 651         if (val->value.i >= 6)
 652                 return -EINVAL;
 653
 654         return rtl8366_smi_rmwr(smi, RTL8366S_LED_BLINKRATE_REG,
 655                                 RTL8366S_LED_BLINKRATE_MASK,
 656                                 val->value.i);
 657 }
 658
 659 static int rtl8366s_sw_get_max_length(struct switch_dev *dev,
 660                                         const struct switch_attr *attr,
 661                                         struct switch_val *val)
 662 {
 663         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 664         u32 data;
 665
 666         rtl8366_smi_read_reg(smi, RTL8366S_SGCR, &data);
 667
 668         val->value.i = ((data & (RTL8366S_SGCR_MAX_LENGTH_MASK)) >> 4);
 669
 670         return 0;
 671 }
 672
 673 static int rtl8366s_sw_set_max_length(struct switch_dev *dev,
 674                                         const struct switch_attr *attr,
 675                                         struct switch_val *val)
 676 {
 677         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 678         char length_code;
 679
 680         switch (val->value.i) {
 681                 case 0:
 682                         length_code = RTL8366S_SGCR_MAX_LENGTH_1522;
 683                         break;
 684                 case 1:
 685                         length_code = RTL8366S_SGCR_MAX_LENGTH_1536;
 686                         break;
 687                 case 2:
 688                         length_code = RTL8366S_SGCR_MAX_LENGTH_1552;
 689                         break;
 690                 case 3:
 691                         length_code = RTL8366S_SGCR_MAX_LENGTH_16000;
 692                         break;
 693                 default:
 694                         return -EINVAL;
 695         }
 696
 697         return rtl8366_smi_rmwr(smi, RTL8366S_SGCR,
 698                         RTL8366S_SGCR_MAX_LENGTH_MASK,
 699                         length_code);
 700 }
 701
 702 static int rtl8366s_sw_get_learning_enable(struct switch_dev *dev,
 703                                            const struct switch_attr *attr,
 704                                            struct switch_val *val)
 705 {
 706         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 707         u32 data;
 708
 709         rtl8366_smi_read_reg(smi,RTL8366S_SSCR0, &data);
 710         val->value.i = !data;
 711
 712         return 0;
 713 }
 714
 715
 716 static int rtl8366s_sw_set_learning_enable(struct switch_dev *dev,
 717                                            const struct switch_attr *attr,
 718                                            struct switch_val *val)
 719 {
 720         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 721         u32 portmask = 0;
 722         int err = 0;
 723
 724         if (!val->value.i)
 725                 portmask = RTL8366S_PORT_ALL;
 726
 727         /* set learning for all ports */
 728         REG_WR(smi, RTL8366S_SSCR0, portmask);
 729
 730         /* set auto ageing for all ports */
 731         REG_WR(smi, RTL8366S_SSCR1, portmask);
 732
 733         return 0;
 734 }
 735
 736 static int rtl8366s_sw_get_port_link(struct switch_dev *dev,
 737                                      int port,
 738                                      struct switch_port_link *link)
 739 {
 740         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 741         u32 data = 0;
 742         u32 speed;
 743
 744         if (port >= RTL8366S_NUM_PORTS)
 745                 return -EINVAL;
 746
 747         rtl8366_smi_read_reg(smi, RTL8366S_PORT_LINK_STATUS_BASE + (port / 2),
 748                              &data);
 749
 750         if (port % 2)
 751                 data = data >> 8;
 752
 753         link->link = !!(data & RTL8366S_PORT_STATUS_LINK_MASK);
 754         if (!link->link)
 755                 return 0;
 756
 757         link->duplex = !!(data & RTL8366S_PORT_STATUS_DUPLEX_MASK);
 758         link->rx_flow = !!(data & RTL8366S_PORT_STATUS_RXPAUSE_MASK);
 759         link->tx_flow = !!(data & RTL8366S_PORT_STATUS_TXPAUSE_MASK);
 760         link->aneg = !!(data & RTL8366S_PORT_STATUS_AN_MASK);
 761
 762         speed = (data & RTL8366S_PORT_STATUS_SPEED_MASK);
 763         switch (speed) {
 764         case 0:
 765                 link->speed = SWITCH_PORT_SPEED_10;
 766                 break;
 767         case 1:
 768                 link->speed = SWITCH_PORT_SPEED_100;
 769                 break;
 770         case 2:
 771                 link->speed = SWITCH_PORT_SPEED_1000;
 772                 break;
 773         default:
 774                 link->speed = SWITCH_PORT_SPEED_UNKNOWN;
 775                 break;
 776         }
 777
 778         return 0;
 779 }
 780
 781 static int rtl8366s_sw_set_port_led(struct switch_dev *dev,
 782                                     const struct switch_attr *attr,
 783                                     struct switch_val *val)
 784 {
 785         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 786         u32 data;
 787         u32 mask;
 788         u32 reg;
 789
 790         if (val->port_vlan >= RTL8366S_NUM_PORTS ||
 791             (1 << val->port_vlan) == RTL8366S_PORT_UNKNOWN)
 792                 return -EINVAL;
 793
 794         if (val->port_vlan == RTL8366S_PORT_NUM_CPU) {
 795                 reg = RTL8366S_LED_BLINKRATE_REG;
 796                 mask = 0xF << 4;
 797                 data = val->value.i << 4;
 798         } else {
 799                 reg = RTL8366S_LED_CTRL_REG;
 800                 mask = 0xF << (val->port_vlan * 4),
 801                 data = val->value.i << (val->port_vlan * 4);
 802         }
 803
 804         return rtl8366_smi_rmwr(smi, reg, mask, data);
 805 }
 806
 807 static int rtl8366s_sw_get_port_led(struct switch_dev *dev,
 808                                     const struct switch_attr *attr,
 809                                     struct switch_val *val)
 810 {
 811         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 812         u32 data = 0;
 813
 814         if (val->port_vlan >= RTL8366S_NUM_LEDGROUPS)
 815                 return -EINVAL;
 816
 817         rtl8366_smi_read_reg(smi, RTL8366S_LED_CTRL_REG, &data);
 818         val->value.i = (data >> (val->port_vlan * 4)) & 0x000F;
 819
 820         return 0;
 821 }
 822
 823 static int rtl8366s_sw_reset_port_mibs(struct switch_dev *dev,
 824                                        const struct switch_attr *attr,
 825                                        struct switch_val *val)
 826 {
 827         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 828
 829         if (val->port_vlan >= RTL8366S_NUM_PORTS)
 830                 return -EINVAL;
 831
 832
 833         return rtl8366_smi_rmwr(smi, RTL8366S_MIB_CTRL_REG,
 834                                 0, (1 << (val->port_vlan + 3)));
 835 }
 836
 837 static struct switch_attr rtl8366s_globals[] = {
 838         {
 839                 .type = SWITCH_TYPE_INT,
 840                 .name = "enable_learning",
 841                 .description = "Enable learning, enable aging",
 842                 .set = rtl8366s_sw_set_learning_enable,
 843                 .get = rtl8366s_sw_get_learning_enable,
 844                 .max = 1,
 845         }, {
 846                 .type = SWITCH_TYPE_INT,
 847                 .name = "enable_vlan",
 848                 .description = "Enable VLAN mode",
 849                 .set = rtl8366_sw_set_vlan_enable,
 850                 .get = rtl8366_sw_get_vlan_enable,
 851                 .max = 1,
 852                 .ofs = 1
 853         }, {
 854                 .type = SWITCH_TYPE_INT,
 855                 .name = "enable_vlan4k",
 856                 .description = "Enable VLAN 4K mode",
 857                 .set = rtl8366_sw_set_vlan_enable,
 858                 .get = rtl8366_sw_get_vlan_enable,
 859                 .max = 1,
 860                 .ofs = 2
 861         }, {
 862                 .type = SWITCH_TYPE_NOVAL,
 863                 .name = "reset_mibs",
 864                 .description = "Reset all MIB counters",
 865                 .set = rtl8366s_sw_reset_mibs,
 866         }, {
 867                 .type = SWITCH_TYPE_INT,
 868                 .name = "blinkrate",
 869                 .description = "Get/Set LED blinking rate (0 = 43ms, 1 = 84ms,"
 870                 " 2 = 120ms, 3 = 170ms, 4 = 340ms, 5 = 670ms)",
 871                 .set = rtl8366s_sw_set_blinkrate,
 872                 .get = rtl8366s_sw_get_blinkrate,
 873                 .max = 5
 874         }, {
 875                 .type = SWITCH_TYPE_INT,
 876                 .name = "max_length",
 877                 .description = "Get/Set the maximum length of valid packets"
 878                 " (0 = 1522, 1 = 1536, 2 = 1552, 3 = 16000 (9216?))",
 879                 .set = rtl8366s_sw_set_max_length,
 880                 .get = rtl8366s_sw_get_max_length,
 881                 .max = 3,
 882         },
 883 };
 884
 885 static struct switch_attr rtl8366s_port[] = {
 886         {
 887                 .type = SWITCH_TYPE_NOVAL,
 888                 .name = "reset_mib",
 889                 .description = "Reset single port MIB counters",
 890                 .set = rtl8366s_sw_reset_port_mibs,
 891         }, {
 892                 .type = SWITCH_TYPE_STRING,
 893                 .name = "mib",
 894                 .description = "Get MIB counters for port",
 895                 .max = 33,
 896                 .set = NULL,
 897                 .get = rtl8366_sw_get_port_mib,
 898         }, {
 899                 .type = SWITCH_TYPE_INT,
 900                 .name = "led",
 901                 .description = "Get/Set port group (0 - 3) led mode (0 - 15)",
 902                 .max = 15,
 903                 .set = rtl8366s_sw_set_port_led,
 904                 .get = rtl8366s_sw_get_port_led,
 905         },
 906 };
 907
 908 static struct switch_attr rtl8366s_vlan[] = {
 909         {
 910                 .type = SWITCH_TYPE_STRING,
 911                 .name = "info",
 912                 .description = "Get vlan information",
 913                 .max = 1,
 914                 .set = NULL,
 915                 .get = rtl8366_sw_get_vlan_info,
 916         }, {
 917                 .type = SWITCH_TYPE_INT,
 918                 .name = "fid",
 919                 .description = "Get/Set vlan FID",
 920                 .max = RTL8366S_FIDMAX,
 921                 .set = rtl8366_sw_set_vlan_fid,
 922                 .get = rtl8366_sw_get_vlan_fid,
 923         },
 924 };
 925
 926 static const struct switch_dev_ops rtl8366_ops = {
 927         .attr_global = {
 928                 .attr = rtl8366s_globals,
 929                 .n_attr = ARRAY_SIZE(rtl8366s_globals),
 930         },
 931         .attr_port = {
 932                 .attr = rtl8366s_port,
 933                 .n_attr = ARRAY_SIZE(rtl8366s_port),
 934         },
 935         .attr_vlan = {
 936                 .attr = rtl8366s_vlan,
 937                 .n_attr = ARRAY_SIZE(rtl8366s_vlan),
 938         },
 939
 940         .get_vlan_ports = rtl8366_sw_get_vlan_ports,
 941         .set_vlan_ports = rtl8366_sw_set_vlan_ports,
 942         .get_port_pvid = rtl8366_sw_get_port_pvid,
 943         .set_port_pvid = rtl8366_sw_set_port_pvid,
 944         .reset_switch = rtl8366_sw_reset_switch,
 945         .get_port_link = rtl8366s_sw_get_port_link,
 946 };
 947
 948 static int rtl8366s_switch_init(struct rtl8366_smi *smi)
 949 {
 950         struct switch_dev *dev = &smi->sw_dev;
 951         int err;
 952
 953         dev->name = "RTL8366S";
 954         dev->cpu_port = RTL8366S_PORT_NUM_CPU;
 955         dev->ports = RTL8366S_NUM_PORTS;
 956         dev->vlans = RTL8366S_NUM_VIDS;
 957         dev->ops = &rtl8366_ops;
 958         dev->alias = dev_name(smi->parent);
 959
 960         err = register_switch(dev, NULL);
 961         if (err)
 962                 dev_err(smi->parent, "switch registration failed\n");
 963
 964         return err;
 965 }
 966
 967 static void rtl8366s_switch_cleanup(struct rtl8366_smi *smi)
 968 {
 969         unregister_switch(&smi->sw_dev);
 970 }
 971
 972 static int rtl8366s_mii_read(struct mii_bus *bus, int addr, int reg)
 973 {
 974         struct rtl8366_smi *smi = bus->priv;
 975         u32 val = 0;
 976         int err;
 977
 978         err = rtl8366s_read_phy_reg(smi, addr, 0, reg, &val);
 979         if (err)
 980                 return 0xffff;
 981
 982         return val;
 983 }
 984
 985 static int rtl8366s_mii_write(struct mii_bus *bus, int addr, int reg, u16 val)
 986 {
 987         struct rtl8366_smi *smi = bus->priv;
 988         u32 t;
 989         int err;
 990
 991         err = rtl8366s_write_phy_reg(smi, addr, 0, reg, val);
 992         /* flush write */
 993         (void) rtl8366s_read_phy_reg(smi, addr, 0, reg, &t);
 994
 995         return err;
 996 }
 997
 998 static int rtl8366s_detect(struct rtl8366_smi *smi)
 999 {
1000         u32 chip_id = 0;
1001         u32 chip_ver = 0;
1002         int ret;
1003
1004         ret = rtl8366_smi_read_reg(smi, RTL8366S_CHIP_ID_REG, &chip_id);
1005         if (ret) {
1006                 dev_err(smi->parent, "unable to read chip id\n");
1007                 return ret;
1008         }
1009
1010         switch (chip_id) {
1011         case RTL8366S_CHIP_ID_8366:
1012                 break;
1013         default:
1014                 dev_err(smi->parent, "unknown chip id (%04x)\n", chip_id);
1015                 return -ENODEV;
1016         }
1017
1018         ret = rtl8366_smi_read_reg(smi, RTL8366S_CHIP_VERSION_CTRL_REG,
1019                                    &chip_ver);
1020         if (ret) {
1021                 dev_err(smi->parent, "unable to read chip version\n");
1022                 return ret;
1023         }
1024
1025         dev_info(smi->parent, "RTL%04x ver. %u chip found\n",
1026                  chip_id, chip_ver & RTL8366S_CHIP_VERSION_MASK);
1027
1028         return 0;
1029 }
1030
1031 static struct rtl8366_smi_ops rtl8366s_smi_ops = {
1032         .detect         = rtl8366s_detect,
1033         .reset_chip     = rtl8366s_reset_chip,
1034         .setup          = rtl8366s_setup,
1035
1036         .mii_read       = rtl8366s_mii_read,
1037         .mii_write      = rtl8366s_mii_write,
1038
1039         .get_vlan_mc    = rtl8366s_get_vlan_mc,
1040         .set_vlan_mc    = rtl8366s_set_vlan_mc,
1041         .get_vlan_4k    = rtl8366s_get_vlan_4k,
1042         .set_vlan_4k    = rtl8366s_set_vlan_4k,
1043         .get_mc_index   = rtl8366s_get_mc_index,
1044         .set_mc_index   = rtl8366s_set_mc_index,
1045         .get_mib_counter = rtl8366_get_mib_counter,
1046         .is_vlan_valid  = rtl8366s_is_vlan_valid,
1047         .enable_vlan    = rtl8366s_enable_vlan,
1048         .enable_vlan4k  = rtl8366s_enable_vlan4k,
1049         .enable_port    = rtl8366s_enable_port,
1050 };
1051
1052 static int __devinit rtl8366s_probe(struct platform_device *pdev)
1053 {
1054         static int rtl8366_smi_version_printed;
1055         struct rtl8366_platform_data *pdata;
1056         struct rtl8366_smi *smi;
1057         int err;
1058
1059         if (!rtl8366_smi_version_printed++)
1060                 printk(KERN_NOTICE RTL8366S_DRIVER_DESC
1061                        " version " RTL8366S_DRIVER_VER"\n");
1062
1063         smi = rtl8366_smi_probe(pdev);
1064         if (!smi)
1065                 return -ENODEV;
1066
1067         smi->clk_delay = 10;
1068         smi->cmd_read = 0xa9;
1069         smi->cmd_write = 0xa8;
1070         smi->ops = &rtl8366s_smi_ops;
1071         smi->cpu_port = RTL8366S_PORT_NUM_CPU;
1072         smi->num_ports = RTL8366S_NUM_PORTS;
1073         smi->num_vlan_mc = RTL8366S_NUM_VLANS;
1074         smi->mib_counters = rtl8366s_mib_counters;
1075         smi->num_mib_counters = ARRAY_SIZE(rtl8366s_mib_counters);
1076
1077         err = rtl8366_smi_init(smi);
1078         if (err)
1079                 goto err_free_smi;
1080
1081         platform_set_drvdata(pdev, smi);
1082
1083         err = rtl8366s_switch_init(smi);
1084         if (err)
1085                 goto err_clear_drvdata;
1086
1087         return 0;
1088
1089  err_clear_drvdata:
1090         platform_set_drvdata(pdev, NULL);
1091         rtl8366_smi_cleanup(smi);
1092  err_free_smi:
1093         kfree(smi);
1094  err_out:
1095         return err;
1096 }
1097
1098 static int __devexit rtl8366s_remove(struct platform_device *pdev)
1099 {
1100         struct rtl8366_smi *smi = platform_get_drvdata(pdev);
1101
1102         if (smi) {
1103                 rtl8366s_switch_cleanup(smi);
1104                 platform_set_drvdata(pdev, NULL);
1105                 rtl8366_smi_cleanup(smi);
1106                 kfree(smi);
1107         }
1108
1109         return 0;
1110 }
1111
1112 #ifdef CONFIG_OF
1113 static const struct of_device_id rtl8366s_match[] = {
1114         { .compatible = "rtl8366s" },
1115         {},
1116 };
1117 MODULE_DEVICE_TABLE(of, rtl8366s_match);
1118 #endif
1119
1120 static struct platform_driver rtl8366s_driver = {
1121         .driver = {
1122                 .name           = RTL8366S_DRIVER_NAME,
1123                 .owner          = THIS_MODULE,
1124 #ifdef CONFIG_OF
1125                 .of_match_table = of_match_ptr(rtl8366s_match),
1126 #endif
1127         },
1128         .probe          = rtl8366s_probe,
1129         .remove         = __devexit_p(rtl8366s_remove),
1130 };
1131
1132 static int __init rtl8366s_module_init(void)
1133 {
1134         return platform_driver_register(&rtl8366s_driver);
1135 }
1136 module_init(rtl8366s_module_init);
1137
1138 static void __exit rtl8366s_module_exit(void)
1139 {
1140         platform_driver_unregister(&rtl8366s_driver);
1141 }
1142 module_exit(rtl8366s_module_exit);
1143
1144 MODULE_DESCRIPTION(RTL8366S_DRIVER_DESC);
1145 MODULE_VERSION(RTL8366S_DRIVER_VER);
1146 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
1147 MODULE_AUTHOR("Antti Seppälä <a.seppala@gmail.com>");
1148 MODULE_LICENSE("GPL v2");
1149 MODULE_ALIAS("platform:" RTL8366S_DRIVER_NAME);