2 * Platform driver for the Realtek RTL8366S ethernet switch
4 * Copyright (C) 2009-2010 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2010 Antti Seppälä <a.seppala@gmail.com>
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published
9 * by the Free Software Foundation.
12 #include <linux/kernel.h>
13 #include <linux/module.h>
14 #include <linux/init.h>
15 #include <linux/platform_device.h>
16 #include <linux/delay.h>
17 #include <linux/skbuff.h>
18 #include <linux/switch.h>
19 #include <linux/rtl8366s.h>
21 #include "rtl8366_smi.h"
23 #ifdef CONFIG_RTL8366S_PHY_DEBUG_FS
24 #include <linux/debugfs.h>
27 #define RTL8366S_DRIVER_DESC "Realtek RTL8366S ethernet switch driver"
28 #define RTL8366S_DRIVER_VER "0.2.2"
30 #define RTL8366S_PHY_NO_MAX 4
31 #define RTL8366S_PHY_PAGE_MAX 7
32 #define RTL8366S_PHY_ADDR_MAX 31
34 #define RTL8366S_CHIP_GLOBAL_CTRL_REG 0x0000
35 #define RTL8366S_CHIP_CTRL_VLAN (1 << 13)
37 /* Switch Global Configuration register */
38 #define RTL8366S_SGCR 0x0000
39 #define RTL8366S_SGCR_EN_BC_STORM_CTRL BIT(0)
40 #define RTL8366S_SGCR_MAX_LENGTH(_x) (_x << 4)
41 #define RTL8366S_SGCR_MAX_LENGTH_MASK RTL8366S_SGCR_MAX_LENGTH(0x3)
42 #define RTL8366S_SGCR_MAX_LENGTH_1522 RTL8366S_SGCR_MAX_LENGTH(0x0)
43 #define RTL8366S_SGCR_MAX_LENGTH_1536 RTL8366S_SGCR_MAX_LENGTH(0x1)
44 #define RTL8366S_SGCR_MAX_LENGTH_1552 RTL8366S_SGCR_MAX_LENGTH(0x2)
45 #define RTL8366S_SGCR_MAX_LENGTH_16000 RTL8366S_SGCR_MAX_LENGTH(0x3)
47 /* Port Enable Control register */
48 #define RTL8366S_PECR 0x0001
50 /* Switch Security Control registers */
51 #define RTL8366S_SSCR0 0x0002
52 #define RTL8366S_SSCR1 0x0003
53 #define RTL8366S_SSCR2 0x0004
54 #define RTL8366S_SSCR2_DROP_UNKNOWN_DA BIT(0)
56 #define RTL8366S_RESET_CTRL_REG 0x0100
57 #define RTL8366S_CHIP_CTRL_RESET_HW 1
58 #define RTL8366S_CHIP_CTRL_RESET_SW (1 << 1)
60 #define RTL8366S_CHIP_VERSION_CTRL_REG 0x0104
61 #define RTL8366S_CHIP_VERSION_MASK 0xf
62 #define RTL8366S_CHIP_ID_REG 0x0105
63 #define RTL8366S_CHIP_ID_8366 0x8366
65 /* PHY registers control */
66 #define RTL8366S_PHY_ACCESS_CTRL_REG 0x8028
67 #define RTL8366S_PHY_ACCESS_DATA_REG 0x8029
69 #define RTL8366S_PHY_CTRL_READ 1
70 #define RTL8366S_PHY_CTRL_WRITE 0
72 #define RTL8366S_PHY_REG_MASK 0x1f
73 #define RTL8366S_PHY_PAGE_OFFSET 5
74 #define RTL8366S_PHY_PAGE_MASK (0x7 << 5)
75 #define RTL8366S_PHY_NO_OFFSET 9
76 #define RTL8366S_PHY_NO_MASK (0x1f << 9)
78 /* LED control registers */
79 #define RTL8366S_LED_BLINKRATE_REG 0x0420
80 #define RTL8366S_LED_BLINKRATE_BIT 0
81 #define RTL8366S_LED_BLINKRATE_MASK 0x0007
83 #define RTL8366S_LED_CTRL_REG 0x0421
84 #define RTL8366S_LED_0_1_CTRL_REG 0x0422
85 #define RTL8366S_LED_2_3_CTRL_REG 0x0423
87 #define RTL8366S_MIB_COUNT 33
88 #define RTL8366S_GLOBAL_MIB_COUNT 1
89 #define RTL8366S_MIB_COUNTER_PORT_OFFSET 0x0040
90 #define RTL8366S_MIB_COUNTER_BASE 0x1000
91 #define RTL8366S_MIB_COUNTER_PORT_OFFSET2 0x0008
92 #define RTL8366S_MIB_COUNTER_BASE2 0x1180
93 #define RTL8366S_MIB_CTRL_REG 0x11F0
94 #define RTL8366S_MIB_CTRL_USER_MASK 0x01FF
95 #define RTL8366S_MIB_CTRL_BUSY_MASK 0x0001
96 #define RTL8366S_MIB_CTRL_RESET_MASK 0x0002
98 #define RTL8366S_MIB_CTRL_GLOBAL_RESET_MASK 0x0004
99 #define RTL8366S_MIB_CTRL_PORT_RESET_BIT 0x0003
100 #define RTL8366S_MIB_CTRL_PORT_RESET_MASK 0x01FC
103 #define RTL8366S_PORT_VLAN_CTRL_BASE 0x0058
104 #define RTL8366S_PORT_VLAN_CTRL_REG(_p) \
105 (RTL8366S_PORT_VLAN_CTRL_BASE + (_p) / 4)
106 #define RTL8366S_PORT_VLAN_CTRL_MASK 0xf
107 #define RTL8366S_PORT_VLAN_CTRL_SHIFT(_p) (4 * ((_p) % 4))
110 #define RTL8366S_VLAN_TABLE_READ_BASE 0x018B
111 #define RTL8366S_VLAN_TABLE_WRITE_BASE 0x0185
113 #define RTL8366S_VLAN_TB_CTRL_REG 0x010F
115 #define RTL8366S_TABLE_ACCESS_CTRL_REG 0x0180
116 #define RTL8366S_TABLE_VLAN_READ_CTRL 0x0E01
117 #define RTL8366S_TABLE_VLAN_WRITE_CTRL 0x0F01
119 #define RTL8366S_VLAN_MEMCONF_BASE 0x0016
122 #define RTL8366S_PORT_LINK_STATUS_BASE 0x0060
123 #define RTL8366S_PORT_STATUS_SPEED_MASK 0x0003
124 #define RTL8366S_PORT_STATUS_DUPLEX_MASK 0x0004
125 #define RTL8366S_PORT_STATUS_LINK_MASK 0x0010
126 #define RTL8366S_PORT_STATUS_TXPAUSE_MASK 0x0020
127 #define RTL8366S_PORT_STATUS_RXPAUSE_MASK 0x0040
128 #define RTL8366S_PORT_STATUS_AN_MASK 0x0080
131 #define RTL8366S_PORT_NUM_CPU 5
132 #define RTL8366S_NUM_PORTS 6
133 #define RTL8366S_NUM_VLANS 16
134 #define RTL8366S_NUM_LEDGROUPS 4
135 #define RTL8366S_NUM_VIDS 4096
136 #define RTL8366S_PRIORITYMAX 7
137 #define RTL8366S_FIDMAX 7
140 #define RTL8366S_PORT_1 (1 << 0) /* In userspace port 0 */
141 #define RTL8366S_PORT_2 (1 << 1) /* In userspace port 1 */
142 #define RTL8366S_PORT_3 (1 << 2) /* In userspace port 2 */
143 #define RTL8366S_PORT_4 (1 << 3) /* In userspace port 3 */
145 #define RTL8366S_PORT_UNKNOWN (1 << 4) /* No known connection */
146 #define RTL8366S_PORT_CPU (1 << 5) /* CPU port */
148 #define RTL8366S_PORT_ALL (RTL8366S_PORT_1 | \
152 RTL8366S_PORT_UNKNOWN | \
155 #define RTL8366S_PORT_ALL_BUT_CPU (RTL8366S_PORT_1 | \
159 RTL8366S_PORT_UNKNOWN)
161 #define RTL8366S_PORT_ALL_EXTERNAL (RTL8366S_PORT_1 | \
166 #define RTL8366S_PORT_ALL_INTERNAL (RTL8366S_PORT_UNKNOWN | \
170 struct device *parent;
171 struct rtl8366_smi smi;
172 struct switch_dev dev;
175 struct rtl8366s_vlan_mc {
186 struct rtl8366s_vlan_4k {
196 static struct rtl8366_mib_counter rtl8366s_mib_counters[] = {
197 { 0, 0, 4, "IfInOctets" },
198 { 0, 4, 4, "EtherStatsOctets" },
199 { 0, 8, 2, "EtherStatsUnderSizePkts" },
200 { 0, 10, 2, "EtherFragments" },
201 { 0, 12, 2, "EtherStatsPkts64Octets" },
202 { 0, 14, 2, "EtherStatsPkts65to127Octets" },
203 { 0, 16, 2, "EtherStatsPkts128to255Octets" },
204 { 0, 18, 2, "EtherStatsPkts256to511Octets" },
205 { 0, 20, 2, "EtherStatsPkts512to1023Octets" },
206 { 0, 22, 2, "EtherStatsPkts1024to1518Octets" },
207 { 0, 24, 2, "EtherOversizeStats" },
208 { 0, 26, 2, "EtherStatsJabbers" },
209 { 0, 28, 2, "IfInUcastPkts" },
210 { 0, 30, 2, "EtherStatsMulticastPkts" },
211 { 0, 32, 2, "EtherStatsBroadcastPkts" },
212 { 0, 34, 2, "EtherStatsDropEvents" },
213 { 0, 36, 2, "Dot3StatsFCSErrors" },
214 { 0, 38, 2, "Dot3StatsSymbolErrors" },
215 { 0, 40, 2, "Dot3InPauseFrames" },
216 { 0, 42, 2, "Dot3ControlInUnknownOpcodes" },
217 { 0, 44, 4, "IfOutOctets" },
218 { 0, 48, 2, "Dot3StatsSingleCollisionFrames" },
219 { 0, 50, 2, "Dot3StatMultipleCollisionFrames" },
220 { 0, 52, 2, "Dot3sDeferredTransmissions" },
221 { 0, 54, 2, "Dot3StatsLateCollisions" },
222 { 0, 56, 2, "EtherStatsCollisions" },
223 { 0, 58, 2, "Dot3StatsExcessiveCollisions" },
224 { 0, 60, 2, "Dot3OutPauseFrames" },
225 { 0, 62, 2, "Dot1dBasePortDelayExceededDiscards" },
228 * The following counters are accessible at a different
231 { 1, 0, 2, "Dot1dTpPortInDiscards" },
232 { 1, 2, 2, "IfOutUcastPkts" },
233 { 1, 4, 2, "IfOutMulticastPkts" },
234 { 1, 6, 2, "IfOutBroadcastPkts" },
237 #define REG_WR(_smi, _reg, _val) \
239 err = rtl8366_smi_write_reg(_smi, _reg, _val); \
244 #define REG_RMW(_smi, _reg, _mask, _val) \
246 err = rtl8366_smi_rmwr(_smi, _reg, _mask, _val); \
251 static inline struct rtl8366s *smi_to_rtl8366s(struct rtl8366_smi *smi)
253 return container_of(smi, struct rtl8366s, smi);
256 static inline struct rtl8366s *sw_to_rtl8366s(struct switch_dev *sw)
258 return container_of(sw, struct rtl8366s, dev);
261 static inline struct rtl8366_smi *sw_to_rtl8366_smi(struct switch_dev *sw)
263 struct rtl8366s *rtl = sw_to_rtl8366s(sw);
267 static int rtl8366s_reset_chip(struct rtl8366_smi *smi)
272 rtl8366_smi_write_reg(smi, RTL8366S_RESET_CTRL_REG,
273 RTL8366S_CHIP_CTRL_RESET_HW);
276 if (rtl8366_smi_read_reg(smi, RTL8366S_RESET_CTRL_REG, &data))
279 if (!(data & RTL8366S_CHIP_CTRL_RESET_HW))
284 printk("Timeout waiting for the switch to reset\n");
291 static int rtl8366s_hw_init(struct rtl8366_smi *smi)
295 /* set maximum packet length to 1536 bytes */
296 REG_RMW(smi, RTL8366S_SGCR, RTL8366S_SGCR_MAX_LENGTH_MASK,
297 RTL8366S_SGCR_MAX_LENGTH_1536);
299 /* enable all ports */
300 REG_WR(smi, RTL8366S_PECR, 0);
302 /* disable learning for all ports */
303 REG_WR(smi, RTL8366S_SSCR0, RTL8366S_PORT_ALL);
305 /* disable auto ageing for all ports */
306 REG_WR(smi, RTL8366S_SSCR1, RTL8366S_PORT_ALL);
308 /* don't drop packets whose DA has not been learned */
309 REG_RMW(smi, RTL8366S_SSCR2, RTL8366S_SSCR2_DROP_UNKNOWN_DA, 0);
314 static int rtl8366s_read_phy_reg(struct rtl8366_smi *smi,
315 u32 phy_no, u32 page, u32 addr, u32 *data)
320 if (phy_no > RTL8366S_PHY_NO_MAX)
323 if (page > RTL8366S_PHY_PAGE_MAX)
326 if (addr > RTL8366S_PHY_ADDR_MAX)
329 ret = rtl8366_smi_write_reg(smi, RTL8366S_PHY_ACCESS_CTRL_REG,
330 RTL8366S_PHY_CTRL_READ);
334 reg = 0x8000 | (1 << (phy_no + RTL8366S_PHY_NO_OFFSET)) |
335 ((page << RTL8366S_PHY_PAGE_OFFSET) & RTL8366S_PHY_PAGE_MASK) |
336 (addr & RTL8366S_PHY_REG_MASK);
338 ret = rtl8366_smi_write_reg(smi, reg, 0);
342 ret = rtl8366_smi_read_reg(smi, RTL8366S_PHY_ACCESS_DATA_REG, data);
349 static int rtl8366s_write_phy_reg(struct rtl8366_smi *smi,
350 u32 phy_no, u32 page, u32 addr, u32 data)
355 if (phy_no > RTL8366S_PHY_NO_MAX)
358 if (page > RTL8366S_PHY_PAGE_MAX)
361 if (addr > RTL8366S_PHY_ADDR_MAX)
364 ret = rtl8366_smi_write_reg(smi, RTL8366S_PHY_ACCESS_CTRL_REG,
365 RTL8366S_PHY_CTRL_WRITE);
369 reg = 0x8000 | (1 << (phy_no + RTL8366S_PHY_NO_OFFSET)) |
370 ((page << RTL8366S_PHY_PAGE_OFFSET) & RTL8366S_PHY_PAGE_MASK) |
371 (addr & RTL8366S_PHY_REG_MASK);
373 ret = rtl8366_smi_write_reg(smi, reg, data);
380 static int rtl8366_get_mib_counter(struct rtl8366_smi *smi, int counter,
381 int port, unsigned long long *val)
388 if (port > RTL8366S_NUM_PORTS || counter >= RTL8366S_MIB_COUNT)
391 switch (rtl8366s_mib_counters[counter].base) {
393 addr = RTL8366S_MIB_COUNTER_BASE +
394 RTL8366S_MIB_COUNTER_PORT_OFFSET * port;
398 addr = RTL8366S_MIB_COUNTER_BASE2 +
399 RTL8366S_MIB_COUNTER_PORT_OFFSET2 * port;
406 addr += rtl8366s_mib_counters[counter].offset;
409 * Writing access counter address first
410 * then ASIC will prepare 64bits counter wait for being retrived
412 data = 0; /* writing data will be discard by ASIC */
413 err = rtl8366_smi_write_reg(smi, addr, data);
417 /* read MIB control register */
418 err = rtl8366_smi_read_reg(smi, RTL8366S_MIB_CTRL_REG, &data);
422 if (data & RTL8366S_MIB_CTRL_BUSY_MASK)
425 if (data & RTL8366S_MIB_CTRL_RESET_MASK)
429 for (i = rtl8366s_mib_counters[counter].length; i > 0; i--) {
430 err = rtl8366_smi_read_reg(smi, addr + (i - 1), &data);
434 mibvalue = (mibvalue << 16) | (data & 0xFFFF);
441 static int rtl8366s_get_vlan_4k(struct rtl8366_smi *smi, u32 vid,
442 struct rtl8366_vlan_4k *vlan4k)
444 struct rtl8366s_vlan_4k vlan4k_priv;
449 memset(vlan4k, '\0', sizeof(struct rtl8366_vlan_4k));
450 vlan4k_priv.vid = vid;
452 if (vid >= RTL8366S_NUM_VIDS)
455 tableaddr = (u16 *)&vlan4k_priv;
459 err = rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TABLE_WRITE_BASE, data);
463 /* write table access control word */
464 err = rtl8366_smi_write_reg(smi, RTL8366S_TABLE_ACCESS_CTRL_REG,
465 RTL8366S_TABLE_VLAN_READ_CTRL);
469 err = rtl8366_smi_read_reg(smi, RTL8366S_VLAN_TABLE_READ_BASE, &data);
476 err = rtl8366_smi_read_reg(smi, RTL8366S_VLAN_TABLE_READ_BASE + 1,
484 vlan4k->untag = vlan4k_priv.untag;
485 vlan4k->member = vlan4k_priv.member;
486 vlan4k->fid = vlan4k_priv.fid;
491 static int rtl8366s_set_vlan_4k(struct rtl8366_smi *smi,
492 const struct rtl8366_vlan_4k *vlan4k)
494 struct rtl8366s_vlan_4k vlan4k_priv;
499 if (vlan4k->vid >= RTL8366S_NUM_VIDS ||
500 vlan4k->member > RTL8366S_PORT_ALL ||
501 vlan4k->untag > RTL8366S_PORT_ALL ||
502 vlan4k->fid > RTL8366S_FIDMAX)
505 vlan4k_priv.vid = vlan4k->vid;
506 vlan4k_priv.untag = vlan4k->untag;
507 vlan4k_priv.member = vlan4k->member;
508 vlan4k_priv.fid = vlan4k->fid;
510 tableaddr = (u16 *)&vlan4k_priv;
514 err = rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TABLE_WRITE_BASE, data);
522 err = rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TABLE_WRITE_BASE + 1,
527 /* write table access control word */
528 err = rtl8366_smi_write_reg(smi, RTL8366S_TABLE_ACCESS_CTRL_REG,
529 RTL8366S_TABLE_VLAN_WRITE_CTRL);
534 static int rtl8366s_get_vlan_mc(struct rtl8366_smi *smi, u32 index,
535 struct rtl8366_vlan_mc *vlanmc)
537 struct rtl8366s_vlan_mc vlanmc_priv;
543 memset(vlanmc, '\0', sizeof(struct rtl8366_vlan_mc));
545 if (index >= RTL8366S_NUM_VLANS)
548 tableaddr = (u16 *)&vlanmc_priv;
550 addr = RTL8366S_VLAN_MEMCONF_BASE + (index << 1);
551 err = rtl8366_smi_read_reg(smi, addr, &data);
558 addr = RTL8366S_VLAN_MEMCONF_BASE + 1 + (index << 1);
559 err = rtl8366_smi_read_reg(smi, addr, &data);
565 vlanmc->vid = vlanmc_priv.vid;
566 vlanmc->priority = vlanmc_priv.priority;
567 vlanmc->untag = vlanmc_priv.untag;
568 vlanmc->member = vlanmc_priv.member;
569 vlanmc->fid = vlanmc_priv.fid;
574 static int rtl8366s_set_vlan_mc(struct rtl8366_smi *smi, u32 index,
575 const struct rtl8366_vlan_mc *vlanmc)
577 struct rtl8366s_vlan_mc vlanmc_priv;
583 if (index >= RTL8366S_NUM_VLANS ||
584 vlanmc->vid >= RTL8366S_NUM_VIDS ||
585 vlanmc->priority > RTL8366S_PRIORITYMAX ||
586 vlanmc->member > RTL8366S_PORT_ALL ||
587 vlanmc->untag > RTL8366S_PORT_ALL ||
588 vlanmc->fid > RTL8366S_FIDMAX)
591 vlanmc_priv.vid = vlanmc->vid;
592 vlanmc_priv.priority = vlanmc->priority;
593 vlanmc_priv.untag = vlanmc->untag;
594 vlanmc_priv.member = vlanmc->member;
595 vlanmc_priv.fid = vlanmc->fid;
597 addr = RTL8366S_VLAN_MEMCONF_BASE + (index << 1);
599 tableaddr = (u16 *)&vlanmc_priv;
602 err = rtl8366_smi_write_reg(smi, addr, data);
606 addr = RTL8366S_VLAN_MEMCONF_BASE + 1 + (index << 1);
611 err = rtl8366_smi_write_reg(smi, addr, data);
618 static int rtl8366s_get_mc_index(struct rtl8366_smi *smi, int port, int *val)
623 if (port >= RTL8366S_NUM_PORTS)
626 err = rtl8366_smi_read_reg(smi, RTL8366S_PORT_VLAN_CTRL_REG(port),
631 *val = (data >> RTL8366S_PORT_VLAN_CTRL_SHIFT(port)) &
632 RTL8366S_PORT_VLAN_CTRL_MASK;
637 static int rtl8366s_set_mc_index(struct rtl8366_smi *smi, int port, int index)
639 if (port >= RTL8366S_NUM_PORTS || index >= RTL8366S_NUM_VLANS)
642 return rtl8366_smi_rmwr(smi, RTL8366S_PORT_VLAN_CTRL_REG(port),
643 RTL8366S_PORT_VLAN_CTRL_MASK <<
644 RTL8366S_PORT_VLAN_CTRL_SHIFT(port),
645 (index & RTL8366S_PORT_VLAN_CTRL_MASK) <<
646 RTL8366S_PORT_VLAN_CTRL_SHIFT(port));
649 static int rtl8366s_vlan_set_vlan(struct rtl8366_smi *smi, int enable)
651 return rtl8366_smi_rmwr(smi, RTL8366S_CHIP_GLOBAL_CTRL_REG,
652 RTL8366S_CHIP_CTRL_VLAN,
653 (enable) ? RTL8366S_CHIP_CTRL_VLAN : 0);
656 static int rtl8366s_vlan_set_4ktable(struct rtl8366_smi *smi, int enable)
658 return rtl8366_smi_rmwr(smi, RTL8366S_VLAN_TB_CTRL_REG,
659 1, (enable) ? 1 : 0);
662 #ifdef CONFIG_RTL8366S_PHY_DEBUG_FS
663 static ssize_t rtl8366s_read_debugfs_mibs(struct file *file,
664 char __user *user_buf,
665 size_t count, loff_t *ppos)
667 struct rtl8366_smi *smi = (struct rtl8366_smi *)file->private_data;
669 char *buf = smi->buf;
671 len += snprintf(buf + len, sizeof(smi->buf) - len,
672 "%-36s %12s %12s %12s %12s %12s %12s\n",
674 "Port 0", "Port 1", "Port 2",
675 "Port 3", "Port 4", "Port 5");
677 for (i = 0; i < ARRAY_SIZE(rtl8366s_mib_counters); ++i) {
678 len += snprintf(buf + len, sizeof(smi->buf) - len, "%-36s ",
679 rtl8366s_mib_counters[i].name);
680 for (j = 0; j < RTL8366S_NUM_PORTS; ++j) {
681 unsigned long long counter = 0;
683 if (!rtl8366_get_mib_counter(smi, i, j, &counter))
684 len += snprintf(buf + len,
685 sizeof(smi->buf) - len,
688 len += snprintf(buf + len,
689 sizeof(smi->buf) - len,
692 len += snprintf(buf + len, sizeof(smi->buf) - len, "\n");
695 return simple_read_from_buffer(user_buf, count, ppos, buf, len);
698 static const struct file_operations fops_rtl8366s_mibs = {
699 .read = rtl8366s_read_debugfs_mibs,
700 .open = rtl8366_debugfs_open,
704 static void rtl8366s_debugfs_init(struct rtl8366_smi *smi)
708 if (!smi->debugfs_root)
711 node = debugfs_create_file("mibs", S_IRUSR, smi->debugfs_root, smi,
712 &fops_rtl8366s_mibs);
714 dev_err(smi->parent, "Creating debugfs file '%s' failed\n",
718 static inline void rtl8366s_debugfs_init(struct rtl8366_smi *smi) {}
719 #endif /* CONFIG_RTL8366S_PHY_DEBUG_FS */
721 static int rtl8366s_sw_reset_mibs(struct switch_dev *dev,
722 const struct switch_attr *attr,
723 struct switch_val *val)
725 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
728 if (val->value.i == 1)
729 err = rtl8366_smi_rmwr(smi, RTL8366S_MIB_CTRL_REG, 0, (1 << 2));
734 static int rtl8366s_sw_get_vlan_enable(struct switch_dev *dev,
735 const struct switch_attr *attr,
736 struct switch_val *val)
738 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
741 if (attr->ofs == 1) {
742 rtl8366_smi_read_reg(smi, RTL8366S_CHIP_GLOBAL_CTRL_REG, &data);
744 if (data & RTL8366S_CHIP_CTRL_VLAN)
748 } else if (attr->ofs == 2) {
749 rtl8366_smi_read_reg(smi, RTL8366S_VLAN_TB_CTRL_REG, &data);
760 static int rtl8366s_sw_get_blinkrate(struct switch_dev *dev,
761 const struct switch_attr *attr,
762 struct switch_val *val)
764 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
767 rtl8366_smi_read_reg(smi, RTL8366S_LED_BLINKRATE_REG, &data);
769 val->value.i = (data & (RTL8366S_LED_BLINKRATE_MASK));
774 static int rtl8366s_sw_set_blinkrate(struct switch_dev *dev,
775 const struct switch_attr *attr,
776 struct switch_val *val)
778 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
780 if (val->value.i >= 6)
783 return rtl8366_smi_rmwr(smi, RTL8366S_LED_BLINKRATE_REG,
784 RTL8366S_LED_BLINKRATE_MASK,
788 static int rtl8366s_sw_set_vlan_enable(struct switch_dev *dev,
789 const struct switch_attr *attr,
790 struct switch_val *val)
792 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
795 return rtl8366s_vlan_set_vlan(smi, val->value.i);
797 return rtl8366s_vlan_set_4ktable(smi, val->value.i);
800 static const char *rtl8366s_speed_str(unsigned speed)
814 static int rtl8366s_sw_get_port_link(struct switch_dev *dev,
815 const struct switch_attr *attr,
816 struct switch_val *val)
818 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
819 u32 len = 0, data = 0;
821 if (val->port_vlan >= RTL8366S_NUM_PORTS)
824 memset(smi->buf, '\0', sizeof(smi->buf));
825 rtl8366_smi_read_reg(smi, RTL8366S_PORT_LINK_STATUS_BASE +
826 (val->port_vlan / 2), &data);
828 if (val->port_vlan % 2)
831 if (data & RTL8366S_PORT_STATUS_LINK_MASK) {
832 len = snprintf(smi->buf, sizeof(smi->buf),
833 "port:%d link:up speed:%s %s-duplex %s%s%s",
835 rtl8366s_speed_str(data &
836 RTL8366S_PORT_STATUS_SPEED_MASK),
837 (data & RTL8366S_PORT_STATUS_DUPLEX_MASK) ?
839 (data & RTL8366S_PORT_STATUS_TXPAUSE_MASK) ?
841 (data & RTL8366S_PORT_STATUS_RXPAUSE_MASK) ?
843 (data & RTL8366S_PORT_STATUS_AN_MASK) ?
846 len = snprintf(smi->buf, sizeof(smi->buf), "port:%d link: down",
850 val->value.s = smi->buf;
856 static int rtl8366s_sw_get_vlan_info(struct switch_dev *dev,
857 const struct switch_attr *attr,
858 struct switch_val *val)
862 struct rtl8366_vlan_4k vlan4k;
863 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
864 char *buf = smi->buf;
867 if (val->port_vlan == 0 || val->port_vlan >= RTL8366S_NUM_VLANS)
870 memset(buf, '\0', sizeof(smi->buf));
872 err = rtl8366s_get_vlan_4k(smi, val->port_vlan, &vlan4k);
876 len += snprintf(buf + len, sizeof(smi->buf) - len,
877 "VLAN %d: Ports: '", vlan4k.vid);
879 for (i = 0; i < RTL8366S_NUM_PORTS; i++) {
880 if (!(vlan4k.member & (1 << i)))
883 len += snprintf(buf + len, sizeof(smi->buf) - len, "%d%s", i,
884 (vlan4k.untag & (1 << i)) ? "" : "t");
887 len += snprintf(buf + len, sizeof(smi->buf) - len,
888 "', members=%04x, untag=%04x, fid=%u",
889 vlan4k.member, vlan4k.untag, vlan4k.fid);
897 static int rtl8366s_sw_set_port_led(struct switch_dev *dev,
898 const struct switch_attr *attr,
899 struct switch_val *val)
901 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
906 if (val->port_vlan >= RTL8366S_NUM_PORTS ||
907 (1 << val->port_vlan) == RTL8366S_PORT_UNKNOWN)
910 if (val->port_vlan == RTL8366S_PORT_NUM_CPU) {
911 reg = RTL8366S_LED_BLINKRATE_REG;
913 data = val->value.i << 4;
915 reg = RTL8366S_LED_CTRL_REG;
916 mask = 0xF << (val->port_vlan * 4),
917 data = val->value.i << (val->port_vlan * 4);
920 return rtl8366_smi_rmwr(smi, RTL8366S_LED_BLINKRATE_REG, mask, data);
923 static int rtl8366s_sw_get_port_led(struct switch_dev *dev,
924 const struct switch_attr *attr,
925 struct switch_val *val)
927 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
930 if (val->port_vlan >= RTL8366S_NUM_LEDGROUPS)
933 rtl8366_smi_read_reg(smi, RTL8366S_LED_CTRL_REG, &data);
934 val->value.i = (data >> (val->port_vlan * 4)) & 0x000F;
939 static int rtl8366s_sw_reset_port_mibs(struct switch_dev *dev,
940 const struct switch_attr *attr,
941 struct switch_val *val)
943 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
945 if (val->port_vlan >= RTL8366S_NUM_PORTS)
949 return rtl8366_smi_rmwr(smi, RTL8366S_MIB_CTRL_REG,
950 0, (1 << (val->port_vlan + 3)));
953 static int rtl8366s_sw_get_port_mib(struct switch_dev *dev,
954 const struct switch_attr *attr,
955 struct switch_val *val)
957 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
959 unsigned long long counter = 0;
960 char *buf = smi->buf;
962 if (val->port_vlan >= RTL8366S_NUM_PORTS)
965 len += snprintf(buf + len, sizeof(smi->buf) - len,
966 "Port %d MIB counters\n",
969 for (i = 0; i < ARRAY_SIZE(rtl8366s_mib_counters); ++i) {
970 len += snprintf(buf + len, sizeof(smi->buf) - len,
971 "%-36s: ", rtl8366s_mib_counters[i].name);
972 if (!rtl8366_get_mib_counter(smi, i, val->port_vlan, &counter))
973 len += snprintf(buf + len, sizeof(smi->buf) - len,
976 len += snprintf(buf + len, sizeof(smi->buf) - len,
985 static int rtl8366s_sw_get_vlan_ports(struct switch_dev *dev,
986 struct switch_val *val)
988 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
989 struct switch_port *port;
990 struct rtl8366_vlan_4k vlan4k;
993 if (val->port_vlan == 0 || val->port_vlan >= RTL8366S_NUM_VLANS)
996 rtl8366s_get_vlan_4k(smi, val->port_vlan, &vlan4k);
998 port = &val->value.ports[0];
1000 for (i = 0; i < RTL8366S_NUM_PORTS; i++) {
1001 if (!(vlan4k.member & BIT(i)))
1005 port->flags = (vlan4k.untag & BIT(i)) ?
1006 0 : BIT(SWITCH_PORT_FLAG_TAGGED);
1013 static int rtl8366s_sw_set_vlan_ports(struct switch_dev *dev,
1014 struct switch_val *val)
1016 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1017 struct switch_port *port;
1022 if (val->port_vlan == 0 || val->port_vlan >= RTL8366S_NUM_VLANS)
1025 port = &val->value.ports[0];
1026 for (i = 0; i < val->len; i++, port++) {
1027 member |= BIT(port->id);
1029 if (!(port->flags & BIT(SWITCH_PORT_FLAG_TAGGED)))
1030 untag |= BIT(port->id);
1033 return rtl8366_set_vlan(smi, val->port_vlan, member, untag, 0);
1036 static int rtl8366s_sw_get_port_pvid(struct switch_dev *dev, int port, int *val)
1038 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1039 return rtl8366_get_pvid(smi, port, val);
1042 static int rtl8366s_sw_set_port_pvid(struct switch_dev *dev, int port, int val)
1044 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1045 return rtl8366_set_pvid(smi, port, val);
1048 static int rtl8366s_sw_reset_switch(struct switch_dev *dev)
1050 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1053 err = rtl8366s_reset_chip(smi);
1057 err = rtl8366s_hw_init(smi);
1061 return rtl8366_reset_vlan(smi);
1064 static struct switch_attr rtl8366s_globals[] = {
1066 .type = SWITCH_TYPE_INT,
1067 .name = "enable_vlan",
1068 .description = "Enable VLAN mode",
1069 .set = rtl8366s_sw_set_vlan_enable,
1070 .get = rtl8366s_sw_get_vlan_enable,
1074 .type = SWITCH_TYPE_INT,
1075 .name = "enable_vlan4k",
1076 .description = "Enable VLAN 4K mode",
1077 .set = rtl8366s_sw_set_vlan_enable,
1078 .get = rtl8366s_sw_get_vlan_enable,
1082 .type = SWITCH_TYPE_INT,
1083 .name = "reset_mibs",
1084 .description = "Reset all MIB counters",
1085 .set = rtl8366s_sw_reset_mibs,
1089 .type = SWITCH_TYPE_INT,
1090 .name = "blinkrate",
1091 .description = "Get/Set LED blinking rate (0 = 43ms, 1 = 84ms,"
1092 " 2 = 120ms, 3 = 170ms, 4 = 340ms, 5 = 670ms)",
1093 .set = rtl8366s_sw_set_blinkrate,
1094 .get = rtl8366s_sw_get_blinkrate,
1099 static struct switch_attr rtl8366s_port[] = {
1101 .type = SWITCH_TYPE_STRING,
1103 .description = "Get port link information",
1106 .get = rtl8366s_sw_get_port_link,
1108 .type = SWITCH_TYPE_INT,
1109 .name = "reset_mib",
1110 .description = "Reset single port MIB counters",
1112 .set = rtl8366s_sw_reset_port_mibs,
1115 .type = SWITCH_TYPE_STRING,
1117 .description = "Get MIB counters for port",
1120 .get = rtl8366s_sw_get_port_mib,
1122 .type = SWITCH_TYPE_INT,
1124 .description = "Get/Set port group (0 - 3) led mode (0 - 15)",
1126 .set = rtl8366s_sw_set_port_led,
1127 .get = rtl8366s_sw_get_port_led,
1131 static struct switch_attr rtl8366s_vlan[] = {
1133 .type = SWITCH_TYPE_STRING,
1135 .description = "Get vlan information",
1138 .get = rtl8366s_sw_get_vlan_info,
1143 static struct switch_dev rtl8366_switch_dev = {
1145 .cpu_port = RTL8366S_PORT_NUM_CPU,
1146 .ports = RTL8366S_NUM_PORTS,
1147 .vlans = RTL8366S_NUM_VLANS,
1149 .attr = rtl8366s_globals,
1150 .n_attr = ARRAY_SIZE(rtl8366s_globals),
1153 .attr = rtl8366s_port,
1154 .n_attr = ARRAY_SIZE(rtl8366s_port),
1157 .attr = rtl8366s_vlan,
1158 .n_attr = ARRAY_SIZE(rtl8366s_vlan),
1161 .get_vlan_ports = rtl8366s_sw_get_vlan_ports,
1162 .set_vlan_ports = rtl8366s_sw_set_vlan_ports,
1163 .get_port_pvid = rtl8366s_sw_get_port_pvid,
1164 .set_port_pvid = rtl8366s_sw_set_port_pvid,
1165 .reset_switch = rtl8366s_sw_reset_switch,
1168 static int rtl8366s_switch_init(struct rtl8366s *rtl)
1170 struct switch_dev *dev = &rtl->dev;
1173 memcpy(dev, &rtl8366_switch_dev, sizeof(struct switch_dev));
1175 dev->devname = dev_name(rtl->parent);
1177 err = register_switch(dev, NULL);
1179 dev_err(rtl->parent, "switch registration failed\n");
1184 static void rtl8366s_switch_cleanup(struct rtl8366s *rtl)
1186 unregister_switch(&rtl->dev);
1189 static int rtl8366s_mii_read(struct mii_bus *bus, int addr, int reg)
1191 struct rtl8366_smi *smi = bus->priv;
1195 err = rtl8366s_read_phy_reg(smi, addr, 0, reg, &val);
1202 static int rtl8366s_mii_write(struct mii_bus *bus, int addr, int reg, u16 val)
1204 struct rtl8366_smi *smi = bus->priv;
1208 err = rtl8366s_write_phy_reg(smi, addr, 0, reg, val);
1210 (void) rtl8366s_read_phy_reg(smi, addr, 0, reg, &t);
1215 static int rtl8366s_mii_bus_match(struct mii_bus *bus)
1217 return (bus->read == rtl8366s_mii_read &&
1218 bus->write == rtl8366s_mii_write);
1221 static int rtl8366s_setup(struct rtl8366s *rtl)
1223 struct rtl8366_smi *smi = &rtl->smi;
1226 rtl8366s_debugfs_init(smi);
1228 ret = rtl8366s_reset_chip(smi);
1232 ret = rtl8366s_hw_init(smi);
1236 static int rtl8366s_detect(struct rtl8366_smi *smi)
1242 ret = rtl8366_smi_read_reg(smi, RTL8366S_CHIP_ID_REG, &chip_id);
1244 dev_err(smi->parent, "unable to read chip id\n");
1249 case RTL8366S_CHIP_ID_8366:
1252 dev_err(smi->parent, "unknown chip id (%04x)\n", chip_id);
1256 ret = rtl8366_smi_read_reg(smi, RTL8366S_CHIP_VERSION_CTRL_REG,
1259 dev_err(smi->parent, "unable to read chip version\n");
1263 dev_info(smi->parent, "RTL%04x ver. %u chip found\n",
1264 chip_id, chip_ver & RTL8366S_CHIP_VERSION_MASK);
1269 static struct rtl8366_smi_ops rtl8366s_smi_ops = {
1270 .detect = rtl8366s_detect,
1271 .mii_read = rtl8366s_mii_read,
1272 .mii_write = rtl8366s_mii_write,
1274 .get_vlan_mc = rtl8366s_get_vlan_mc,
1275 .set_vlan_mc = rtl8366s_set_vlan_mc,
1276 .get_vlan_4k = rtl8366s_get_vlan_4k,
1277 .set_vlan_4k = rtl8366s_set_vlan_4k,
1278 .get_mc_index = rtl8366s_get_mc_index,
1279 .set_mc_index = rtl8366s_set_mc_index,
1282 static int __init rtl8366s_probe(struct platform_device *pdev)
1284 static int rtl8366_smi_version_printed;
1285 struct rtl8366s_platform_data *pdata;
1286 struct rtl8366s *rtl;
1287 struct rtl8366_smi *smi;
1290 if (!rtl8366_smi_version_printed++)
1291 printk(KERN_NOTICE RTL8366S_DRIVER_DESC
1292 " version " RTL8366S_DRIVER_VER"\n");
1294 pdata = pdev->dev.platform_data;
1296 dev_err(&pdev->dev, "no platform data specified\n");
1301 rtl = kzalloc(sizeof(*rtl), GFP_KERNEL);
1303 dev_err(&pdev->dev, "no memory for private data\n");
1308 rtl->parent = &pdev->dev;
1311 smi->parent = &pdev->dev;
1312 smi->gpio_sda = pdata->gpio_sda;
1313 smi->gpio_sck = pdata->gpio_sck;
1314 smi->ops = &rtl8366s_smi_ops;
1315 smi->cpu_port = RTL8366S_PORT_NUM_CPU;
1316 smi->num_ports = RTL8366S_NUM_PORTS;
1317 smi->num_vlan_mc = RTL8366S_NUM_VLANS;
1319 err = rtl8366_smi_init(smi);
1323 platform_set_drvdata(pdev, rtl);
1325 err = rtl8366s_setup(rtl);
1327 goto err_clear_drvdata;
1329 err = rtl8366s_switch_init(rtl);
1331 goto err_clear_drvdata;
1336 platform_set_drvdata(pdev, NULL);
1337 rtl8366_smi_cleanup(smi);
1344 static int rtl8366s_phy_config_init(struct phy_device *phydev)
1346 if (!rtl8366s_mii_bus_match(phydev->bus))
1352 static int rtl8366s_phy_config_aneg(struct phy_device *phydev)
1357 static struct phy_driver rtl8366s_phy_driver = {
1358 .phy_id = 0x001cc960,
1359 .name = "Realtek RTL8366S",
1360 .phy_id_mask = 0x1ffffff0,
1361 .features = PHY_GBIT_FEATURES,
1362 .config_aneg = rtl8366s_phy_config_aneg,
1363 .config_init = rtl8366s_phy_config_init,
1364 .read_status = genphy_read_status,
1366 .owner = THIS_MODULE,
1370 static int __devexit rtl8366s_remove(struct platform_device *pdev)
1372 struct rtl8366s *rtl = platform_get_drvdata(pdev);
1375 rtl8366s_switch_cleanup(rtl);
1376 platform_set_drvdata(pdev, NULL);
1377 rtl8366_smi_cleanup(&rtl->smi);
1384 static struct platform_driver rtl8366s_driver = {
1386 .name = RTL8366S_DRIVER_NAME,
1387 .owner = THIS_MODULE,
1389 .probe = rtl8366s_probe,
1390 .remove = __devexit_p(rtl8366s_remove),
1393 static int __init rtl8366s_module_init(void)
1396 ret = platform_driver_register(&rtl8366s_driver);
1400 ret = phy_driver_register(&rtl8366s_phy_driver);
1402 goto err_platform_unregister;
1406 err_platform_unregister:
1407 platform_driver_unregister(&rtl8366s_driver);
1410 module_init(rtl8366s_module_init);
1412 static void __exit rtl8366s_module_exit(void)
1414 phy_driver_unregister(&rtl8366s_phy_driver);
1415 platform_driver_unregister(&rtl8366s_driver);
1417 module_exit(rtl8366s_module_exit);
1419 MODULE_DESCRIPTION(RTL8366S_DRIVER_DESC);
1420 MODULE_VERSION(RTL8366S_DRIVER_VER);
1421 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
1422 MODULE_AUTHOR("Antti Seppälä <a.seppala@gmail.com>");
1423 MODULE_LICENSE("GPL v2");
1424 MODULE_ALIAS("platform:" RTL8366S_DRIVER_NAME);