target/linux/generic/files/drivers/net/phy/rtl8366s.c

   1 /*
   2  * Platform driver for the Realtek RTL8366S ethernet switch
   3  *
   4  * Copyright (C) 2009-2010 Gabor Juhos <juhosg@openwrt.org>
   5  * Copyright (C) 2010 Antti Seppälä <a.seppala@gmail.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms of the GNU General Public License version 2 as published
   9  * by the Free Software Foundation.
  10  */
  11
  12 #include <linux/kernel.h>
  13 #include <linux/module.h>
  14 #include <linux/init.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/delay.h>
  17 #include <linux/skbuff.h>
  18 #include <linux/switch.h>
  19 #include <linux/rtl8366s.h>
  20
  21 #include "rtl8366_smi.h"
  22
  23 #define RTL8366S_DRIVER_DESC    "Realtek RTL8366S ethernet switch driver"
  24 #define RTL8366S_DRIVER_VER     "0.2.2"
  25
  26 #define RTL8366S_PHY_NO_MAX     4
  27 #define RTL8366S_PHY_PAGE_MAX   7
  28 #define RTL8366S_PHY_ADDR_MAX   31
  29
  30 /* Switch Global Configuration register */
  31 #define RTL8366S_SGCR                           0x0000
  32 #define RTL8366S_SGCR_EN_BC_STORM_CTRL          BIT(0)
  33 #define RTL8366S_SGCR_MAX_LENGTH(_x)            (_x << 4)
  34 #define RTL8366S_SGCR_MAX_LENGTH_MASK           RTL8366S_SGCR_MAX_LENGTH(0x3)
  35 #define RTL8366S_SGCR_MAX_LENGTH_1522           RTL8366S_SGCR_MAX_LENGTH(0x0)
  36 #define RTL8366S_SGCR_MAX_LENGTH_1536           RTL8366S_SGCR_MAX_LENGTH(0x1)
  37 #define RTL8366S_SGCR_MAX_LENGTH_1552           RTL8366S_SGCR_MAX_LENGTH(0x2)
  38 #define RTL8366S_SGCR_MAX_LENGTH_16000          RTL8366S_SGCR_MAX_LENGTH(0x3)
  39 #define RTL8366S_SGCR_EN_VLAN                   BIT(13)
  40
  41 /* Port Enable Control register */
  42 #define RTL8366S_PECR                           0x0001
  43
  44 /* Switch Security Control registers */
  45 #define RTL8366S_SSCR0                          0x0002
  46 #define RTL8366S_SSCR1                          0x0003
  47 #define RTL8366S_SSCR2                          0x0004
  48 #define RTL8366S_SSCR2_DROP_UNKNOWN_DA          BIT(0)
  49
  50 #define RTL8366S_RESET_CTRL_REG                 0x0100
  51 #define RTL8366S_CHIP_CTRL_RESET_HW             1
  52 #define RTL8366S_CHIP_CTRL_RESET_SW             (1 << 1)
  53
  54 #define RTL8366S_CHIP_VERSION_CTRL_REG          0x0104
  55 #define RTL8366S_CHIP_VERSION_MASK              0xf
  56 #define RTL8366S_CHIP_ID_REG                    0x0105
  57 #define RTL8366S_CHIP_ID_8366                   0x8366
  58
  59 /* PHY registers control */
  60 #define RTL8366S_PHY_ACCESS_CTRL_REG            0x8028
  61 #define RTL8366S_PHY_ACCESS_DATA_REG            0x8029
  62
  63 #define RTL8366S_PHY_CTRL_READ                  1
  64 #define RTL8366S_PHY_CTRL_WRITE                 0
  65
  66 #define RTL8366S_PHY_REG_MASK                   0x1f
  67 #define RTL8366S_PHY_PAGE_OFFSET                5
  68 #define RTL8366S_PHY_PAGE_MASK                  (0x7 << 5)
  69 #define RTL8366S_PHY_NO_OFFSET                  9
  70 #define RTL8366S_PHY_NO_MASK                    (0x1f << 9)
  71
  72 /* LED control registers */
  73 #define RTL8366S_LED_BLINKRATE_REG              0x0420
  74 #define RTL8366S_LED_BLINKRATE_BIT              0
  75 #define RTL8366S_LED_BLINKRATE_MASK             0x0007
  76
  77 #define RTL8366S_LED_CTRL_REG                   0x0421
  78 #define RTL8366S_LED_0_1_CTRL_REG               0x0422
  79 #define RTL8366S_LED_2_3_CTRL_REG               0x0423
  80
  81 #define RTL8366S_MIB_COUNT                      33
  82 #define RTL8366S_GLOBAL_MIB_COUNT               1
  83 #define RTL8366S_MIB_COUNTER_PORT_OFFSET        0x0040
  84 #define RTL8366S_MIB_COUNTER_BASE               0x1000
  85 #define RTL8366S_MIB_COUNTER_PORT_OFFSET2       0x0008
  86 #define RTL8366S_MIB_COUNTER_BASE2              0x1180
  87 #define RTL8366S_MIB_CTRL_REG                   0x11F0
  88 #define RTL8366S_MIB_CTRL_USER_MASK             0x01FF
  89 #define RTL8366S_MIB_CTRL_BUSY_MASK             0x0001
  90 #define RTL8366S_MIB_CTRL_RESET_MASK            0x0002
  91
  92 #define RTL8366S_MIB_CTRL_GLOBAL_RESET_MASK     0x0004
  93 #define RTL8366S_MIB_CTRL_PORT_RESET_BIT        0x0003
  94 #define RTL8366S_MIB_CTRL_PORT_RESET_MASK       0x01FC
  95
  96
  97 #define RTL8366S_PORT_VLAN_CTRL_BASE            0x0058
  98 #define RTL8366S_PORT_VLAN_CTRL_REG(_p)  \
  99                 (RTL8366S_PORT_VLAN_CTRL_BASE + (_p) / 4)
 100 #define RTL8366S_PORT_VLAN_CTRL_MASK            0xf
 101 #define RTL8366S_PORT_VLAN_CTRL_SHIFT(_p)       (4 * ((_p) % 4))
 102
 103
 104 #define RTL8366S_VLAN_TABLE_READ_BASE           0x018B
 105 #define RTL8366S_VLAN_TABLE_WRITE_BASE          0x0185
 106
 107 #define RTL8366S_VLAN_TB_CTRL_REG               0x010F
 108
 109 #define RTL8366S_TABLE_ACCESS_CTRL_REG          0x0180
 110 #define RTL8366S_TABLE_VLAN_READ_CTRL           0x0E01
 111 #define RTL8366S_TABLE_VLAN_WRITE_CTRL          0x0F01
 112
 113 #define RTL8366S_VLAN_MEMCONF_BASE              0x0016
 114
 115 #define RTL8366S_VLAN_MEMBERINGRESS_REG         0x0379
 116
 117 #define RTL8366S_PORT_LINK_STATUS_BASE          0x0060
 118 #define RTL8366S_PORT_STATUS_SPEED_MASK         0x0003
 119 #define RTL8366S_PORT_STATUS_DUPLEX_MASK        0x0004
 120 #define RTL8366S_PORT_STATUS_LINK_MASK          0x0010
 121 #define RTL8366S_PORT_STATUS_TXPAUSE_MASK       0x0020
 122 #define RTL8366S_PORT_STATUS_RXPAUSE_MASK       0x0040
 123 #define RTL8366S_PORT_STATUS_AN_MASK            0x0080
 124
 125
 126 #define RTL8366S_PORT_NUM_CPU           5
 127 #define RTL8366S_NUM_PORTS              6
 128 #define RTL8366S_NUM_VLANS              16
 129 #define RTL8366S_NUM_LEDGROUPS          4
 130 #define RTL8366S_NUM_VIDS               4096
 131 #define RTL8366S_PRIORITYMAX            7
 132 #define RTL8366S_FIDMAX                 7
 133
 134
 135 #define RTL8366S_PORT_1                 (1 << 0) /* In userspace port 0 */
 136 #define RTL8366S_PORT_2                 (1 << 1) /* In userspace port 1 */
 137 #define RTL8366S_PORT_3                 (1 << 2) /* In userspace port 2 */
 138 #define RTL8366S_PORT_4                 (1 << 3) /* In userspace port 3 */
 139
 140 #define RTL8366S_PORT_UNKNOWN           (1 << 4) /* No known connection */
 141 #define RTL8366S_PORT_CPU               (1 << 5) /* CPU port */
 142
 143 #define RTL8366S_PORT_ALL               (RTL8366S_PORT_1 |      \
 144                                          RTL8366S_PORT_2 |      \
 145                                          RTL8366S_PORT_3 |      \
 146                                          RTL8366S_PORT_4 |      \
 147                                          RTL8366S_PORT_UNKNOWN | \
 148                                          RTL8366S_PORT_CPU)
 149
 150 #define RTL8366S_PORT_ALL_BUT_CPU       (RTL8366S_PORT_1 |      \
 151                                          RTL8366S_PORT_2 |      \
 152                                          RTL8366S_PORT_3 |      \
 153                                          RTL8366S_PORT_4 |      \
 154                                          RTL8366S_PORT_UNKNOWN)
 155
 156 #define RTL8366S_PORT_ALL_EXTERNAL      (RTL8366S_PORT_1 |      \
 157                                          RTL8366S_PORT_2 |      \
 158                                          RTL8366S_PORT_3 |      \
 159                                          RTL8366S_PORT_4)
 160
 161 #define RTL8366S_PORT_ALL_INTERNAL      (RTL8366S_PORT_UNKNOWN | \
 162                                          RTL8366S_PORT_CPU)
 163
 164 struct rtl8366s {
 165         struct device           *parent;
 166         struct rtl8366_smi      smi;
 167         struct switch_dev       dev;
 168 };
 169
 170 struct rtl8366s_vlan_mc {
 171         u16     reserved2:1;
 172         u16     priority:3;
 173         u16     vid:12;
 174
 175         u16     reserved1:1;
 176         u16     fid:3;
 177         u16     untag:6;
 178         u16     member:6;
 179 };
 180
 181 struct rtl8366s_vlan_4k {
 182         u16     reserved1:4;
 183         u16     vid:12;
 184
 185         u16     reserved2:1;
 186         u16     fid:3;
 187         u16     untag:6;
 188         u16     member:6;
 189 };
 190
 191 static struct rtl8366_mib_counter rtl8366s_mib_counters[] = {
 192         { 0,  0, 4, "IfInOctets"                                },
 193         { 0,  4, 4, "EtherStatsOctets"                          },
 194         { 0,  8, 2, "EtherStatsUnderSizePkts"                   },
 195         { 0, 10, 2, "EtherFragments"                            },
 196         { 0, 12, 2, "EtherStatsPkts64Octets"                    },
 197         { 0, 14, 2, "EtherStatsPkts65to127Octets"               },
 198         { 0, 16, 2, "EtherStatsPkts128to255Octets"              },
 199         { 0, 18, 2, "EtherStatsPkts256to511Octets"              },
 200         { 0, 20, 2, "EtherStatsPkts512to1023Octets"             },
 201         { 0, 22, 2, "EtherStatsPkts1024to1518Octets"            },
 202         { 0, 24, 2, "EtherOversizeStats"                        },
 203         { 0, 26, 2, "EtherStatsJabbers"                         },
 204         { 0, 28, 2, "IfInUcastPkts"                             },
 205         { 0, 30, 2, "EtherStatsMulticastPkts"                   },
 206         { 0, 32, 2, "EtherStatsBroadcastPkts"                   },
 207         { 0, 34, 2, "EtherStatsDropEvents"                      },
 208         { 0, 36, 2, "Dot3StatsFCSErrors"                        },
 209         { 0, 38, 2, "Dot3StatsSymbolErrors"                     },
 210         { 0, 40, 2, "Dot3InPauseFrames"                         },
 211         { 0, 42, 2, "Dot3ControlInUnknownOpcodes"               },
 212         { 0, 44, 4, "IfOutOctets"                               },
 213         { 0, 48, 2, "Dot3StatsSingleCollisionFrames"            },
 214         { 0, 50, 2, "Dot3StatMultipleCollisionFrames"           },
 215         { 0, 52, 2, "Dot3sDeferredTransmissions"                },
 216         { 0, 54, 2, "Dot3StatsLateCollisions"                   },
 217         { 0, 56, 2, "EtherStatsCollisions"                      },
 218         { 0, 58, 2, "Dot3StatsExcessiveCollisions"              },
 219         { 0, 60, 2, "Dot3OutPauseFrames"                        },
 220         { 0, 62, 2, "Dot1dBasePortDelayExceededDiscards"        },
 221
 222         /*
 223          * The following counters are accessible at a different
 224          * base address.
 225          */
 226         { 1,  0, 2, "Dot1dTpPortInDiscards"                     },
 227         { 1,  2, 2, "IfOutUcastPkts"                            },
 228         { 1,  4, 2, "IfOutMulticastPkts"                        },
 229         { 1,  6, 2, "IfOutBroadcastPkts"                        },
 230 };
 231
 232 #define REG_WR(_smi, _reg, _val)                                        \
 233         do {                                                            \
 234                 err = rtl8366_smi_write_reg(_smi, _reg, _val);          \
 235                 if (err)                                                \
 236                         return err;                                     \
 237         } while (0)
 238
 239 #define REG_RMW(_smi, _reg, _mask, _val)                                \
 240         do {                                                            \
 241                 err = rtl8366_smi_rmwr(_smi, _reg, _mask, _val);        \
 242                 if (err)                                                \
 243                         return err;                                     \
 244         } while (0)
 245
 246 static inline struct rtl8366s *smi_to_rtl8366s(struct rtl8366_smi *smi)
 247 {
 248         return container_of(smi, struct rtl8366s, smi);
 249 }
 250
 251 static inline struct rtl8366s *sw_to_rtl8366s(struct switch_dev *sw)
 252 {
 253         return container_of(sw, struct rtl8366s, dev);
 254 }
 255
 256 static inline struct rtl8366_smi *sw_to_rtl8366_smi(struct switch_dev *sw)
 257 {
 258         struct rtl8366s *rtl = sw_to_rtl8366s(sw);
 259         return &rtl->smi;
 260 }
 261
 262 static int rtl8366s_reset_chip(struct rtl8366_smi *smi)
 263 {
 264         int timeout = 10;
 265         u32 data;
 266
 267         rtl8366_smi_write_reg(smi, RTL8366S_RESET_CTRL_REG,
 268                               RTL8366S_CHIP_CTRL_RESET_HW);
 269         do {
 270                 msleep(1);
 271                 if (rtl8366_smi_read_reg(smi, RTL8366S_RESET_CTRL_REG, &data))
 272                         return -EIO;
 273
 274                 if (!(data & RTL8366S_CHIP_CTRL_RESET_HW))
 275                         break;
 276         } while (--timeout);
 277
 278         if (!timeout) {
 279                 printk("Timeout waiting for the switch to reset\n");
 280                 return -EIO;
 281         }
 282
 283         return 0;
 284 }
 285
 286 static int rtl8366s_hw_init(struct rtl8366_smi *smi)
 287 {
 288         int err;
 289
 290         /* set maximum packet length to 1536 bytes */
 291         REG_RMW(smi, RTL8366S_SGCR, RTL8366S_SGCR_MAX_LENGTH_MASK,
 292                 RTL8366S_SGCR_MAX_LENGTH_1536);
 293
 294         /* enable all ports */
 295         REG_WR(smi, RTL8366S_PECR, 0);
 296
 297         /* disable learning for all ports */
 298         REG_WR(smi, RTL8366S_SSCR0, RTL8366S_PORT_ALL);
 299
 300         /* disable auto ageing for all ports */
 301         REG_WR(smi, RTL8366S_SSCR1, RTL8366S_PORT_ALL);
 302
 303         /*
 304          * discard VLAN tagged packets if the port is not a member of
 305          * the VLAN with which the packets is associated.
 306          */
 307         REG_WR(smi, RTL8366S_VLAN_MEMBERINGRESS_REG, RTL8366S_PORT_ALL);
 308
 309         /* don't drop packets whose DA has not been learned */
 310         REG_RMW(smi, RTL8366S_SSCR2, RTL8366S_SSCR2_DROP_UNKNOWN_DA, 0);
 311
 312         return 0;
 313 }
 314
 315 static int rtl8366s_read_phy_reg(struct rtl8366_smi *smi,
 316                                  u32 phy_no, u32 page, u32 addr, u32 *data)
 317 {
 318         u32 reg;
 319         int ret;
 320
 321         if (phy_no > RTL8366S_PHY_NO_MAX)
 322                 return -EINVAL;
 323
 324         if (page > RTL8366S_PHY_PAGE_MAX)
 325                 return -EINVAL;
 326
 327         if (addr > RTL8366S_PHY_ADDR_MAX)
 328                 return -EINVAL;
 329
 330         ret = rtl8366_smi_write_reg(smi, RTL8366S_PHY_ACCESS_CTRL_REG,
 331                                     RTL8366S_PHY_CTRL_READ);
 332         if (ret)
 333                 return ret;
 334
 335         reg = 0x8000 | (1 << (phy_no + RTL8366S_PHY_NO_OFFSET)) |
 336               ((page << RTL8366S_PHY_PAGE_OFFSET) & RTL8366S_PHY_PAGE_MASK) |
 337               (addr & RTL8366S_PHY_REG_MASK);
 338
 339         ret = rtl8366_smi_write_reg(smi, reg, 0);
 340         if (ret)
 341                 return ret;
 342
 343         ret = rtl8366_smi_read_reg(smi, RTL8366S_PHY_ACCESS_DATA_REG, data);
 344         if (ret)
 345                 return ret;
 346
 347         return 0;
 348 }
 349
 350 static int rtl8366s_write_phy_reg(struct rtl8366_smi *smi,
 351                                   u32 phy_no, u32 page, u32 addr, u32 data)
 352 {
 353         u32 reg;
 354         int ret;
 355
 356         if (phy_no > RTL8366S_PHY_NO_MAX)
 357                 return -EINVAL;
 358
 359         if (page > RTL8366S_PHY_PAGE_MAX)
 360                 return -EINVAL;
 361
 362         if (addr > RTL8366S_PHY_ADDR_MAX)
 363                 return -EINVAL;
 364
 365         ret = rtl8366_smi_write_reg(smi, RTL8366S_PHY_ACCESS_CTRL_REG,
 366                                     RTL8366S_PHY_CTRL_WRITE);
 367         if (ret)
 368                 return ret;
 369
 370         reg = 0x8000 | (1 << (phy_no + RTL8366S_PHY_NO_OFFSET)) |
 371               ((page << RTL8366S_PHY_PAGE_OFFSET) & RTL8366S_PHY_PAGE_MASK) |
 372               (addr & RTL8366S_PHY_REG_MASK);
 373
 374         ret = rtl8366_smi_write_reg(smi, reg, data);
 375         if (ret)
 376                 return ret;
 377
 378         return 0;
 379 }
 380
 381 static int rtl8366_get_mib_counter(struct rtl8366_smi *smi, int counter,
 382                                    int port, unsigned long long *val)
 383 {
 384         int i;
 385         int err;
 386         u32 addr, data;
 387         u64 mibvalue;
 388
 389         if (port > RTL8366S_NUM_PORTS || counter >= RTL8366S_MIB_COUNT)
 390                 return -EINVAL;
 391
 392         switch (rtl8366s_mib_counters[counter].base) {
 393         case 0:
 394                 addr = RTL8366S_MIB_COUNTER_BASE +
 395                        RTL8366S_MIB_COUNTER_PORT_OFFSET * port;
 396                 break;
 397
 398         case 1:
 399                 addr = RTL8366S_MIB_COUNTER_BASE2 +
 400                         RTL8366S_MIB_COUNTER_PORT_OFFSET2 * port;
 401                 break;
 402
 403         default:
 404                 return -EINVAL;
 405         }
 406
 407         addr += rtl8366s_mib_counters[counter].offset;
 408
 409         /*
 410          * Writing access counter address first
 411          * then ASIC will prepare 64bits counter wait for being retrived
 412          */
 413         data = 0; /* writing data will be discard by ASIC */
 414         err = rtl8366_smi_write_reg(smi, addr, data);
 415         if (err)
 416                 return err;
 417
 418         /* read MIB control register */
 419         err =  rtl8366_smi_read_reg(smi, RTL8366S_MIB_CTRL_REG, &data);
 420         if (err)
 421                 return err;
 422
 423         if (data & RTL8366S_MIB_CTRL_BUSY_MASK)
 424                 return -EBUSY;
 425
 426         if (data & RTL8366S_MIB_CTRL_RESET_MASK)
 427                 return -EIO;
 428
 429         mibvalue = 0;
 430         for (i = rtl8366s_mib_counters[counter].length; i > 0; i--) {
 431                 err = rtl8366_smi_read_reg(smi, addr + (i - 1), &data);
 432                 if (err)
 433                         return err;
 434
 435                 mibvalue = (mibvalue << 16) | (data & 0xFFFF);
 436         }
 437
 438         *val = mibvalue;
 439         return 0;
 440 }
 441
 442 static int rtl8366s_get_vlan_4k(struct rtl8366_smi *smi, u32 vid,
 443                                 struct rtl8366_vlan_4k *vlan4k)
 444 {
 445         struct rtl8366s_vlan_4k vlan4k_priv;
 446         int err;
 447         u32 data;
 448         u16 *tableaddr;
 449
 450         memset(vlan4k, '\0', sizeof(struct rtl8366_vlan_4k));
 451         vlan4k_priv.vid = vid;
 452
 453         if (vid >= RTL8366S_NUM_VIDS)
 454                 return -EINVAL;
 455
 456         tableaddr = (u16 *)&vlan4k_priv;
 457
 458         /* write VID */
 459         data = *tableaddr;
 460         err = rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TABLE_WRITE_BASE, data);
 461         if (err)
 462                 return err;
 463
 464         /* write table access control word */
 465         err = rtl8366_smi_write_reg(smi, RTL8366S_TABLE_ACCESS_CTRL_REG,
 466                                     RTL8366S_TABLE_VLAN_READ_CTRL);
 467         if (err)
 468                 return err;
 469
 470         err = rtl8366_smi_read_reg(smi, RTL8366S_VLAN_TABLE_READ_BASE, &data);
 471         if (err)
 472                 return err;
 473
 474         *tableaddr = data;
 475         tableaddr++;
 476
 477         err = rtl8366_smi_read_reg(smi, RTL8366S_VLAN_TABLE_READ_BASE + 1,
 478                                    &data);
 479         if (err)
 480                 return err;
 481
 482         *tableaddr = data;
 483
 484         vlan4k->vid = vid;
 485         vlan4k->untag = vlan4k_priv.untag;
 486         vlan4k->member = vlan4k_priv.member;
 487         vlan4k->fid = vlan4k_priv.fid;
 488
 489         return 0;
 490 }
 491
 492 static int rtl8366s_set_vlan_4k(struct rtl8366_smi *smi,
 493                                 const struct rtl8366_vlan_4k *vlan4k)
 494 {
 495         struct rtl8366s_vlan_4k vlan4k_priv;
 496         int err;
 497         u32 data;
 498         u16 *tableaddr;
 499
 500         if (vlan4k->vid >= RTL8366S_NUM_VIDS ||
 501             vlan4k->member > RTL8366S_PORT_ALL ||
 502             vlan4k->untag > RTL8366S_PORT_ALL ||
 503             vlan4k->fid > RTL8366S_FIDMAX)
 504                 return -EINVAL;
 505
 506         vlan4k_priv.vid = vlan4k->vid;
 507         vlan4k_priv.untag = vlan4k->untag;
 508         vlan4k_priv.member = vlan4k->member;
 509         vlan4k_priv.fid = vlan4k->fid;
 510
 511         tableaddr = (u16 *)&vlan4k_priv;
 512
 513         data = *tableaddr;
 514
 515         err = rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TABLE_WRITE_BASE, data);
 516         if (err)
 517                 return err;
 518
 519         tableaddr++;
 520
 521         data = *tableaddr;
 522
 523         err = rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TABLE_WRITE_BASE + 1,
 524                                     data);
 525         if (err)
 526                 return err;
 527
 528         /* write table access control word */
 529         err = rtl8366_smi_write_reg(smi, RTL8366S_TABLE_ACCESS_CTRL_REG,
 530                                     RTL8366S_TABLE_VLAN_WRITE_CTRL);
 531
 532         return err;
 533 }
 534
 535 static int rtl8366s_get_vlan_mc(struct rtl8366_smi *smi, u32 index,
 536                                 struct rtl8366_vlan_mc *vlanmc)
 537 {
 538         struct rtl8366s_vlan_mc vlanmc_priv;
 539         int err;
 540         u32 addr;
 541         u32 data;
 542         u16 *tableaddr;
 543
 544         memset(vlanmc, '\0', sizeof(struct rtl8366_vlan_mc));
 545
 546         if (index >= RTL8366S_NUM_VLANS)
 547                 return -EINVAL;
 548
 549         tableaddr = (u16 *)&vlanmc_priv;
 550
 551         addr = RTL8366S_VLAN_MEMCONF_BASE + (index << 1);
 552         err = rtl8366_smi_read_reg(smi, addr, &data);
 553         if (err)
 554                 return err;
 555
 556         *tableaddr = data;
 557         tableaddr++;
 558
 559         addr = RTL8366S_VLAN_MEMCONF_BASE + 1 + (index << 1);
 560         err = rtl8366_smi_read_reg(smi, addr, &data);
 561         if (err)
 562                 return err;
 563
 564         *tableaddr = data;
 565
 566         vlanmc->vid = vlanmc_priv.vid;
 567         vlanmc->priority = vlanmc_priv.priority;
 568         vlanmc->untag = vlanmc_priv.untag;
 569         vlanmc->member = vlanmc_priv.member;
 570         vlanmc->fid = vlanmc_priv.fid;
 571
 572         return 0;
 573 }
 574
 575 static int rtl8366s_set_vlan_mc(struct rtl8366_smi *smi, u32 index,
 576                                 const struct rtl8366_vlan_mc *vlanmc)
 577 {
 578         struct rtl8366s_vlan_mc vlanmc_priv;
 579         int err;
 580         u32 addr;
 581         u32 data;
 582         u16 *tableaddr;
 583
 584         if (index >= RTL8366S_NUM_VLANS ||
 585             vlanmc->vid >= RTL8366S_NUM_VIDS ||
 586             vlanmc->priority > RTL8366S_PRIORITYMAX ||
 587             vlanmc->member > RTL8366S_PORT_ALL ||
 588             vlanmc->untag > RTL8366S_PORT_ALL ||
 589             vlanmc->fid > RTL8366S_FIDMAX)
 590                 return -EINVAL;
 591
 592         vlanmc_priv.vid = vlanmc->vid;
 593         vlanmc_priv.priority = vlanmc->priority;
 594         vlanmc_priv.untag = vlanmc->untag;
 595         vlanmc_priv.member = vlanmc->member;
 596         vlanmc_priv.fid = vlanmc->fid;
 597
 598         addr = RTL8366S_VLAN_MEMCONF_BASE + (index << 1);
 599
 600         tableaddr = (u16 *)&vlanmc_priv;
 601         data = *tableaddr;
 602
 603         err = rtl8366_smi_write_reg(smi, addr, data);
 604         if (err)
 605                 return err;
 606
 607         addr = RTL8366S_VLAN_MEMCONF_BASE + 1 + (index << 1);
 608
 609         tableaddr++;
 610         data = *tableaddr;
 611
 612         err = rtl8366_smi_write_reg(smi, addr, data);
 613         if (err)
 614                 return err;
 615
 616         return 0;
 617 }
 618
 619 static int rtl8366s_get_mc_index(struct rtl8366_smi *smi, int port, int *val)
 620 {
 621         u32 data;
 622         int err;
 623
 624         if (port >= RTL8366S_NUM_PORTS)
 625                 return -EINVAL;
 626
 627         err = rtl8366_smi_read_reg(smi, RTL8366S_PORT_VLAN_CTRL_REG(port),
 628                                    &data);
 629         if (err)
 630                 return err;
 631
 632         *val = (data >> RTL8366S_PORT_VLAN_CTRL_SHIFT(port)) &
 633                RTL8366S_PORT_VLAN_CTRL_MASK;
 634
 635         return 0;
 636 }
 637
 638 static int rtl8366s_set_mc_index(struct rtl8366_smi *smi, int port, int index)
 639 {
 640         if (port >= RTL8366S_NUM_PORTS || index >= RTL8366S_NUM_VLANS)
 641                 return -EINVAL;
 642
 643         return rtl8366_smi_rmwr(smi, RTL8366S_PORT_VLAN_CTRL_REG(port),
 644                                 RTL8366S_PORT_VLAN_CTRL_MASK <<
 645                                         RTL8366S_PORT_VLAN_CTRL_SHIFT(port),
 646                                 (index & RTL8366S_PORT_VLAN_CTRL_MASK) <<
 647                                         RTL8366S_PORT_VLAN_CTRL_SHIFT(port));
 648 }
 649
 650 static int rtl8366s_vlan_set_vlan(struct rtl8366_smi *smi, int enable)
 651 {
 652         return rtl8366_smi_rmwr(smi, RTL8366S_SGCR, RTL8366S_SGCR_EN_VLAN,
 653                                 (enable) ? RTL8366S_SGCR_EN_VLAN : 0);
 654 }
 655
 656 static int rtl8366s_vlan_set_4ktable(struct rtl8366_smi *smi, int enable)
 657 {
 658         return rtl8366_smi_rmwr(smi, RTL8366S_VLAN_TB_CTRL_REG,
 659                                 1, (enable) ? 1 : 0);
 660 }
 661
 662 static int rtl8366s_sw_reset_mibs(struct switch_dev *dev,
 663                                   const struct switch_attr *attr,
 664                                   struct switch_val *val)
 665 {
 666         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 667
 668         return rtl8366_smi_rmwr(smi, RTL8366S_MIB_CTRL_REG, 0, (1 << 2));
 669 }
 670
 671 static int rtl8366s_sw_get_vlan_enable(struct switch_dev *dev,
 672                                        const struct switch_attr *attr,
 673                                        struct switch_val *val)
 674 {
 675         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 676         u32 data;
 677
 678         if (attr->ofs == 1) {
 679                 rtl8366_smi_read_reg(smi, RTL8366S_SGCR, &data);
 680
 681                 if (data & RTL8366S_SGCR_EN_VLAN)
 682                         val->value.i = 1;
 683                 else
 684                         val->value.i = 0;
 685         } else if (attr->ofs == 2) {
 686                 rtl8366_smi_read_reg(smi, RTL8366S_VLAN_TB_CTRL_REG, &data);
 687
 688                 if (data & 0x0001)
 689                         val->value.i = 1;
 690                 else
 691                         val->value.i = 0;
 692         }
 693
 694         return 0;
 695 }
 696
 697 static int rtl8366s_sw_get_blinkrate(struct switch_dev *dev,
 698                                      const struct switch_attr *attr,
 699                                      struct switch_val *val)
 700 {
 701         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 702         u32 data;
 703
 704         rtl8366_smi_read_reg(smi, RTL8366S_LED_BLINKRATE_REG, &data);
 705
 706         val->value.i = (data & (RTL8366S_LED_BLINKRATE_MASK));
 707
 708         return 0;
 709 }
 710
 711 static int rtl8366s_sw_set_blinkrate(struct switch_dev *dev,
 712                                     const struct switch_attr *attr,
 713                                     struct switch_val *val)
 714 {
 715         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 716
 717         if (val->value.i >= 6)
 718                 return -EINVAL;
 719
 720         return rtl8366_smi_rmwr(smi, RTL8366S_LED_BLINKRATE_REG,
 721                                 RTL8366S_LED_BLINKRATE_MASK,
 722                                 val->value.i);
 723 }
 724
 725 static int rtl8366s_sw_set_vlan_enable(struct switch_dev *dev,
 726                                        const struct switch_attr *attr,
 727                                        struct switch_val *val)
 728 {
 729         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 730
 731         if (attr->ofs == 1)
 732                 return rtl8366s_vlan_set_vlan(smi, val->value.i);
 733         else
 734                 return rtl8366s_vlan_set_4ktable(smi, val->value.i);
 735 }
 736
 737 static const char *rtl8366s_speed_str(unsigned speed)
 738 {
 739         switch (speed) {
 740         case 0:
 741                 return "10baseT";
 742         case 1:
 743                 return "100baseT";
 744         case 2:
 745                 return "1000baseT";
 746         }
 747
 748         return "unknown";
 749 }
 750
 751 static int rtl8366s_sw_get_port_link(struct switch_dev *dev,
 752                                      const struct switch_attr *attr,
 753                                      struct switch_val *val)
 754 {
 755         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 756         u32 len = 0, data = 0;
 757
 758         if (val->port_vlan >= RTL8366S_NUM_PORTS)
 759                 return -EINVAL;
 760
 761         memset(smi->buf, '\0', sizeof(smi->buf));
 762         rtl8366_smi_read_reg(smi, RTL8366S_PORT_LINK_STATUS_BASE +
 763                              (val->port_vlan / 2), &data);
 764
 765         if (val->port_vlan % 2)
 766                 data = data >> 8;
 767
 768         if (data & RTL8366S_PORT_STATUS_LINK_MASK) {
 769                 len = snprintf(smi->buf, sizeof(smi->buf),
 770                                 "port:%d link:up speed:%s %s-duplex %s%s%s",
 771                                 val->port_vlan,
 772                                 rtl8366s_speed_str(data &
 773                                           RTL8366S_PORT_STATUS_SPEED_MASK),
 774                                 (data & RTL8366S_PORT_STATUS_DUPLEX_MASK) ?
 775                                         "full" : "half",
 776                                 (data & RTL8366S_PORT_STATUS_TXPAUSE_MASK) ?
 777                                         "tx-pause ": "",
 778                                 (data & RTL8366S_PORT_STATUS_RXPAUSE_MASK) ?
 779                                         "rx-pause " : "",
 780                                 (data & RTL8366S_PORT_STATUS_AN_MASK) ?
 781                                         "nway ": "");
 782         } else {
 783                 len = snprintf(smi->buf, sizeof(smi->buf), "port:%d link: down",
 784                                 val->port_vlan);
 785         }
 786
 787         val->value.s = smi->buf;
 788         val->len = len;
 789
 790         return 0;
 791 }
 792
 793 static int rtl8366s_sw_get_vlan_info(struct switch_dev *dev,
 794                                      const struct switch_attr *attr,
 795                                      struct switch_val *val)
 796 {
 797         int i;
 798         u32 len = 0;
 799         struct rtl8366_vlan_4k vlan4k;
 800         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 801         char *buf = smi->buf;
 802         int err;
 803
 804         if (val->port_vlan == 0 || val->port_vlan >= RTL8366S_NUM_VLANS)
 805                 return -EINVAL;
 806
 807         memset(buf, '\0', sizeof(smi->buf));
 808
 809         err = rtl8366s_get_vlan_4k(smi, val->port_vlan, &vlan4k);
 810         if (err)
 811                 return err;
 812
 813         len += snprintf(buf + len, sizeof(smi->buf) - len,
 814                         "VLAN %d: Ports: '", vlan4k.vid);
 815
 816         for (i = 0; i < RTL8366S_NUM_PORTS; i++) {
 817                 if (!(vlan4k.member & (1 << i)))
 818                         continue;
 819
 820                 len += snprintf(buf + len, sizeof(smi->buf) - len, "%d%s", i,
 821                                 (vlan4k.untag & (1 << i)) ? "" : "t");
 822         }
 823
 824         len += snprintf(buf + len, sizeof(smi->buf) - len,
 825                         "', members=%04x, untag=%04x, fid=%u",
 826                         vlan4k.member, vlan4k.untag, vlan4k.fid);
 827
 828         val->value.s = buf;
 829         val->len = len;
 830
 831         return 0;
 832 }
 833
 834 static int rtl8366s_sw_set_port_led(struct switch_dev *dev,
 835                                     const struct switch_attr *attr,
 836                                     struct switch_val *val)
 837 {
 838         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 839         u32 data;
 840         u32 mask;
 841         u32 reg;
 842
 843         if (val->port_vlan >= RTL8366S_NUM_PORTS ||
 844             (1 << val->port_vlan) == RTL8366S_PORT_UNKNOWN)
 845                 return -EINVAL;
 846
 847         if (val->port_vlan == RTL8366S_PORT_NUM_CPU) {
 848                 reg = RTL8366S_LED_BLINKRATE_REG;
 849                 mask = 0xF << 4;
 850                 data = val->value.i << 4;
 851         } else {
 852                 reg = RTL8366S_LED_CTRL_REG;
 853                 mask = 0xF << (val->port_vlan * 4),
 854                 data = val->value.i << (val->port_vlan * 4);
 855         }
 856
 857         return rtl8366_smi_rmwr(smi, RTL8366S_LED_BLINKRATE_REG, mask, data);
 858 }
 859
 860 static int rtl8366s_sw_get_port_led(struct switch_dev *dev,
 861                                     const struct switch_attr *attr,
 862                                     struct switch_val *val)
 863 {
 864         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 865         u32 data = 0;
 866
 867         if (val->port_vlan >= RTL8366S_NUM_LEDGROUPS)
 868                 return -EINVAL;
 869
 870         rtl8366_smi_read_reg(smi, RTL8366S_LED_CTRL_REG, &data);
 871         val->value.i = (data >> (val->port_vlan * 4)) & 0x000F;
 872
 873         return 0;
 874 }
 875
 876 static int rtl8366s_sw_reset_port_mibs(struct switch_dev *dev,
 877                                        const struct switch_attr *attr,
 878                                        struct switch_val *val)
 879 {
 880         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 881
 882         if (val->port_vlan >= RTL8366S_NUM_PORTS)
 883                 return -EINVAL;
 884
 885
 886         return rtl8366_smi_rmwr(smi, RTL8366S_MIB_CTRL_REG,
 887                                 0, (1 << (val->port_vlan + 3)));
 888 }
 889
 890 static int rtl8366s_sw_get_port_mib(struct switch_dev *dev,
 891                                     const struct switch_attr *attr,
 892                                     struct switch_val *val)
 893 {
 894         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 895         int i, len = 0;
 896         unsigned long long counter = 0;
 897         char *buf = smi->buf;
 898
 899         if (val->port_vlan >= RTL8366S_NUM_PORTS)
 900                 return -EINVAL;
 901
 902         len += snprintf(buf + len, sizeof(smi->buf) - len,
 903                         "Port %d MIB counters\n",
 904                         val->port_vlan);
 905
 906         for (i = 0; i < ARRAY_SIZE(rtl8366s_mib_counters); ++i) {
 907                 len += snprintf(buf + len, sizeof(smi->buf) - len,
 908                                 "%-36s: ", rtl8366s_mib_counters[i].name);
 909                 if (!rtl8366_get_mib_counter(smi, i, val->port_vlan, &counter))
 910                         len += snprintf(buf + len, sizeof(smi->buf) - len,
 911                                         "%llu\n", counter);
 912                 else
 913                         len += snprintf(buf + len, sizeof(smi->buf) - len,
 914                                         "%s\n", "error");
 915         }
 916
 917         val->value.s = buf;
 918         val->len = len;
 919         return 0;
 920 }
 921
 922 static int rtl8366s_sw_get_vlan_ports(struct switch_dev *dev,
 923                                       struct switch_val *val)
 924 {
 925         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 926         struct switch_port *port;
 927         struct rtl8366_vlan_4k vlan4k;
 928         int i;
 929
 930         if (val->port_vlan == 0 || val->port_vlan >= RTL8366S_NUM_VLANS)
 931                 return -EINVAL;
 932
 933         rtl8366s_get_vlan_4k(smi, val->port_vlan, &vlan4k);
 934
 935         port = &val->value.ports[0];
 936         val->len = 0;
 937         for (i = 0; i < RTL8366S_NUM_PORTS; i++) {
 938                 if (!(vlan4k.member & BIT(i)))
 939                         continue;
 940
 941                 port->id = i;
 942                 port->flags = (vlan4k.untag & BIT(i)) ?
 943                                         0 : BIT(SWITCH_PORT_FLAG_TAGGED);
 944                 val->len++;
 945                 port++;
 946         }
 947         return 0;
 948 }
 949
 950 static int rtl8366s_sw_set_vlan_ports(struct switch_dev *dev,
 951                                       struct switch_val *val)
 952 {
 953         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 954         struct switch_port *port;
 955         u32 member = 0;
 956         u32 untag = 0;
 957         int i;
 958
 959         if (val->port_vlan == 0 || val->port_vlan >= RTL8366S_NUM_VLANS)
 960                 return -EINVAL;
 961
 962         port = &val->value.ports[0];
 963         for (i = 0; i < val->len; i++, port++) {
 964                 member |= BIT(port->id);
 965
 966                 if (!(port->flags & BIT(SWITCH_PORT_FLAG_TAGGED)))
 967                         untag |= BIT(port->id);
 968         }
 969
 970         return rtl8366_set_vlan(smi, val->port_vlan, member, untag, 0);
 971 }
 972
 973 static int rtl8366s_sw_get_port_pvid(struct switch_dev *dev, int port, int *val)
 974 {
 975         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 976         return rtl8366_get_pvid(smi, port, val);
 977 }
 978
 979 static int rtl8366s_sw_set_port_pvid(struct switch_dev *dev, int port, int val)
 980 {
 981         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 982         return rtl8366_set_pvid(smi, port, val);
 983 }
 984
 985 static int rtl8366s_sw_reset_switch(struct switch_dev *dev)
 986 {
 987         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 988         int err;
 989
 990         err = rtl8366s_reset_chip(smi);
 991         if (err)
 992                 return err;
 993
 994         err = rtl8366s_hw_init(smi);
 995         if (err)
 996                 return err;
 997
 998         return rtl8366_reset_vlan(smi);
 999 }
1000
1001 static struct switch_attr rtl8366s_globals[] = {
1002         {
1003                 .type = SWITCH_TYPE_INT,
1004                 .name = "enable_vlan",
1005                 .description = "Enable VLAN mode",
1006                 .set = rtl8366s_sw_set_vlan_enable,
1007                 .get = rtl8366s_sw_get_vlan_enable,
1008                 .max = 1,
1009                 .ofs = 1
1010         }, {
1011                 .type = SWITCH_TYPE_INT,
1012                 .name = "enable_vlan4k",
1013                 .description = "Enable VLAN 4K mode",
1014                 .set = rtl8366s_sw_set_vlan_enable,
1015                 .get = rtl8366s_sw_get_vlan_enable,
1016                 .max = 1,
1017                 .ofs = 2
1018         }, {
1019                 .type = SWITCH_TYPE_NOVAL,
1020                 .name = "reset_mibs",
1021                 .description = "Reset all MIB counters",
1022                 .set = rtl8366s_sw_reset_mibs,
1023         }, {
1024                 .type = SWITCH_TYPE_INT,
1025                 .name = "blinkrate",
1026                 .description = "Get/Set LED blinking rate (0 = 43ms, 1 = 84ms,"
1027                 " 2 = 120ms, 3 = 170ms, 4 = 340ms, 5 = 670ms)",
1028                 .set = rtl8366s_sw_set_blinkrate,
1029                 .get = rtl8366s_sw_get_blinkrate,
1030                 .max = 5
1031         },
1032 };
1033
1034 static struct switch_attr rtl8366s_port[] = {
1035         {
1036                 .type = SWITCH_TYPE_STRING,
1037                 .name = "link",
1038                 .description = "Get port link information",
1039                 .max = 1,
1040                 .set = NULL,
1041                 .get = rtl8366s_sw_get_port_link,
1042         }, {
1043                 .type = SWITCH_TYPE_NOVAL,
1044                 .name = "reset_mib",
1045                 .description = "Reset single port MIB counters",
1046                 .set = rtl8366s_sw_reset_port_mibs,
1047         }, {
1048                 .type = SWITCH_TYPE_STRING,
1049                 .name = "mib",
1050                 .description = "Get MIB counters for port",
1051                 .max = 33,
1052                 .set = NULL,
1053                 .get = rtl8366s_sw_get_port_mib,
1054         }, {
1055                 .type = SWITCH_TYPE_INT,
1056                 .name = "led",
1057                 .description = "Get/Set port group (0 - 3) led mode (0 - 15)",
1058                 .max = 15,
1059                 .set = rtl8366s_sw_set_port_led,
1060                 .get = rtl8366s_sw_get_port_led,
1061         },
1062 };
1063
1064 static struct switch_attr rtl8366s_vlan[] = {
1065         {
1066                 .type = SWITCH_TYPE_STRING,
1067                 .name = "info",
1068                 .description = "Get vlan information",
1069                 .max = 1,
1070                 .set = NULL,
1071                 .get = rtl8366s_sw_get_vlan_info,
1072         },
1073 };
1074
1075 /* template */
1076 static struct switch_dev rtl8366_switch_dev = {
1077         .name = "RTL8366S",
1078         .cpu_port = RTL8366S_PORT_NUM_CPU,
1079         .ports = RTL8366S_NUM_PORTS,
1080         .vlans = RTL8366S_NUM_VLANS,
1081         .attr_global = {
1082                 .attr = rtl8366s_globals,
1083                 .n_attr = ARRAY_SIZE(rtl8366s_globals),
1084         },
1085         .attr_port = {
1086                 .attr = rtl8366s_port,
1087                 .n_attr = ARRAY_SIZE(rtl8366s_port),
1088         },
1089         .attr_vlan = {
1090                 .attr = rtl8366s_vlan,
1091                 .n_attr = ARRAY_SIZE(rtl8366s_vlan),
1092         },
1093
1094         .get_vlan_ports = rtl8366s_sw_get_vlan_ports,
1095         .set_vlan_ports = rtl8366s_sw_set_vlan_ports,
1096         .get_port_pvid = rtl8366s_sw_get_port_pvid,
1097         .set_port_pvid = rtl8366s_sw_set_port_pvid,
1098         .reset_switch = rtl8366s_sw_reset_switch,
1099 };
1100
1101 static int rtl8366s_switch_init(struct rtl8366s *rtl)
1102 {
1103         struct switch_dev *dev = &rtl->dev;
1104         int err;
1105
1106         memcpy(dev, &rtl8366_switch_dev, sizeof(struct switch_dev));
1107         dev->priv = rtl;
1108         dev->devname = dev_name(rtl->parent);
1109
1110         err = register_switch(dev, NULL);
1111         if (err)
1112                 dev_err(rtl->parent, "switch registration failed\n");
1113
1114         return err;
1115 }
1116
1117 static void rtl8366s_switch_cleanup(struct rtl8366s *rtl)
1118 {
1119         unregister_switch(&rtl->dev);
1120 }
1121
1122 static int rtl8366s_mii_read(struct mii_bus *bus, int addr, int reg)
1123 {
1124         struct rtl8366_smi *smi = bus->priv;
1125         u32 val = 0;
1126         int err;
1127
1128         err = rtl8366s_read_phy_reg(smi, addr, 0, reg, &val);
1129         if (err)
1130                 return 0xffff;
1131
1132         return val;
1133 }
1134
1135 static int rtl8366s_mii_write(struct mii_bus *bus, int addr, int reg, u16 val)
1136 {
1137         struct rtl8366_smi *smi = bus->priv;
1138         u32 t;
1139         int err;
1140
1141         err = rtl8366s_write_phy_reg(smi, addr, 0, reg, val);
1142         /* flush write */
1143         (void) rtl8366s_read_phy_reg(smi, addr, 0, reg, &t);
1144
1145         return err;
1146 }
1147
1148 static int rtl8366s_mii_bus_match(struct mii_bus *bus)
1149 {
1150         return (bus->read == rtl8366s_mii_read &&
1151                 bus->write == rtl8366s_mii_write);
1152 }
1153
1154 static int rtl8366s_setup(struct rtl8366s *rtl)
1155 {
1156         struct rtl8366_smi *smi = &rtl->smi;
1157         int ret;
1158
1159         ret = rtl8366s_reset_chip(smi);
1160         if (ret)
1161                 return ret;
1162
1163         ret = rtl8366s_hw_init(smi);
1164         return ret;
1165 }
1166
1167 static int rtl8366s_detect(struct rtl8366_smi *smi)
1168 {
1169         u32 chip_id = 0;
1170         u32 chip_ver = 0;
1171         int ret;
1172
1173         ret = rtl8366_smi_read_reg(smi, RTL8366S_CHIP_ID_REG, &chip_id);
1174         if (ret) {
1175                 dev_err(smi->parent, "unable to read chip id\n");
1176                 return ret;
1177         }
1178
1179         switch (chip_id) {
1180         case RTL8366S_CHIP_ID_8366:
1181                 break;
1182         default:
1183                 dev_err(smi->parent, "unknown chip id (%04x)\n", chip_id);
1184                 return -ENODEV;
1185         }
1186
1187         ret = rtl8366_smi_read_reg(smi, RTL8366S_CHIP_VERSION_CTRL_REG,
1188                                    &chip_ver);
1189         if (ret) {
1190                 dev_err(smi->parent, "unable to read chip version\n");
1191                 return ret;
1192         }
1193
1194         dev_info(smi->parent, "RTL%04x ver. %u chip found\n",
1195                  chip_id, chip_ver & RTL8366S_CHIP_VERSION_MASK);
1196
1197         return 0;
1198 }
1199
1200 static struct rtl8366_smi_ops rtl8366s_smi_ops = {
1201         .detect         = rtl8366s_detect,
1202         .mii_read       = rtl8366s_mii_read,
1203         .mii_write      = rtl8366s_mii_write,
1204
1205         .get_vlan_mc    = rtl8366s_get_vlan_mc,
1206         .set_vlan_mc    = rtl8366s_set_vlan_mc,
1207         .get_vlan_4k    = rtl8366s_get_vlan_4k,
1208         .set_vlan_4k    = rtl8366s_set_vlan_4k,
1209         .get_mc_index   = rtl8366s_get_mc_index,
1210         .set_mc_index   = rtl8366s_set_mc_index,
1211         .get_mib_counter = rtl8366_get_mib_counter,
1212 };
1213
1214 static int __init rtl8366s_probe(struct platform_device *pdev)
1215 {
1216         static int rtl8366_smi_version_printed;
1217         struct rtl8366s_platform_data *pdata;
1218         struct rtl8366s *rtl;
1219         struct rtl8366_smi *smi;
1220         int err;
1221
1222         if (!rtl8366_smi_version_printed++)
1223                 printk(KERN_NOTICE RTL8366S_DRIVER_DESC
1224                        " version " RTL8366S_DRIVER_VER"\n");
1225
1226         pdata = pdev->dev.platform_data;
1227         if (!pdata) {
1228                 dev_err(&pdev->dev, "no platform data specified\n");
1229                 err = -EINVAL;
1230                 goto err_out;
1231         }
1232
1233         rtl = kzalloc(sizeof(*rtl), GFP_KERNEL);
1234         if (!rtl) {
1235                 dev_err(&pdev->dev, "no memory for private data\n");
1236                 err = -ENOMEM;
1237                 goto err_out;
1238         }
1239
1240         rtl->parent = &pdev->dev;
1241
1242         smi = &rtl->smi;
1243         smi->parent = &pdev->dev;
1244         smi->gpio_sda = pdata->gpio_sda;
1245         smi->gpio_sck = pdata->gpio_sck;
1246         smi->ops = &rtl8366s_smi_ops;
1247         smi->cpu_port = RTL8366S_PORT_NUM_CPU;
1248         smi->num_ports = RTL8366S_NUM_PORTS;
1249         smi->num_vlan_mc = RTL8366S_NUM_VLANS;
1250         smi->mib_counters = rtl8366s_mib_counters;
1251         smi->num_mib_counters = ARRAY_SIZE(rtl8366s_mib_counters);
1252
1253         err = rtl8366_smi_init(smi);
1254         if (err)
1255                 goto err_free_rtl;
1256
1257         platform_set_drvdata(pdev, rtl);
1258
1259         err = rtl8366s_setup(rtl);
1260         if (err)
1261                 goto err_clear_drvdata;
1262
1263         err = rtl8366s_switch_init(rtl);
1264         if (err)
1265                 goto err_clear_drvdata;
1266
1267         return 0;
1268
1269  err_clear_drvdata:
1270         platform_set_drvdata(pdev, NULL);
1271         rtl8366_smi_cleanup(smi);
1272  err_free_rtl:
1273         kfree(rtl);
1274  err_out:
1275         return err;
1276 }
1277
1278 static int rtl8366s_phy_config_init(struct phy_device *phydev)
1279 {
1280         if (!rtl8366s_mii_bus_match(phydev->bus))
1281                 return -EINVAL;
1282
1283         return 0;
1284 }
1285
1286 static int rtl8366s_phy_config_aneg(struct phy_device *phydev)
1287 {
1288         return 0;
1289 }
1290
1291 static struct phy_driver rtl8366s_phy_driver = {
1292         .phy_id         = 0x001cc960,
1293         .name           = "Realtek RTL8366S",
1294         .phy_id_mask    = 0x1ffffff0,
1295         .features       = PHY_GBIT_FEATURES,
1296         .config_aneg    = rtl8366s_phy_config_aneg,
1297         .config_init    = rtl8366s_phy_config_init,
1298         .read_status    = genphy_read_status,
1299         .driver         = {
1300                 .owner = THIS_MODULE,
1301         },
1302 };
1303
1304 static int __devexit rtl8366s_remove(struct platform_device *pdev)
1305 {
1306         struct rtl8366s *rtl = platform_get_drvdata(pdev);
1307
1308         if (rtl) {
1309                 rtl8366s_switch_cleanup(rtl);
1310                 platform_set_drvdata(pdev, NULL);
1311                 rtl8366_smi_cleanup(&rtl->smi);
1312                 kfree(rtl);
1313         }
1314
1315         return 0;
1316 }
1317
1318 static struct platform_driver rtl8366s_driver = {
1319         .driver = {
1320                 .name           = RTL8366S_DRIVER_NAME,
1321                 .owner          = THIS_MODULE,
1322         },
1323         .probe          = rtl8366s_probe,
1324         .remove         = __devexit_p(rtl8366s_remove),
1325 };
1326
1327 static int __init rtl8366s_module_init(void)
1328 {
1329         int ret;
1330         ret = platform_driver_register(&rtl8366s_driver);
1331         if (ret)
1332                 return ret;
1333
1334         ret = phy_driver_register(&rtl8366s_phy_driver);
1335         if (ret)
1336                 goto err_platform_unregister;
1337
1338         return 0;
1339
1340  err_platform_unregister:
1341         platform_driver_unregister(&rtl8366s_driver);
1342         return ret;
1343 }
1344 module_init(rtl8366s_module_init);
1345
1346 static void __exit rtl8366s_module_exit(void)
1347 {
1348         phy_driver_unregister(&rtl8366s_phy_driver);
1349         platform_driver_unregister(&rtl8366s_driver);
1350 }
1351 module_exit(rtl8366s_module_exit);
1352
1353 MODULE_DESCRIPTION(RTL8366S_DRIVER_DESC);
1354 MODULE_VERSION(RTL8366S_DRIVER_VER);
1355 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
1356 MODULE_AUTHOR("Antti Seppälä <a.seppala@gmail.com>");
1357 MODULE_LICENSE("GPL v2");
1358 MODULE_ALIAS("platform:" RTL8366S_DRIVER_NAME);