target/linux/generic/files/drivers/net/phy/rtl8366s.c

   1 /*
   2  * Platform driver for the Realtek RTL8366S ethernet switch
   3  *
   4  * Copyright (C) 2009-2010 Gabor Juhos <juhosg@openwrt.org>
   5  * Copyright (C) 2010 Antti Seppälä <a.seppala@gmail.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms of the GNU General Public License version 2 as published
   9  * by the Free Software Foundation.
  10  */
  11
  12 #include <linux/kernel.h>
  13 #include <linux/module.h>
  14 #include <linux/init.h>
  15 #include <linux/device.h>
  16 #include <linux/of.h>
  17 #include <linux/of_platform.h>
  18 #include <linux/delay.h>
  19 #include <linux/skbuff.h>
  20 #include <linux/rtl8366.h>
  21
  22 #include "rtl8366_smi.h"
  23
  24 #define RTL8366S_DRIVER_DESC    "Realtek RTL8366S ethernet switch driver"
  25 #define RTL8366S_DRIVER_VER     "0.2.2"
  26
  27 #define RTL8366S_PHY_NO_MAX     4
  28 #define RTL8366S_PHY_PAGE_MAX   7
  29 #define RTL8366S_PHY_ADDR_MAX   31
  30
  31 /* Switch Global Configuration register */
  32 #define RTL8366S_SGCR                           0x0000
  33 #define RTL8366S_SGCR_EN_BC_STORM_CTRL          BIT(0)
  34 #define RTL8366S_SGCR_MAX_LENGTH(_x)            (_x << 4)
  35 #define RTL8366S_SGCR_MAX_LENGTH_MASK           RTL8366S_SGCR_MAX_LENGTH(0x3)
  36 #define RTL8366S_SGCR_MAX_LENGTH_1522           RTL8366S_SGCR_MAX_LENGTH(0x0)
  37 #define RTL8366S_SGCR_MAX_LENGTH_1536           RTL8366S_SGCR_MAX_LENGTH(0x1)
  38 #define RTL8366S_SGCR_MAX_LENGTH_1552           RTL8366S_SGCR_MAX_LENGTH(0x2)
  39 #define RTL8366S_SGCR_MAX_LENGTH_16000          RTL8366S_SGCR_MAX_LENGTH(0x3)
  40 #define RTL8366S_SGCR_EN_VLAN                   BIT(13)
  41
  42 /* Port Enable Control register */
  43 #define RTL8366S_PECR                           0x0001
  44
  45 /* Switch Security Control registers */
  46 #define RTL8366S_SSCR0                          0x0002
  47 #define RTL8366S_SSCR1                          0x0003
  48 #define RTL8366S_SSCR2                          0x0004
  49 #define RTL8366S_SSCR2_DROP_UNKNOWN_DA          BIT(0)
  50
  51 #define RTL8366S_RESET_CTRL_REG                 0x0100
  52 #define RTL8366S_CHIP_CTRL_RESET_HW             1
  53 #define RTL8366S_CHIP_CTRL_RESET_SW             (1 << 1)
  54
  55 #define RTL8366S_CHIP_VERSION_CTRL_REG          0x0104
  56 #define RTL8366S_CHIP_VERSION_MASK              0xf
  57 #define RTL8366S_CHIP_ID_REG                    0x0105
  58 #define RTL8366S_CHIP_ID_8366                   0x8366
  59
  60 /* PHY registers control */
  61 #define RTL8366S_PHY_ACCESS_CTRL_REG            0x8028
  62 #define RTL8366S_PHY_ACCESS_DATA_REG            0x8029
  63
  64 #define RTL8366S_PHY_CTRL_READ                  1
  65 #define RTL8366S_PHY_CTRL_WRITE                 0
  66
  67 #define RTL8366S_PHY_REG_MASK                   0x1f
  68 #define RTL8366S_PHY_PAGE_OFFSET                5
  69 #define RTL8366S_PHY_PAGE_MASK                  (0x7 << 5)
  70 #define RTL8366S_PHY_NO_OFFSET                  9
  71 #define RTL8366S_PHY_NO_MASK                    (0x1f << 9)
  72
  73 /* LED control registers */
  74 #define RTL8366S_LED_BLINKRATE_REG              0x0420
  75 #define RTL8366S_LED_BLINKRATE_BIT              0
  76 #define RTL8366S_LED_BLINKRATE_MASK             0x0007
  77
  78 #define RTL8366S_LED_CTRL_REG                   0x0421
  79 #define RTL8366S_LED_0_1_CTRL_REG               0x0422
  80 #define RTL8366S_LED_2_3_CTRL_REG               0x0423
  81
  82 #define RTL8366S_MIB_COUNT                      33
  83 #define RTL8366S_GLOBAL_MIB_COUNT               1
  84 #define RTL8366S_MIB_COUNTER_PORT_OFFSET        0x0040
  85 #define RTL8366S_MIB_COUNTER_BASE               0x1000
  86 #define RTL8366S_MIB_COUNTER_PORT_OFFSET2       0x0008
  87 #define RTL8366S_MIB_COUNTER_BASE2              0x1180
  88 #define RTL8366S_MIB_CTRL_REG                   0x11F0
  89 #define RTL8366S_MIB_CTRL_USER_MASK             0x01FF
  90 #define RTL8366S_MIB_CTRL_BUSY_MASK             0x0001
  91 #define RTL8366S_MIB_CTRL_RESET_MASK            0x0002
  92
  93 #define RTL8366S_MIB_CTRL_GLOBAL_RESET_MASK     0x0004
  94 #define RTL8366S_MIB_CTRL_PORT_RESET_BIT        0x0003
  95 #define RTL8366S_MIB_CTRL_PORT_RESET_MASK       0x01FC
  96
  97
  98 #define RTL8366S_PORT_VLAN_CTRL_BASE            0x0058
  99 #define RTL8366S_PORT_VLAN_CTRL_REG(_p)  \
 100                 (RTL8366S_PORT_VLAN_CTRL_BASE + (_p) / 4)
 101 #define RTL8366S_PORT_VLAN_CTRL_MASK            0xf
 102 #define RTL8366S_PORT_VLAN_CTRL_SHIFT(_p)       (4 * ((_p) % 4))
 103
 104
 105 #define RTL8366S_VLAN_TABLE_READ_BASE           0x018B
 106 #define RTL8366S_VLAN_TABLE_WRITE_BASE          0x0185
 107
 108 #define RTL8366S_VLAN_TB_CTRL_REG               0x010F
 109
 110 #define RTL8366S_TABLE_ACCESS_CTRL_REG          0x0180
 111 #define RTL8366S_TABLE_VLAN_READ_CTRL           0x0E01
 112 #define RTL8366S_TABLE_VLAN_WRITE_CTRL          0x0F01
 113
 114 #define RTL8366S_VLAN_MC_BASE(_x)               (0x0016 + (_x) * 2)
 115
 116 #define RTL8366S_VLAN_MEMBERINGRESS_REG         0x0379
 117
 118 #define RTL8366S_PORT_LINK_STATUS_BASE          0x0060
 119 #define RTL8366S_PORT_STATUS_SPEED_MASK         0x0003
 120 #define RTL8366S_PORT_STATUS_DUPLEX_MASK        0x0004
 121 #define RTL8366S_PORT_STATUS_LINK_MASK          0x0010
 122 #define RTL8366S_PORT_STATUS_TXPAUSE_MASK       0x0020
 123 #define RTL8366S_PORT_STATUS_RXPAUSE_MASK       0x0040
 124 #define RTL8366S_PORT_STATUS_AN_MASK            0x0080
 125
 126
 127 #define RTL8366S_PORT_NUM_CPU           5
 128 #define RTL8366S_NUM_PORTS              6
 129 #define RTL8366S_NUM_VLANS              16
 130 #define RTL8366S_NUM_LEDGROUPS          4
 131 #define RTL8366S_NUM_VIDS               4096
 132 #define RTL8366S_PRIORITYMAX            7
 133 #define RTL8366S_FIDMAX                 7
 134
 135
 136 #define RTL8366S_PORT_1                 (1 << 0) /* In userspace port 0 */
 137 #define RTL8366S_PORT_2                 (1 << 1) /* In userspace port 1 */
 138 #define RTL8366S_PORT_3                 (1 << 2) /* In userspace port 2 */
 139 #define RTL8366S_PORT_4                 (1 << 3) /* In userspace port 3 */
 140
 141 #define RTL8366S_PORT_UNKNOWN           (1 << 4) /* No known connection */
 142 #define RTL8366S_PORT_CPU               (1 << 5) /* CPU port */
 143
 144 #define RTL8366S_PORT_ALL               (RTL8366S_PORT_1 |      \
 145                                          RTL8366S_PORT_2 |      \
 146                                          RTL8366S_PORT_3 |      \
 147                                          RTL8366S_PORT_4 |      \
 148                                          RTL8366S_PORT_UNKNOWN | \
 149                                          RTL8366S_PORT_CPU)
 150
 151 #define RTL8366S_PORT_ALL_BUT_CPU       (RTL8366S_PORT_1 |      \
 152                                          RTL8366S_PORT_2 |      \
 153                                          RTL8366S_PORT_3 |      \
 154                                          RTL8366S_PORT_4 |      \
 155                                          RTL8366S_PORT_UNKNOWN)
 156
 157 #define RTL8366S_PORT_ALL_EXTERNAL      (RTL8366S_PORT_1 |      \
 158                                          RTL8366S_PORT_2 |      \
 159                                          RTL8366S_PORT_3 |      \
 160                                          RTL8366S_PORT_4)
 161
 162 #define RTL8366S_PORT_ALL_INTERNAL      (RTL8366S_PORT_UNKNOWN | \
 163                                          RTL8366S_PORT_CPU)
 164
 165 #define RTL8366S_VLAN_VID_MASK          0xfff
 166 #define RTL8366S_VLAN_PRIORITY_SHIFT    12
 167 #define RTL8366S_VLAN_PRIORITY_MASK     0x7
 168 #define RTL8366S_VLAN_MEMBER_MASK       0x3f
 169 #define RTL8366S_VLAN_UNTAG_SHIFT       6
 170 #define RTL8366S_VLAN_UNTAG_MASK        0x3f
 171 #define RTL8366S_VLAN_FID_SHIFT         12
 172 #define RTL8366S_VLAN_FID_MASK          0x7
 173
 174 static struct rtl8366_mib_counter rtl8366s_mib_counters[] = {
 175         { 0,  0, 4, "IfInOctets"                                },
 176         { 0,  4, 4, "EtherStatsOctets"                          },
 177         { 0,  8, 2, "EtherStatsUnderSizePkts"                   },
 178         { 0, 10, 2, "EtherFragments"                            },
 179         { 0, 12, 2, "EtherStatsPkts64Octets"                    },
 180         { 0, 14, 2, "EtherStatsPkts65to127Octets"               },
 181         { 0, 16, 2, "EtherStatsPkts128to255Octets"              },
 182         { 0, 18, 2, "EtherStatsPkts256to511Octets"              },
 183         { 0, 20, 2, "EtherStatsPkts512to1023Octets"             },
 184         { 0, 22, 2, "EtherStatsPkts1024to1518Octets"            },
 185         { 0, 24, 2, "EtherOversizeStats"                        },
 186         { 0, 26, 2, "EtherStatsJabbers"                         },
 187         { 0, 28, 2, "IfInUcastPkts"                             },
 188         { 0, 30, 2, "EtherStatsMulticastPkts"                   },
 189         { 0, 32, 2, "EtherStatsBroadcastPkts"                   },
 190         { 0, 34, 2, "EtherStatsDropEvents"                      },
 191         { 0, 36, 2, "Dot3StatsFCSErrors"                        },
 192         { 0, 38, 2, "Dot3StatsSymbolErrors"                     },
 193         { 0, 40, 2, "Dot3InPauseFrames"                         },
 194         { 0, 42, 2, "Dot3ControlInUnknownOpcodes"               },
 195         { 0, 44, 4, "IfOutOctets"                               },
 196         { 0, 48, 2, "Dot3StatsSingleCollisionFrames"            },
 197         { 0, 50, 2, "Dot3StatMultipleCollisionFrames"           },
 198         { 0, 52, 2, "Dot3sDeferredTransmissions"                },
 199         { 0, 54, 2, "Dot3StatsLateCollisions"                   },
 200         { 0, 56, 2, "EtherStatsCollisions"                      },
 201         { 0, 58, 2, "Dot3StatsExcessiveCollisions"              },
 202         { 0, 60, 2, "Dot3OutPauseFrames"                        },
 203         { 0, 62, 2, "Dot1dBasePortDelayExceededDiscards"        },
 204
 205         /*
 206          * The following counters are accessible at a different
 207          * base address.
 208          */
 209         { 1,  0, 2, "Dot1dTpPortInDiscards"                     },
 210         { 1,  2, 2, "IfOutUcastPkts"                            },
 211         { 1,  4, 2, "IfOutMulticastPkts"                        },
 212         { 1,  6, 2, "IfOutBroadcastPkts"                        },
 213 };
 214
 215 #define REG_WR(_smi, _reg, _val)                                        \
 216         do {                                                            \
 217                 err = rtl8366_smi_write_reg(_smi, _reg, _val);          \
 218                 if (err)                                                \
 219                         return err;                                     \
 220         } while (0)
 221
 222 #define REG_RMW(_smi, _reg, _mask, _val)                                \
 223         do {                                                            \
 224                 err = rtl8366_smi_rmwr(_smi, _reg, _mask, _val);        \
 225                 if (err)                                                \
 226                         return err;                                     \
 227         } while (0)
 228
 229 static int rtl8366s_reset_chip(struct rtl8366_smi *smi)
 230 {
 231         int timeout = 10;
 232         u32 data;
 233
 234         rtl8366_smi_write_reg_noack(smi, RTL8366S_RESET_CTRL_REG,
 235                                     RTL8366S_CHIP_CTRL_RESET_HW);
 236         do {
 237                 msleep(1);
 238                 if (rtl8366_smi_read_reg(smi, RTL8366S_RESET_CTRL_REG, &data))
 239                         return -EIO;
 240
 241                 if (!(data & RTL8366S_CHIP_CTRL_RESET_HW))
 242                         break;
 243         } while (--timeout);
 244
 245         if (!timeout) {
 246                 printk("Timeout waiting for the switch to reset\n");
 247                 return -EIO;
 248         }
 249
 250         return 0;
 251 }
 252
 253 static int rtl8366s_setup(struct rtl8366_smi *smi)
 254 {
 255         struct rtl8366_platform_data *pdata;
 256         int err;
 257         unsigned i;
 258 #ifdef CONFIG_OF
 259         struct device_node *np;
 260         unsigned num_initvals;
 261         const __be32 *paddr;
 262 #endif
 263
 264         pdata = smi->parent->platform_data;
 265         if (pdata && pdata->num_initvals && pdata->initvals) {
 266                 dev_info(smi->parent, "applying initvals\n");
 267                 for (i = 0; i < pdata->num_initvals; i++)
 268                         REG_WR(smi, pdata->initvals[i].reg,
 269                                pdata->initvals[i].val);
 270         }
 271
 272 #ifdef CONFIG_OF
 273         np = smi->parent->of_node;
 274
 275         paddr = of_get_property(np, "realtek,initvals", &num_initvals);
 276         if (paddr) {
 277                 dev_info(smi->parent, "applying initvals from DTS\n");
 278
 279                 if (num_initvals < (2 * sizeof(*paddr)))
 280                         return -EINVAL;
 281
 282                 num_initvals /= sizeof(*paddr);
 283
 284                 for (i = 0; i < num_initvals - 1; i += 2) {
 285                         u32 reg = be32_to_cpup(paddr + i);
 286                         u32 val = be32_to_cpup(paddr + i + 1);
 287
 288                         REG_WR(smi, reg, val);
 289                 }
 290         }
 291 #endif
 292
 293         /* set maximum packet length to 1536 bytes */
 294         REG_RMW(smi, RTL8366S_SGCR, RTL8366S_SGCR_MAX_LENGTH_MASK,
 295                 RTL8366S_SGCR_MAX_LENGTH_1536);
 296
 297         /* enable learning for all ports */
 298         REG_WR(smi, RTL8366S_SSCR0, 0);
 299
 300         /* enable auto ageing for all ports */
 301         REG_WR(smi, RTL8366S_SSCR1, 0);
 302
 303         /*
 304          * discard VLAN tagged packets if the port is not a member of
 305          * the VLAN with which the packets is associated.
 306          */
 307         REG_WR(smi, RTL8366S_VLAN_MEMBERINGRESS_REG, RTL8366S_PORT_ALL);
 308
 309         /* don't drop packets whose DA has not been learned */
 310         REG_RMW(smi, RTL8366S_SSCR2, RTL8366S_SSCR2_DROP_UNKNOWN_DA, 0);
 311
 312         return 0;
 313 }
 314
 315 static int rtl8366s_read_phy_reg(struct rtl8366_smi *smi,
 316                                  u32 phy_no, u32 page, u32 addr, u32 *data)
 317 {
 318         u32 reg;
 319         int ret;
 320
 321         if (phy_no > RTL8366S_PHY_NO_MAX)
 322                 return -EINVAL;
 323
 324         if (page > RTL8366S_PHY_PAGE_MAX)
 325                 return -EINVAL;
 326
 327         if (addr > RTL8366S_PHY_ADDR_MAX)
 328                 return -EINVAL;
 329
 330         ret = rtl8366_smi_write_reg(smi, RTL8366S_PHY_ACCESS_CTRL_REG,
 331                                     RTL8366S_PHY_CTRL_READ);
 332         if (ret)
 333                 return ret;
 334
 335         reg = 0x8000 | (1 << (phy_no + RTL8366S_PHY_NO_OFFSET)) |
 336               ((page << RTL8366S_PHY_PAGE_OFFSET) & RTL8366S_PHY_PAGE_MASK) |
 337               (addr & RTL8366S_PHY_REG_MASK);
 338
 339         ret = rtl8366_smi_write_reg(smi, reg, 0);
 340         if (ret)
 341                 return ret;
 342
 343         ret = rtl8366_smi_read_reg(smi, RTL8366S_PHY_ACCESS_DATA_REG, data);
 344         if (ret)
 345                 return ret;
 346
 347         return 0;
 348 }
 349
 350 static int rtl8366s_write_phy_reg(struct rtl8366_smi *smi,
 351                                   u32 phy_no, u32 page, u32 addr, u32 data)
 352 {
 353         u32 reg;
 354         int ret;
 355
 356         if (phy_no > RTL8366S_PHY_NO_MAX)
 357                 return -EINVAL;
 358
 359         if (page > RTL8366S_PHY_PAGE_MAX)
 360                 return -EINVAL;
 361
 362         if (addr > RTL8366S_PHY_ADDR_MAX)
 363                 return -EINVAL;
 364
 365         ret = rtl8366_smi_write_reg(smi, RTL8366S_PHY_ACCESS_CTRL_REG,
 366                                     RTL8366S_PHY_CTRL_WRITE);
 367         if (ret)
 368                 return ret;
 369
 370         reg = 0x8000 | (1 << (phy_no + RTL8366S_PHY_NO_OFFSET)) |
 371               ((page << RTL8366S_PHY_PAGE_OFFSET) & RTL8366S_PHY_PAGE_MASK) |
 372               (addr & RTL8366S_PHY_REG_MASK);
 373
 374         ret = rtl8366_smi_write_reg(smi, reg, data);
 375         if (ret)
 376                 return ret;
 377
 378         return 0;
 379 }
 380
 381 static int rtl8366_get_mib_counter(struct rtl8366_smi *smi, int counter,
 382                                    int port, unsigned long long *val)
 383 {
 384         int i;
 385         int err;
 386         u32 addr, data;
 387         u64 mibvalue;
 388
 389         if (port > RTL8366S_NUM_PORTS || counter >= RTL8366S_MIB_COUNT)
 390                 return -EINVAL;
 391
 392         switch (rtl8366s_mib_counters[counter].base) {
 393         case 0:
 394                 addr = RTL8366S_MIB_COUNTER_BASE +
 395                        RTL8366S_MIB_COUNTER_PORT_OFFSET * port;
 396                 break;
 397
 398         case 1:
 399                 addr = RTL8366S_MIB_COUNTER_BASE2 +
 400                         RTL8366S_MIB_COUNTER_PORT_OFFSET2 * port;
 401                 break;
 402
 403         default:
 404                 return -EINVAL;
 405         }
 406
 407         addr += rtl8366s_mib_counters[counter].offset;
 408
 409         /*
 410          * Writing access counter address first
 411          * then ASIC will prepare 64bits counter wait for being retrived
 412          */
 413         data = 0; /* writing data will be discard by ASIC */
 414         err = rtl8366_smi_write_reg(smi, addr, data);
 415         if (err)
 416                 return err;
 417
 418         /* read MIB control register */
 419         err =  rtl8366_smi_read_reg(smi, RTL8366S_MIB_CTRL_REG, &data);
 420         if (err)
 421                 return err;
 422
 423         if (data & RTL8366S_MIB_CTRL_BUSY_MASK)
 424                 return -EBUSY;
 425
 426         if (data & RTL8366S_MIB_CTRL_RESET_MASK)
 427                 return -EIO;
 428
 429         mibvalue = 0;
 430         for (i = rtl8366s_mib_counters[counter].length; i > 0; i--) {
 431                 err = rtl8366_smi_read_reg(smi, addr + (i - 1), &data);
 432                 if (err)
 433                         return err;
 434
 435                 mibvalue = (mibvalue << 16) | (data & 0xFFFF);
 436         }
 437
 438         *val = mibvalue;
 439         return 0;
 440 }
 441
 442 static int rtl8366s_get_vlan_4k(struct rtl8366_smi *smi, u32 vid,
 443                                 struct rtl8366_vlan_4k *vlan4k)
 444 {
 445         u32 data[2];
 446         int err;
 447         int i;
 448
 449         memset(vlan4k, '\0', sizeof(struct rtl8366_vlan_4k));
 450
 451         if (vid >= RTL8366S_NUM_VIDS)
 452                 return -EINVAL;
 453
 454         /* write VID */
 455         err = rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TABLE_WRITE_BASE,
 456                                     vid & RTL8366S_VLAN_VID_MASK);
 457         if (err)
 458                 return err;
 459
 460         /* write table access control word */
 461         err = rtl8366_smi_write_reg(smi, RTL8366S_TABLE_ACCESS_CTRL_REG,
 462                                     RTL8366S_TABLE_VLAN_READ_CTRL);
 463         if (err)
 464                 return err;
 465
 466         for (i = 0; i < 2; i++) {
 467                 err = rtl8366_smi_read_reg(smi,
 468                                            RTL8366S_VLAN_TABLE_READ_BASE + i,
 469                                            &data[i]);
 470                 if (err)
 471                         return err;
 472         }
 473
 474         vlan4k->vid = vid;
 475         vlan4k->untag = (data[1] >> RTL8366S_VLAN_UNTAG_SHIFT) &
 476                         RTL8366S_VLAN_UNTAG_MASK;
 477         vlan4k->member = data[1] & RTL8366S_VLAN_MEMBER_MASK;
 478         vlan4k->fid = (data[1] >> RTL8366S_VLAN_FID_SHIFT) &
 479                         RTL8366S_VLAN_FID_MASK;
 480
 481         return 0;
 482 }
 483
 484 static int rtl8366s_set_vlan_4k(struct rtl8366_smi *smi,
 485                                 const struct rtl8366_vlan_4k *vlan4k)
 486 {
 487         u32 data[2];
 488         int err;
 489         int i;
 490
 491         if (vlan4k->vid >= RTL8366S_NUM_VIDS ||
 492             vlan4k->member > RTL8366S_VLAN_MEMBER_MASK ||
 493             vlan4k->untag > RTL8366S_VLAN_UNTAG_MASK ||
 494             vlan4k->fid > RTL8366S_FIDMAX)
 495                 return -EINVAL;
 496
 497         data[0] = vlan4k->vid & RTL8366S_VLAN_VID_MASK;
 498         data[1] = (vlan4k->member & RTL8366S_VLAN_MEMBER_MASK) |
 499                   ((vlan4k->untag & RTL8366S_VLAN_UNTAG_MASK) <<
 500                         RTL8366S_VLAN_UNTAG_SHIFT) |
 501                   ((vlan4k->fid & RTL8366S_VLAN_FID_MASK) <<
 502                         RTL8366S_VLAN_FID_SHIFT);
 503
 504         for (i = 0; i < 2; i++) {
 505                 err = rtl8366_smi_write_reg(smi,
 506                                             RTL8366S_VLAN_TABLE_WRITE_BASE + i,
 507                                             data[i]);
 508                 if (err)
 509                         return err;
 510         }
 511
 512         /* write table access control word */
 513         err = rtl8366_smi_write_reg(smi, RTL8366S_TABLE_ACCESS_CTRL_REG,
 514                                     RTL8366S_TABLE_VLAN_WRITE_CTRL);
 515
 516         return err;
 517 }
 518
 519 static int rtl8366s_get_vlan_mc(struct rtl8366_smi *smi, u32 index,
 520                                 struct rtl8366_vlan_mc *vlanmc)
 521 {
 522         u32 data[2];
 523         int err;
 524         int i;
 525
 526         memset(vlanmc, '\0', sizeof(struct rtl8366_vlan_mc));
 527
 528         if (index >= RTL8366S_NUM_VLANS)
 529                 return -EINVAL;
 530
 531         for (i = 0; i < 2; i++) {
 532                 err = rtl8366_smi_read_reg(smi,
 533                                            RTL8366S_VLAN_MC_BASE(index) + i,
 534                                            &data[i]);
 535                 if (err)
 536                         return err;
 537         }
 538
 539         vlanmc->vid = data[0] & RTL8366S_VLAN_VID_MASK;
 540         vlanmc->priority = (data[0] >> RTL8366S_VLAN_PRIORITY_SHIFT) &
 541                            RTL8366S_VLAN_PRIORITY_MASK;
 542         vlanmc->untag = (data[1] >> RTL8366S_VLAN_UNTAG_SHIFT) &
 543                         RTL8366S_VLAN_UNTAG_MASK;
 544         vlanmc->member = data[1] & RTL8366S_VLAN_MEMBER_MASK;
 545         vlanmc->fid = (data[1] >> RTL8366S_VLAN_FID_SHIFT) &
 546                       RTL8366S_VLAN_FID_MASK;
 547
 548         return 0;
 549 }
 550
 551 static int rtl8366s_set_vlan_mc(struct rtl8366_smi *smi, u32 index,
 552                                 const struct rtl8366_vlan_mc *vlanmc)
 553 {
 554         u32 data[2];
 555         int err;
 556         int i;
 557
 558         if (index >= RTL8366S_NUM_VLANS ||
 559             vlanmc->vid >= RTL8366S_NUM_VIDS ||
 560             vlanmc->priority > RTL8366S_PRIORITYMAX ||
 561             vlanmc->member > RTL8366S_VLAN_MEMBER_MASK ||
 562             vlanmc->untag > RTL8366S_VLAN_UNTAG_MASK ||
 563             vlanmc->fid > RTL8366S_FIDMAX)
 564                 return -EINVAL;
 565
 566         data[0] = (vlanmc->vid & RTL8366S_VLAN_VID_MASK) |
 567                   ((vlanmc->priority & RTL8366S_VLAN_PRIORITY_MASK) <<
 568                         RTL8366S_VLAN_PRIORITY_SHIFT);
 569         data[1] = (vlanmc->member & RTL8366S_VLAN_MEMBER_MASK) |
 570                   ((vlanmc->untag & RTL8366S_VLAN_UNTAG_MASK) <<
 571                         RTL8366S_VLAN_UNTAG_SHIFT) |
 572                   ((vlanmc->fid & RTL8366S_VLAN_FID_MASK) <<
 573                         RTL8366S_VLAN_FID_SHIFT);
 574
 575         for (i = 0; i < 2; i++) {
 576                 err = rtl8366_smi_write_reg(smi,
 577                                             RTL8366S_VLAN_MC_BASE(index) + i,
 578                                             data[i]);
 579                 if (err)
 580                         return err;
 581         }
 582
 583         return 0;
 584 }
 585
 586 static int rtl8366s_get_mc_index(struct rtl8366_smi *smi, int port, int *val)
 587 {
 588         u32 data;
 589         int err;
 590
 591         if (port >= RTL8366S_NUM_PORTS)
 592                 return -EINVAL;
 593
 594         err = rtl8366_smi_read_reg(smi, RTL8366S_PORT_VLAN_CTRL_REG(port),
 595                                    &data);
 596         if (err)
 597                 return err;
 598
 599         *val = (data >> RTL8366S_PORT_VLAN_CTRL_SHIFT(port)) &
 600                RTL8366S_PORT_VLAN_CTRL_MASK;
 601
 602         return 0;
 603 }
 604
 605 static int rtl8366s_set_mc_index(struct rtl8366_smi *smi, int port, int index)
 606 {
 607         if (port >= RTL8366S_NUM_PORTS || index >= RTL8366S_NUM_VLANS)
 608                 return -EINVAL;
 609
 610         return rtl8366_smi_rmwr(smi, RTL8366S_PORT_VLAN_CTRL_REG(port),
 611                                 RTL8366S_PORT_VLAN_CTRL_MASK <<
 612                                         RTL8366S_PORT_VLAN_CTRL_SHIFT(port),
 613                                 (index & RTL8366S_PORT_VLAN_CTRL_MASK) <<
 614                                         RTL8366S_PORT_VLAN_CTRL_SHIFT(port));
 615 }
 616
 617 static int rtl8366s_enable_vlan(struct rtl8366_smi *smi, int enable)
 618 {
 619         return rtl8366_smi_rmwr(smi, RTL8366S_SGCR, RTL8366S_SGCR_EN_VLAN,
 620                                 (enable) ? RTL8366S_SGCR_EN_VLAN : 0);
 621 }
 622
 623 static int rtl8366s_enable_vlan4k(struct rtl8366_smi *smi, int enable)
 624 {
 625         return rtl8366_smi_rmwr(smi, RTL8366S_VLAN_TB_CTRL_REG,
 626                                 1, (enable) ? 1 : 0);
 627 }
 628
 629 static int rtl8366s_is_vlan_valid(struct rtl8366_smi *smi, unsigned vlan)
 630 {
 631         unsigned max = RTL8366S_NUM_VLANS;
 632
 633         if (smi->vlan4k_enabled)
 634                 max = RTL8366S_NUM_VIDS - 1;
 635
 636         if (vlan == 0 || vlan >= max)
 637                 return 0;
 638
 639         return 1;
 640 }
 641
 642 static int rtl8366s_enable_port(struct rtl8366_smi *smi, int port, int enable)
 643 {
 644         return rtl8366_smi_rmwr(smi, RTL8366S_PECR, (1 << port),
 645                                 (enable) ? 0 : (1 << port));
 646 }
 647
 648 static int rtl8366s_sw_reset_mibs(struct switch_dev *dev,
 649                                   const struct switch_attr *attr,
 650                                   struct switch_val *val)
 651 {
 652         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 653
 654         return rtl8366_smi_rmwr(smi, RTL8366S_MIB_CTRL_REG, 0, (1 << 2));
 655 }
 656
 657 static int rtl8366s_sw_get_blinkrate(struct switch_dev *dev,
 658                                      const struct switch_attr *attr,
 659                                      struct switch_val *val)
 660 {
 661         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 662         u32 data;
 663
 664         rtl8366_smi_read_reg(smi, RTL8366S_LED_BLINKRATE_REG, &data);
 665
 666         val->value.i = (data & (RTL8366S_LED_BLINKRATE_MASK));
 667
 668         return 0;
 669 }
 670
 671 static int rtl8366s_sw_set_blinkrate(struct switch_dev *dev,
 672                                     const struct switch_attr *attr,
 673                                     struct switch_val *val)
 674 {
 675         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 676
 677         if (val->value.i >= 6)
 678                 return -EINVAL;
 679
 680         return rtl8366_smi_rmwr(smi, RTL8366S_LED_BLINKRATE_REG,
 681                                 RTL8366S_LED_BLINKRATE_MASK,
 682                                 val->value.i);
 683 }
 684
 685 static int rtl8366s_sw_get_max_length(struct switch_dev *dev,
 686                                         const struct switch_attr *attr,
 687                                         struct switch_val *val)
 688 {
 689         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 690         u32 data;
 691
 692         rtl8366_smi_read_reg(smi, RTL8366S_SGCR, &data);
 693
 694         val->value.i = ((data & (RTL8366S_SGCR_MAX_LENGTH_MASK)) >> 4);
 695
 696         return 0;
 697 }
 698
 699 static int rtl8366s_sw_set_max_length(struct switch_dev *dev,
 700                                         const struct switch_attr *attr,
 701                                         struct switch_val *val)
 702 {
 703         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 704         char length_code;
 705
 706         switch (val->value.i) {
 707                 case 0:
 708                         length_code = RTL8366S_SGCR_MAX_LENGTH_1522;
 709                         break;
 710                 case 1:
 711                         length_code = RTL8366S_SGCR_MAX_LENGTH_1536;
 712                         break;
 713                 case 2:
 714                         length_code = RTL8366S_SGCR_MAX_LENGTH_1552;
 715                         break;
 716                 case 3:
 717                         length_code = RTL8366S_SGCR_MAX_LENGTH_16000;
 718                         break;
 719                 default:
 720                         return -EINVAL;
 721         }
 722
 723         return rtl8366_smi_rmwr(smi, RTL8366S_SGCR,
 724                         RTL8366S_SGCR_MAX_LENGTH_MASK,
 725                         length_code);
 726 }
 727
 728 static int rtl8366s_sw_get_learning_enable(struct switch_dev *dev,
 729                                            const struct switch_attr *attr,
 730                                            struct switch_val *val)
 731 {
 732         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 733         u32 data;
 734
 735         rtl8366_smi_read_reg(smi,RTL8366S_SSCR0, &data);
 736         val->value.i = !data;
 737
 738         return 0;
 739 }
 740
 741
 742 static int rtl8366s_sw_set_learning_enable(struct switch_dev *dev,
 743                                            const struct switch_attr *attr,
 744                                            struct switch_val *val)
 745 {
 746         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 747         u32 portmask = 0;
 748         int err = 0;
 749
 750         if (!val->value.i)
 751                 portmask = RTL8366S_PORT_ALL;
 752
 753         /* set learning for all ports */
 754         REG_WR(smi, RTL8366S_SSCR0, portmask);
 755
 756         /* set auto ageing for all ports */
 757         REG_WR(smi, RTL8366S_SSCR1, portmask);
 758
 759         return 0;
 760 }
 761
 762 static int rtl8366s_sw_get_port_link(struct switch_dev *dev,
 763                                      int port,
 764                                      struct switch_port_link *link)
 765 {
 766         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 767         u32 data = 0;
 768         u32 speed;
 769
 770         if (port >= RTL8366S_NUM_PORTS)
 771                 return -EINVAL;
 772
 773         rtl8366_smi_read_reg(smi, RTL8366S_PORT_LINK_STATUS_BASE + (port / 2),
 774                              &data);
 775
 776         if (port % 2)
 777                 data = data >> 8;
 778
 779         link->link = !!(data & RTL8366S_PORT_STATUS_LINK_MASK);
 780         if (!link->link)
 781                 return 0;
 782
 783         link->duplex = !!(data & RTL8366S_PORT_STATUS_DUPLEX_MASK);
 784         link->rx_flow = !!(data & RTL8366S_PORT_STATUS_RXPAUSE_MASK);
 785         link->tx_flow = !!(data & RTL8366S_PORT_STATUS_TXPAUSE_MASK);
 786         link->aneg = !!(data & RTL8366S_PORT_STATUS_AN_MASK);
 787
 788         speed = (data & RTL8366S_PORT_STATUS_SPEED_MASK);
 789         switch (speed) {
 790         case 0:
 791                 link->speed = SWITCH_PORT_SPEED_10;
 792                 break;
 793         case 1:
 794                 link->speed = SWITCH_PORT_SPEED_100;
 795                 break;
 796         case 2:
 797                 link->speed = SWITCH_PORT_SPEED_1000;
 798                 break;
 799         default:
 800                 link->speed = SWITCH_PORT_SPEED_UNKNOWN;
 801                 break;
 802         }
 803
 804         return 0;
 805 }
 806
 807 static int rtl8366s_sw_set_port_led(struct switch_dev *dev,
 808                                     const struct switch_attr *attr,
 809                                     struct switch_val *val)
 810 {
 811         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 812         u32 data;
 813         u32 mask;
 814         u32 reg;
 815
 816         if (val->port_vlan >= RTL8366S_NUM_PORTS ||
 817             (1 << val->port_vlan) == RTL8366S_PORT_UNKNOWN)
 818                 return -EINVAL;
 819
 820         if (val->port_vlan == RTL8366S_PORT_NUM_CPU) {
 821                 reg = RTL8366S_LED_BLINKRATE_REG;
 822                 mask = 0xF << 4;
 823                 data = val->value.i << 4;
 824         } else {
 825                 reg = RTL8366S_LED_CTRL_REG;
 826                 mask = 0xF << (val->port_vlan * 4),
 827                 data = val->value.i << (val->port_vlan * 4);
 828         }
 829
 830         return rtl8366_smi_rmwr(smi, reg, mask, data);
 831 }
 832
 833 static int rtl8366s_sw_get_port_led(struct switch_dev *dev,
 834                                     const struct switch_attr *attr,
 835                                     struct switch_val *val)
 836 {
 837         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 838         u32 data = 0;
 839
 840         if (val->port_vlan >= RTL8366S_NUM_LEDGROUPS)
 841                 return -EINVAL;
 842
 843         rtl8366_smi_read_reg(smi, RTL8366S_LED_CTRL_REG, &data);
 844         val->value.i = (data >> (val->port_vlan * 4)) & 0x000F;
 845
 846         return 0;
 847 }
 848
 849 static int rtl8366s_sw_reset_port_mibs(struct switch_dev *dev,
 850                                        const struct switch_attr *attr,
 851                                        struct switch_val *val)
 852 {
 853         struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
 854
 855         if (val->port_vlan >= RTL8366S_NUM_PORTS)
 856                 return -EINVAL;
 857
 858
 859         return rtl8366_smi_rmwr(smi, RTL8366S_MIB_CTRL_REG,
 860                                 0, (1 << (val->port_vlan + 3)));
 861 }
 862
 863 static struct switch_attr rtl8366s_globals[] = {
 864         {
 865                 .type = SWITCH_TYPE_INT,
 866                 .name = "enable_learning",
 867                 .description = "Enable learning, enable aging",
 868                 .set = rtl8366s_sw_set_learning_enable,
 869                 .get = rtl8366s_sw_get_learning_enable,
 870                 .max = 1,
 871         }, {
 872                 .type = SWITCH_TYPE_INT,
 873                 .name = "enable_vlan",
 874                 .description = "Enable VLAN mode",
 875                 .set = rtl8366_sw_set_vlan_enable,
 876                 .get = rtl8366_sw_get_vlan_enable,
 877                 .max = 1,
 878                 .ofs = 1
 879         }, {
 880                 .type = SWITCH_TYPE_INT,
 881                 .name = "enable_vlan4k",
 882                 .description = "Enable VLAN 4K mode",
 883                 .set = rtl8366_sw_set_vlan_enable,
 884                 .get = rtl8366_sw_get_vlan_enable,
 885                 .max = 1,
 886                 .ofs = 2
 887         }, {
 888                 .type = SWITCH_TYPE_NOVAL,
 889                 .name = "reset_mibs",
 890                 .description = "Reset all MIB counters",
 891                 .set = rtl8366s_sw_reset_mibs,
 892         }, {
 893                 .type = SWITCH_TYPE_INT,
 894                 .name = "blinkrate",
 895                 .description = "Get/Set LED blinking rate (0 = 43ms, 1 = 84ms,"
 896                 " 2 = 120ms, 3 = 170ms, 4 = 340ms, 5 = 670ms)",
 897                 .set = rtl8366s_sw_set_blinkrate,
 898                 .get = rtl8366s_sw_get_blinkrate,
 899                 .max = 5
 900         }, {
 901                 .type = SWITCH_TYPE_INT,
 902                 .name = "max_length",
 903                 .description = "Get/Set the maximum length of valid packets"
 904                 " (0 = 1522, 1 = 1536, 2 = 1552, 3 = 16000 (9216?))",
 905                 .set = rtl8366s_sw_set_max_length,
 906                 .get = rtl8366s_sw_get_max_length,
 907                 .max = 3,
 908         },
 909 };
 910
 911 static struct switch_attr rtl8366s_port[] = {
 912         {
 913                 .type = SWITCH_TYPE_NOVAL,
 914                 .name = "reset_mib",
 915                 .description = "Reset single port MIB counters",
 916                 .set = rtl8366s_sw_reset_port_mibs,
 917         }, {
 918                 .type = SWITCH_TYPE_STRING,
 919                 .name = "mib",
 920                 .description = "Get MIB counters for port",
 921                 .max = 33,
 922                 .set = NULL,
 923                 .get = rtl8366_sw_get_port_mib,
 924         }, {
 925                 .type = SWITCH_TYPE_INT,
 926                 .name = "led",
 927                 .description = "Get/Set port group (0 - 3) led mode (0 - 15)",
 928                 .max = 15,
 929                 .set = rtl8366s_sw_set_port_led,
 930                 .get = rtl8366s_sw_get_port_led,
 931         },
 932 };
 933
 934 static struct switch_attr rtl8366s_vlan[] = {
 935         {
 936                 .type = SWITCH_TYPE_STRING,
 937                 .name = "info",
 938                 .description = "Get vlan information",
 939                 .max = 1,
 940                 .set = NULL,
 941                 .get = rtl8366_sw_get_vlan_info,
 942         }, {
 943                 .type = SWITCH_TYPE_INT,
 944                 .name = "fid",
 945                 .description = "Get/Set vlan FID",
 946                 .max = RTL8366S_FIDMAX,
 947                 .set = rtl8366_sw_set_vlan_fid,
 948                 .get = rtl8366_sw_get_vlan_fid,
 949         },
 950 };
 951
 952 static const struct switch_dev_ops rtl8366_ops = {
 953         .attr_global = {
 954                 .attr = rtl8366s_globals,
 955                 .n_attr = ARRAY_SIZE(rtl8366s_globals),
 956         },
 957         .attr_port = {
 958                 .attr = rtl8366s_port,
 959                 .n_attr = ARRAY_SIZE(rtl8366s_port),
 960         },
 961         .attr_vlan = {
 962                 .attr = rtl8366s_vlan,
 963                 .n_attr = ARRAY_SIZE(rtl8366s_vlan),
 964         },
 965
 966         .get_vlan_ports = rtl8366_sw_get_vlan_ports,
 967         .set_vlan_ports = rtl8366_sw_set_vlan_ports,
 968         .get_port_pvid = rtl8366_sw_get_port_pvid,
 969         .set_port_pvid = rtl8366_sw_set_port_pvid,
 970         .reset_switch = rtl8366_sw_reset_switch,
 971         .get_port_link = rtl8366s_sw_get_port_link,
 972 };
 973
 974 static int rtl8366s_switch_init(struct rtl8366_smi *smi)
 975 {
 976         struct switch_dev *dev = &smi->sw_dev;
 977         int err;
 978
 979         dev->name = "RTL8366S";
 980         dev->cpu_port = RTL8366S_PORT_NUM_CPU;
 981         dev->ports = RTL8366S_NUM_PORTS;
 982         dev->vlans = RTL8366S_NUM_VIDS;
 983         dev->ops = &rtl8366_ops;
 984         dev->alias = dev_name(smi->parent);
 985
 986         err = register_switch(dev, NULL);
 987         if (err)
 988                 dev_err(smi->parent, "switch registration failed\n");
 989
 990         return err;
 991 }
 992
 993 static void rtl8366s_switch_cleanup(struct rtl8366_smi *smi)
 994 {
 995         unregister_switch(&smi->sw_dev);
 996 }
 997
 998 static int rtl8366s_mii_read(struct mii_bus *bus, int addr, int reg)
 999 {
1000         struct rtl8366_smi *smi = bus->priv;
1001         u32 val = 0;
1002         int err;
1003
1004         err = rtl8366s_read_phy_reg(smi, addr, 0, reg, &val);
1005         if (err)
1006                 return 0xffff;
1007
1008         return val;
1009 }
1010
1011 static int rtl8366s_mii_write(struct mii_bus *bus, int addr, int reg, u16 val)
1012 {
1013         struct rtl8366_smi *smi = bus->priv;
1014         u32 t;
1015         int err;
1016
1017         err = rtl8366s_write_phy_reg(smi, addr, 0, reg, val);
1018         /* flush write */
1019         (void) rtl8366s_read_phy_reg(smi, addr, 0, reg, &t);
1020
1021         return err;
1022 }
1023
1024 static int rtl8366s_detect(struct rtl8366_smi *smi)
1025 {
1026         u32 chip_id = 0;
1027         u32 chip_ver = 0;
1028         int ret;
1029
1030         ret = rtl8366_smi_read_reg(smi, RTL8366S_CHIP_ID_REG, &chip_id);
1031         if (ret) {
1032                 dev_err(smi->parent, "unable to read chip id\n");
1033                 return ret;
1034         }
1035
1036         switch (chip_id) {
1037         case RTL8366S_CHIP_ID_8366:
1038                 break;
1039         default:
1040                 dev_err(smi->parent, "unknown chip id (%04x)\n", chip_id);
1041                 return -ENODEV;
1042         }
1043
1044         ret = rtl8366_smi_read_reg(smi, RTL8366S_CHIP_VERSION_CTRL_REG,
1045                                    &chip_ver);
1046         if (ret) {
1047                 dev_err(smi->parent, "unable to read chip version\n");
1048                 return ret;
1049         }
1050
1051         dev_info(smi->parent, "RTL%04x ver. %u chip found\n",
1052                  chip_id, chip_ver & RTL8366S_CHIP_VERSION_MASK);
1053
1054         return 0;
1055 }
1056
1057 static struct rtl8366_smi_ops rtl8366s_smi_ops = {
1058         .detect         = rtl8366s_detect,
1059         .reset_chip     = rtl8366s_reset_chip,
1060         .setup          = rtl8366s_setup,
1061
1062         .mii_read       = rtl8366s_mii_read,
1063         .mii_write      = rtl8366s_mii_write,
1064
1065         .get_vlan_mc    = rtl8366s_get_vlan_mc,
1066         .set_vlan_mc    = rtl8366s_set_vlan_mc,
1067         .get_vlan_4k    = rtl8366s_get_vlan_4k,
1068         .set_vlan_4k    = rtl8366s_set_vlan_4k,
1069         .get_mc_index   = rtl8366s_get_mc_index,
1070         .set_mc_index   = rtl8366s_set_mc_index,
1071         .get_mib_counter = rtl8366_get_mib_counter,
1072         .is_vlan_valid  = rtl8366s_is_vlan_valid,
1073         .enable_vlan    = rtl8366s_enable_vlan,
1074         .enable_vlan4k  = rtl8366s_enable_vlan4k,
1075         .enable_port    = rtl8366s_enable_port,
1076 };
1077
1078 static int rtl8366s_probe(struct platform_device *pdev)
1079 {
1080         static int rtl8366_smi_version_printed;
1081         struct rtl8366_smi *smi;
1082         int err;
1083
1084         if (!rtl8366_smi_version_printed++)
1085                 printk(KERN_NOTICE RTL8366S_DRIVER_DESC
1086                        " version " RTL8366S_DRIVER_VER"\n");
1087
1088         smi = rtl8366_smi_probe(pdev);
1089         if (!smi)
1090                 return -ENODEV;
1091
1092         smi->clk_delay = 10;
1093         smi->cmd_read = 0xa9;
1094         smi->cmd_write = 0xa8;
1095         smi->ops = &rtl8366s_smi_ops;
1096         smi->cpu_port = RTL8366S_PORT_NUM_CPU;
1097         smi->num_ports = RTL8366S_NUM_PORTS;
1098         smi->num_vlan_mc = RTL8366S_NUM_VLANS;
1099         smi->mib_counters = rtl8366s_mib_counters;
1100         smi->num_mib_counters = ARRAY_SIZE(rtl8366s_mib_counters);
1101
1102         err = rtl8366_smi_init(smi);
1103         if (err)
1104                 goto err_free_smi;
1105
1106         platform_set_drvdata(pdev, smi);
1107
1108         err = rtl8366s_switch_init(smi);
1109         if (err)
1110                 goto err_clear_drvdata;
1111
1112         return 0;
1113
1114  err_clear_drvdata:
1115         platform_set_drvdata(pdev, NULL);
1116         rtl8366_smi_cleanup(smi);
1117  err_free_smi:
1118         kfree(smi);
1119         return err;
1120 }
1121
1122 static int rtl8366s_remove(struct platform_device *pdev)
1123 {
1124         struct rtl8366_smi *smi = platform_get_drvdata(pdev);
1125
1126         if (smi) {
1127                 rtl8366s_switch_cleanup(smi);
1128                 platform_set_drvdata(pdev, NULL);
1129                 rtl8366_smi_cleanup(smi);
1130                 kfree(smi);
1131         }
1132
1133         return 0;
1134 }
1135
1136 #ifdef CONFIG_OF
1137 static const struct of_device_id rtl8366s_match[] = {
1138         { .compatible = "realtek,rtl8366s" },
1139         {},
1140 };
1141 MODULE_DEVICE_TABLE(of, rtl8366s_match);
1142 #endif
1143
1144 static struct platform_driver rtl8366s_driver = {
1145         .driver = {
1146                 .name           = RTL8366S_DRIVER_NAME,
1147                 .owner          = THIS_MODULE,
1148 #ifdef CONFIG_OF
1149                 .of_match_table = of_match_ptr(rtl8366s_match),
1150 #endif
1151         },
1152         .probe          = rtl8366s_probe,
1153         .remove         = rtl8366s_remove,
1154 };
1155
1156 static int __init rtl8366s_module_init(void)
1157 {
1158         return platform_driver_register(&rtl8366s_driver);
1159 }
1160 module_init(rtl8366s_module_init);
1161
1162 static void __exit rtl8366s_module_exit(void)
1163 {
1164         platform_driver_unregister(&rtl8366s_driver);
1165 }
1166 module_exit(rtl8366s_module_exit);
1167
1168 MODULE_DESCRIPTION(RTL8366S_DRIVER_DESC);
1169 MODULE_VERSION(RTL8366S_DRIVER_VER);
1170 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
1171 MODULE_AUTHOR("Antti Seppälä <a.seppala@gmail.com>");
1172 MODULE_LICENSE("GPL v2");
1173 MODULE_ALIAS("platform:" RTL8366S_DRIVER_NAME);